CN202217153U - Measure and control circuit for embedded 1553B remote terminal - Google Patents
Measure and control circuit for embedded 1553B remote terminal Download PDFInfo
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- CN202217153U CN202217153U CN2011202138592U CN201120213859U CN202217153U CN 202217153 U CN202217153 U CN 202217153U CN 2011202138592 U CN2011202138592 U CN 2011202138592U CN 201120213859 U CN201120213859 U CN 201120213859U CN 202217153 U CN202217153 U CN 202217153U
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Abstract
The utility model relates to a measure and control circuit for embedded 1553B remote terminal. The measure and control circuit enables the switch value input and output circuit design of the embedded 1553 bus remote terminal to be realized through hardware, and simultaneously is provided with an AD converting circuit used for analog signal sampling and a ferroelectric memory FRAM used for currentless memory of measure information and product attribute information, i.e., when the power supply of the circuit is powered off, the memory information can not be lost. The measure and control circuit for embedded 1553B remote terminal dispenses with the support of a CPU and related devices thereof, and dispenses with developing special software to complete same functions, thereby providing basis for simplifying system design, and enables hardware complexity to be reduced through dispensing with the CPU and other supporting thereof, and is helpful for device design, manufacture and fault removal, thereby reducing direct device cost and software development cost and increasing system reliability.
Description
Technical field
The utility model relates to carrier rocket electronic comprehensive system technical field, particularly relates to a kind of telemetry circuit of embedded 1553B remote terminal.
Background technology
After the 1553B bus arrives the carrier rocket electronic comprehensive system as system integration tool applications; Unit (like ICU) provides 1553B terminal interface on the requirement bullet; Receive from the specific control output of the instruction completion of flight control computer through bus, and test result is sent flight control computer with the test result of this locality through bus.At present, the conceptual design circuit board of a kind of microcomputer system based on CPU of domestic common employing through design and load special software, is realized receiving control data and sending test data through the 1553B bus, accomplishes the function that system assignment is given.In fact, its function of unit on a part of bullet is realized analog quantity and switching value test signals samples, the output of switching value control signal in fact, itself need not accomplish complex calculations.Adopting the shortcoming based on the scheme of the microcomputer system of CPU for this part unit is the hardware more complicated, also needs the software of special, design, produces and test need expend more manpower and materials.In addition, different carrier rocket models have unit on the very most bullet, and its function and performance are roughly the same; Even same model, it is roughly the same that its function of part unit is also arranged.General model unit design all is for the specific function that satisfies system assignment designs, even two roughly the same units of function also design respectively, its electric interfaces and data-interface are not general yet, have the repetition that to a certain degree designs.In addition, general model unit itself can not be preserved product informations such as historical detecting information and device numbering, the date of production.
The utility model content
The purpose of the utility model is to overcome the above-mentioned deficiency of prior art; A kind of telemetry circuit of embedded 1553B remote terminal is provided, and this telemetry circuit has reduced CPU and has supported device, has reduced hardware complexity; More help device design, manufacturing and troubleshooting; Reduced device cost and software development cost, improved the reliability of system, and provided the foundation for the simplified design of system.
The above-mentioned purpose of the utility model is achieved through following technical scheme:
A kind of telemetry circuit of embedded 1553B remote terminal; Comprise a CPLD, the 2nd CPLD, Bus Interface Chip BPIC, drive DR, storer FRAM, analog to digital conversion ADC and clock source CLOCK; Wherein Bus Interface Chip BPIC is the electrical interface of telemetry circuit and 1553B bus; And Bus Interface Chip BPIC is connected with a CPLD, the 2nd CPLD and clock source CLOCK respectively; The one CPLD also connects and drives DR, and the 2nd CPLD is connected storage FRAM and analog to digital conversion ADC respectively also, and between a CPLD and the 2nd CPLD also realization be connected;
The one CPLD deciphers, latchs back control delivery outlet according to the switching value control data that Bus Interface Chip BPIC receives from the 1553B bus interface, realizes switching value instruction output through driving DR amplification rear drive external loading; Gather the interpretation of switching value input signal in real time relatively simultaneously; If arbitrary switching value input signal changes; Then said switching value input signal is latched and supply Bus Interface Chip BPIC visit; If Bus Interface Chip BPIC visit surpasses 3 times and the switching value input signal no longer changes, then export the state that control signal is appointed as Bus Interface Chip BPIC " doing ";
The 2nd CPLD controls the work of analog to digital conversion ADC, obtains the transformation result of analog to digital conversion ADC, and said transformation result is latched, and supplies Bus Interface Chip BPIC visit; The work of control store FRAM simultaneously realizes the storage and the transmission of product test information and attribute information;
Bus Interface Chip BPIC is that telemetry circuit provides 1553B bus electric interfaces, and the need of work outside provides clock source CLOCK;
Storer FRAM is that telemetry circuit provides storage space, storage detecting information and attribute information;
Analog to digital conversion ADC converts the analog quantity test signal that receives the digital measurement trial signal into and exports to the 2nd CPLD;
Driving DR is that telemetry circuit provides driving.
In the telemetry circuit of above-mentioned embedded 1553B remote terminal, the model of Bus Interface Chip BPIC is BU-64703.
In the telemetry circuit of above-mentioned embedded 1553B remote terminal, the model of a CPLD and the 2nd CPLD is XCR3512.
In the telemetry circuit of above-mentioned embedded 1553B remote terminal, driving DR is 6 rp-drives, and model is SNJ5406FK.
In the telemetry circuit of above-mentioned embedded 1553B remote terminal, storer FRAM is a ferroelectric memory, and model is FM22L16.
In the telemetry circuit of above-mentioned embedded 1553B remote terminal, the model of analog to digital conversion ADC is MAX1265BEEI.
The utility model compared with prior art has following advantage:
(1) the utility model telemetry circuit is realized the switching value imput output circuit design of embedded 1553 bus remote terminals through hardware; Be equipped with the modulus A/D convertor circuit simultaneously and realize the sampling of simulating signal; Be equipped with the non-charged storage that ferroelectric memory FRAM realizes detecting information and product attribute information, promptly canned data can not lost after the device looses power, need not CPU and related device support thereof; Need not the software of developing special and accomplish identical functions, for the simplified design of system provides the foundation;
(2) the utility model telemetry circuit has reduced CPU and has supported device in the design proposal of 1553B EBI and control circuit board; Reduced hardware complexity; More help device design, manufacturing and troubleshooting, reduced device cost and software development cost, improved the reliability of system;
(3) the utility model is on unit and external digital Interface design; Adopt " transparent " to change design; Through the CPLD programming local IO of unit and flight control computer control code (design redundanat code) are set up mapping relations one to one, the switching value instruction delivery outlet of flight control computer control unit is equivalent to control the local IO mouth of flight control computer, and software and hardware links such as unit and bus are transparent fully to flight control computer; Instruction is exported and is closed by flight control computer and directly controls; Its concrete function is specified through flight control computer software, and unit need not to be concerned about concrete command function, helps improving product versatility;
(4) design of the utility model telemetry circuit is succinct; Versatility and optimal design have been taken into account; Can be applicable to occasions such as detecting information obtains on sequential control, nozzle switch control and the bullet in the different model carrier rocket electronic comprehensive system; For the simplified design of system, modularization design provide technical foundation, help increasing work efficiency with product quality, accelerate the development Development Schedule, practice thrift cost etc.
Description of drawings
Fig. 1 is the utility model telemetry circuit theory diagram;
Fig. 2 realizes steering order for the utility model CPLD " three get two " logical design figure.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the utility model is described in further detail:
Fig. 1 is the utility model telemetry circuit theory diagram; Can know that by figure telemetry circuit comprises a CPLD, the 2nd CPLD, Bus Interface Chip BPIC, drives DR, storer FRAM, analog to digital conversion ADC and clock source CLOCK; Wherein Bus Interface Chip BPIC is the electrical interface of telemetry circuit and 1553B bus; And Bus Interface Chip BPIC is connected with a CPLD, the 2nd CPLD and clock source CLOCK respectively; The one CPLD also connects and drives DR, and the 2nd CPLD is connected storage FRAM and analog to digital conversion ADC respectively also, and between a CPLD and the 2nd CPLD also realization be connected; Above-mentioned each device connects through the PCB cabling on the PCB printed circuit board.
The function of the utility model telemetry circuit comprises following several aspect:
1) 1553B bus electric interfaces is provided;
2) instruction control of receiving through bus interface converts local switching value output into;
3) the local switching value of sampling input port data send it through the 1553B bus;
4) adopt local analog quantity input interface data, it is sent through the 1553B bus;
5) through 1553B bus interface Acceptance Tests data and product attribute data and be stored to FRAM;
6) through the 1553B bus test data and product attribute data are sent.
The function that wherein above-mentioned each components and parts of each circuit are mainly realized is following:
The major function of CPLD is according to the sequential of shaking hands between BPIC, ADC, the FRAM; The latching of design data, decoding, steering logic; IC chip collaborative works such as control BPIC, ADC, FRAM; Realize circuit function, realize switching value output, switching value input test, analog quantity test and product test information and attribute information storage and sending function.Be specially:
The one CPLD deciphers, latchs back control delivery outlet according to the switching value control data that Bus Interface Chip BPIC receives from the 1553B bus interface, realizes switching value instruction output through driving DR amplification rear drive external loading; Gather the interpretation of switching value input signal relatively from the 1553B Bus Real Time simultaneously; If arbitrary switching value input signal changes; Then said switching value input signal is latched and supply Bus Interface Chip BPIC visit; If Bus Interface Chip BPIC visit surpasses 3 times and or else the switching value input signal changes, then export the state that control signal is appointed as Bus Interface Chip BPIC " doing ";
The 2nd CPLD controls the work of analog to digital conversion ADC, obtains the transformation result of analog to digital conversion ADC, and said transformation result is latched, and supplies Bus Interface Chip BPIC visit; Control store FRAM work simultaneously realizes the storage and the transmission of product test information and attribute information;
Bus Interface Chip BPIC is that telemetry circuit provides 1553B bus electric interfaces, and the need of work outside provides clock source CLOCK;
Storer FRAM is that telemetry circuit provides storage space, storage detecting information and attribute information;
Analog to digital conversion ADC converts the analog quantity test signal that receives into the digital measurement trial signal and supplies the 2nd CPLD;
Driving DR is that telemetry circuit provides driving.
On circuit external digital Interface design; Adopted " transparent " to change scheme of designing, with a certain position of each switching value output terminal, in order to improve reliability corresponding to control data; Through CPLD steering order is realized " three get two " after the logical design, the instruction of output switching value.User's (being flight control computer) can directly control ICU (as 1553B bus remote terminal through bus as 1553B bus controller (BC); RT) unlatching of a certain output or close; Be equivalent to control local IO mouth, software and hardware links such as unit and 1553B bus are transparent fully to user's (being flight control computer).Be illustrated in figure 2 as the utility model digital interface design diagram.
Following table 1 is main components and parts model and the manufacturer of using in the utility model:
Table 1
The realization of each function of telemetry circuit realizes through the CPLD programming in the utility model, specifically describes as follows:
(1), time timing and time Synchronization Design
The time clocking capability is for carrying out direct census to clock input CLOCK (16MHz), and when the clock count value reaches 80000, then system timing time T adds up 1 and with the zero clearing of clock count value, and restarts counting.So circulation, can obtain the resolution rate is the system timing time value T of 5ms.
Stamp the timestamp that has identical time zero with BC when the purpose of time synchronized design is the test signal that provides for the utility model circuit, be convenient to data analysis.The CPLD design specifically is embodied as: the bus data instruction that real-time judge BPIC receives through bus interface; If when receiving the 1553B synchronous mode order of band data word (resolution is 5ms); The moment of T for the representative of synchrodata word will be set the current time in system, realize that system time is synchronous.
(2), the switching value sampled data is sent
This function is united realization by a CPLD and the 2nd CPLD.Switching value test data form is referring to table 1, and data word in front is at first sent on bus in the table, and the corresponding place value of data word is tested useful signal for " 1 " expression in the table, for useful signal is not tested in " 0 " expression.Wherein message name RT5-SA1-6 → BC representes a RT5 (embodiment of the utility model circuit; The RT address is 5, and is variable), 6 words are sent (if be BC → RT5-SA1-6 to BC in subaddressing 1; Represent that then BC sends 6 words to RT5 subaddressing 1, following situation roughly the same).The one CPLD real-time sampling input port test data; When any one of data then latch it when changing; And sending the test data variable signal to the 2nd CPLD, the current system time T of record supplied BC to read as the data variation time after the 2nd CPLD received this signal.When the 2nd CPLD interpretation BPIC receives BC when sending retrieval command when BC order (send RT5-SA1-6 →); Timing node at preceding two words of transmission; Send BPIC to supply to send the test data transformation period that latchs; When a CPLD interpretation receives this order,, send BPIC to send test data word 1～examination data word 4 respectively at the timing node of back 4 words of transmission.
Simultaneously, the real-time interpretation of a CPLD, if this test data is read after 3 times by BC, the test data of sampling does not change, and is then effective to " hurrying " position of this subaddressing with crossing delivery outlet control BPIC.The invalid data that repeats will can not send BC with passing through bus, thereby save the 1553B flow bus.
Table 1
(3), the simulation test data are sent
Through the 2nd CPLD programming Control ADC work, obtain the ADC transformation result and it is latched, supply the BPIC visit, the test data message format is seen table 2.The ADC controlling Design realizes as follows:
1) if the clock timing value is 1, then puts 0, gating ADC through delivery outlet _ ADCS;
2) if the clock timing value is 3; Then put 0 through delivery outlet _ ADWR; The ADC write signal is equipped with effect; Through the adc data bus ADC channel selecting control word is write ADC simultaneously, and conversion ADC channel selecting control word (accomplishing the test of two-way analog quantity through conversion channel selecting control word), the ADC conversion started.
3) if the clock timing value is 7, then the 2nd CPLD delivery outlet ADCS, ADWR put 1,
4) if the clock timing value is 8, then the 2nd CPLD is a high-impedance state with the adc data bus recovery.
5) ADC EOC mark _ ADINT effectively (being " 0 ") is waited in inquiry in real time; If _ ADINT is effectively then after 3 clock period; With the 2nd CPLD delivery outlet _ ADRD, _ ADCS is equipped with effect (for " 0 "), and latchs through the current SELCH of adc data bus ADC transformation result.The next clock period with delivery outlet _ ADRD, _ ADCS puts invalid (for " 1 ").
6) so circulate, obtain the ADC transformation result of two TCH test channels repeatedly.
7) when receiving the analog quantity test data, sends the 2nd CPLD interpretation BPIC (RT5-SA2-2 → when BC) instructing,, send BPIC to send current time in system, analog quantity test signal 1 and analog quantity test signal 2 according to specific timing node.
Table 2
(4), switching value output control
The 2nd CPLD real-time judge, if BPIC receive the switch control command (BC → RT5SA1-1), then with message carry out sending or close the output of respective switch amount after " three get two " logic determines with data word with 2 message datas that receive recently.This message definition is seen table 3.Corresponding place value is that " 1 " expression output is effective in the table, for output is closed in " 0 " expression.This message may command 16 way switch amounts output, other 54 way switch amount output control method is roughly the same no longer enumerated.
Table 3
(5), product attribute and detecting information access
Product attribute and detecting information access are realized by the 2nd CPLD programming Control BPIC and FRAM collaborative work.
1, product attribute and test storage information stores
This function (behind the BC → RT5SA28-32), is stored to FRAM, and upgrades current storage pointer, for Data Receiving is next time prepared for receiving the product attribute detecting information.
1) the 2nd CPLD real-time judge; If BPIC receives product attribute and test storage information stores order (BC → RT5SA28-32); To visit the FRAM address and be changed to current receiver address rRXSP, and in BPIC bus acknowledge signal _ DTACK valid period FRAM write enable signal FMWE and be equipped with effect;
2) if FMWE is effective, then FRAM read-write _ FMWR is changed to " 0 " in BPIC write signal _ ACE_MEMWR valid period, be FRAM with the effect state, otherwise be changed to " 1 ", be FRAM and read effective status;
3) during _ FMWR is for " 0 ", FRAM chip selection signal _ FMCE is equipped with effect;
4) in _ FMWE valid period, BPIC data bus value (being product attribute and detecting information) is write the FRAM data bus;
5) FRAM read-write _ FMWR rising edge adds up 1 with current storage pointer rRXSP constantly.
2, product attribute and test storage information are sent
This function is sent order and (behind the RT5SA28-32 → BC), the content (being product attribute and test storage information) of current transmission pointed FRAM is sent, upgrade and send pointer, for next information transmission is prepared for receiving product attribute and test storage information.
1) the 2nd CPLD real-time judge; If BPIC receives product attribute and test storage information and sends order (RT5SA28-32 → BC); To visit the FRAM address and be changed to current transmission address rTXSP, and FRAM chip selection signal _ FMCE will be equipped with effect in the BPIC bus acknowledge signal DTACK valid period;
2) if _ FMCE is effective, then in the BPIC output enable signal ACE_MEMOE valid period FRAM output enable signal _ FMOE is equipped with effect;
3), FRAM data bus (being product attribute and detecting information) is write the BPIC data bus supply it to send through the 1553B bus in FRAM output enable signal _ FMOE valid period;
4) at FRAM output enable signal _ FMOE rising edge constantly, current transmission pointer rTXSP is added up 1.
3, product attribute and test storage information stores and the initialization of transmission pointer
To send pointer rTXSP and storage pointer rRXSP clear 0 after powering on.
The above; Be merely the best embodiment of the utility model; But the protection domain of the utility model is not limited thereto; Any technician who is familiar with the present technique field is in the technical scope that the utility model discloses, and the variation that can expect easily or replacement all should be encompassed within the protection domain of the utility model.
The content of not doing to describe in detail in the utility model instructions belongs to this area professional and technical personnel's known technology.
Claims (6)
1. the telemetry circuit of an embedded 1553B remote terminal; It is characterized in that: comprise a CPLD, the 2nd CPLD, Bus Interface Chip BPIC, drive DR, storer FRAM, analog to digital conversion ADC and clock source CLOCK; Wherein Bus Interface Chip BPIC is the electrical interface of telemetry circuit and 1553B bus; And Bus Interface Chip BPIC is connected with a CPLD, the 2nd CPLD and clock source CLOCK respectively; The one CPLD also connects and drives DR, and the 2nd CPLD is connected storage FRAM and analog to digital conversion ADC respectively also, and between a CPLD and the 2nd CPLD also realization be connected; Bus Interface Chip BPIC is that telemetry circuit provides 1553B bus electric interfaces, and the need of work outside provides clock source CLOCK; Storer FRAM is that telemetry circuit provides storage space, storage detecting information and attribute information; Analog to digital conversion ADC converts the analog quantity test signal that receives into the digital measurement trial signal and supplies the 2nd CPLD to read; Driving DR is that telemetry circuit provides driving.
2. the telemetry circuit of a kind of embedded 1553B remote terminal according to claim 1 is characterized in that: the model of said Bus Interface Chip BPIC is BU-64703.
3. the telemetry circuit of a kind of embedded 1553B remote terminal according to claim 1 is characterized in that: the model of a said CPLD and the 2nd CPLD is XCR3512.
4. the telemetry circuit of a kind of embedded 1553B remote terminal according to claim 1 is characterized in that: said driving DR is 6 rp-drives, and model is SNJ5406FK.
5. the telemetry circuit of a kind of embedded 1553B remote terminal according to claim 1 is characterized in that: said storer FRAM is a ferroelectric memory, and model is FM22L16.
6. the telemetry circuit of a kind of embedded 1553B remote terminal according to claim 1 is characterized in that: the model of said analog to digital conversion ADC is MAX1265BEEI.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011202138592U CN202217153U (en) | 2011-06-22 | 2011-06-22 | Measure and control circuit for embedded 1553B remote terminal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011202138592U CN202217153U (en) | 2011-06-22 | 2011-06-22 | Measure and control circuit for embedded 1553B remote terminal |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076753A (en) * | 2012-12-27 | 2013-05-01 | 南京因泰莱电器股份有限公司 | Analog channel configurable method |
| CN103973386A (en) * | 2014-05-23 | 2014-08-06 | 哈尔滨工业大学 | Time aligning method for 1553B data and ADC data in data collecting system |
| CN106547601A (en) * | 2016-12-05 | 2017-03-29 | 北京航天自动控制研究所 | A kind of online software programming device and method |
| CN110320428A (en) * | 2019-07-01 | 2019-10-11 | 江西洪都航空工业集团有限责任公司 | A kind of Kind of Missile Control Computer interface automatization test system |
-
2011
- 2011-06-22 CN CN2011202138592U patent/CN202217153U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103076753A (en) * | 2012-12-27 | 2013-05-01 | 南京因泰莱电器股份有限公司 | Analog channel configurable method |
| CN103973386A (en) * | 2014-05-23 | 2014-08-06 | 哈尔滨工业大学 | Time aligning method for 1553B data and ADC data in data collecting system |
| CN103973386B (en) * | 2014-05-23 | 2016-09-28 | 哈尔滨工业大学 | 1553B data and the time unifying method of adc data in a kind of data collecting system |
| CN106547601A (en) * | 2016-12-05 | 2017-03-29 | 北京航天自动控制研究所 | A kind of online software programming device and method |
| CN106547601B (en) * | 2016-12-05 | 2019-09-13 | 北京航天自动控制研究所 | A kind of online software programming device and method |
| CN110320428A (en) * | 2019-07-01 | 2019-10-11 | 江西洪都航空工业集团有限责任公司 | A kind of Kind of Missile Control Computer interface automatization test system |
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