CN205103636U - Multi -axis motion control system - Google Patents

Abstract

The utility model discloses a multi -axis motion control system, the control mainboard, servo driver and the servo motor that constitute including host computer, interface converter, by signal input module, signal processing module and signal output module, be equipped with two port RAM, hand wheel module circuit in the signal input module, be equipped with DSP main control unit circuit, interface expander circuit, encoder counting circuit among the signal processing module, be equipped with DA converting circuit, amplifier circuit, motor interface circuit among the signal output circuit, the utility model discloses utilize the DSP chip as main control chip, accomplish signal transfer, processing and output work between each module, entire system adopts the conception modulaire structure, and furthest reduces the electromagnetic interference between different kinds of signals, has very important's meaning to the accuracy nature that improves the system, the utility model discloses simple structure, convenient operation can realize multiaxis control fast, improves the precision and the ability of numerical control system processing.

Description

A kind of multi-shaft motion control system

Technical field

The utility model relates to a kind of control system, particularly relates to a kind of multi-shaft motion control system.

Background technology

In the past few decades, multi-shaft motion control system grows out of nothing, development very fast; At present, started to develop some functions and all fairly perfect multi-shaft motion control system of performance abroad, corresponding kinetic control system technical merit is also higher, leads the working direction of Multi-axis motion control technology;

Compared with international most advanced level, the research of the multi-shaft motion control system that China is domestic is scarcely out of swaddling-clothes; Common mode inserts motion control card and I/O card on the bus slot of Industrial PC or common PC, is equipped with independently developed control software design and completes the basic function that digital control system requires;

From the development trend of digital control system, the concept of open control system is not fully aware of, do not solve the platform problem of open control system completely, not exclusively possesses the feature of opening, portability, interoperability, interchangeability and the extensibility that open system structural response has, and the institution system that adopts of each producer inconsistent, lack compatible and interchangeability each other, repair inconvenience, cause maintenance cost to raise; All be only limited to concrete physical layer to the description of architecture, really do not rise on theoretical level, thus each system hardware and software does not possess portability and interoperability.

Utility model content

The utility model, in order to make up the deficiencies in the prior art, meets the needs of prior art, provides a kind of multi-shaft motion control system, and this system architecture is simple, easy to operate, can realize multijoint control rapidly, improves precision and the ability of digital control system processing;

For achieving the above object, the technical scheme that the utility model is taked is:

A kind of multi-shaft motion control system, comprises host computer, interface convertor, control mainboard, servo-driver and servomotor; Described host computer is connected with interface convertor; Described interface convertor is connected with control mainboard; Described control mainboard is connected with servo-driver; Described servo-driver is connected with servomotor; It is characterized in that: described control mainboard comprises signal input module, signal processing module and signal output module; Dual port RAM, handwheel modular circuit is provided with in described signal input module; DSP main controller circuit, Interface Expanding circuit, encoder to count circuit is provided with in described signal processing module; D/A change-over circuit, amplifying circuit, motor interface circuit is provided with in described signal output apparatus; Described dual port RAM is connected with interface convertor by bus; Described handwheel modular circuit is connected with DSP main controller circuit; Described DSP main controller circuit is connecting interface expanded circuit, encoder to count circuit respectively; Described DSP main controller circuit is also connected with D/A change-over circuit; Described D/A change-over circuit is connected with amplifying circuit; Described amplifying circuit is connected with motor interface circuit; Described motor interface circuit is connected with servo-driver;

Further improvement, described dual port RAM is 8Kx16 twoport static ram chip, and its model is CY7C025;

Further improvement, described DSP main controller circuit comprises DSP control chip, reset circuit, crystal oscillation clock circuit, sheet outer SRAM circuit, jtag interface circuit, power circuit, real time clock circuit; Described DSP control chip is connected with reset circuit, crystal oscillation clock circuit, the outer SRAM circuit of sheet, jtag interface circuit, power circuit, real time clock circuit respectively;

Further improvement, the model of described DSP control chip is TMS320F2812;

Further improvement, described Interface Expanding circuit comprises storer and I/O expansion interface; Described I/O expansion interface is arranged on the surrounding of CPLD storer, and is connected with CPLD storer;

Further improvement, described storer comprises CPLD chip, CPLD reset circuit and emulation interface circuit; Described CPLD chip is connected with described reset circuit, emulation interface circuit respectively;

Further improvement, described encoder to count circuit comprises encoder feedback circuit and filtering circuit;

Further improvement, described encoder feedback circuit comprises fpga chip, FPGA power circuit, FPGA crystal oscillating circuit, chip external memory circuit, configuration bit selection circuit, FPGA reset circuit and FPGA relay indicating light circuit;

Further improvement, is provided with analog-digital chip in described D/A change-over circuit, and described analog-digital chip is the D/A converter of 12, and its model is DAC7725;

Further improvement, is provided with operation amplifier chip in described amplifying circuit, its model is LM324;

Compared with prior art, adopt such scheme, the beneficial effects of the utility model are: the utility model utilizes dsp chip as main control chip, complete the signal transmission between each module, process and output services; The circuit design of whole system, adopt modular design structure, ensure that the utility model product is when working environment changes, when not carrying out any hardware circuit amendment, in time can adjust the structure of self according to the change of external condition, meet the demand of different control system; In addition, adopt modular design structure, reduce the electromagnetic interference (EMI) between signal with different type to greatest extent, the accuracy tool improving system is of great significance.

Accompanying drawing explanation

Fig. 1 is structural representation of the present utility model;

Fig. 2 is electrical block diagram of the present utility model;

Fig. 3 is the connection block diagram of dual port RAM in the utility model;

Fig. 4 is handwheel timing chart in the utility model;

Fig. 5 is that in the utility model, handwheel interrupts process flow diagram;

Fig. 6 is DSP main controller circuit structural representation in the utility model;

Fig. 7 is the circuit construction of electric power schematic diagram in the utility model in DSP main controller circuit;

Fig. 8 is the crystal oscillating circuit structural representation in the utility model in DSP main controller circuit;

Fig. 9 is the jtag interface electrical block diagram in the utility model in DSP main controller circuit;

Figure 10 is the chip external memory electrical block diagram in the utility model in DSP main controller circuit;

Figure 11 is CPLD inner structure schematic diagram in the utility model;

Figure 12 is CPLD reset circuit structural representation in the utility model;

Figure 13 is emulation interface electrical block diagram in the utility model;

Figure 14 is FPGA circuit construction of electric power schematic diagram in the utility model;

Figure 15 is chip external memory electrical block diagram in the utility model;

Figure 16 is configuration bit selecting circuit structure schematic diagram in the utility model;

Figure 17 is the electrical block diagram that in the utility model, CPLD and DAC7725 connects;

Figure 18 is amplification circuit structure schematic diagram in the utility model;

Embodiment

Below in conjunction with drawings and Examples, the utility model is further illustrated.

As shown in Figure 1 and Figure 2, a kind of multi-shaft motion control system, comprises host computer, interface convertor, control mainboard, servo-driver and servomotor; Described host computer is connected with interface convertor; Described interface convertor is connected with control mainboard; Described control mainboard is connected with servo-driver; Described servo-driver is connected with servomotor; It is characterized in that: described control mainboard comprises signal input module, signal processing module and signal output module; Dual port RAM, handwheel modular circuit is provided with in described signal input module; DSP main controller circuit, Interface Expanding circuit, encoder to count circuit is provided with in described signal processing module; D/A change-over circuit, amplifying circuit, motor interface circuit is provided with in described signal output apparatus; Described dual port RAM is connected with interface convertor by bus; Described handwheel modular circuit is connected with DSP main controller circuit; Described DSP main controller circuit is connecting interface expanded circuit, encoder to count circuit respectively; Described DSP main controller circuit is also connected with D/A change-over circuit; Described D/A change-over circuit is connected with amplifying circuit; Described amplifying circuit is connected with motor interface circuit; Described motor interface circuit is connected with servo-driver;

Signal input module is the tie that system is connected with host computer, is responsible for carrying out exchanges data by bus and host computer, and completes the input of manual control signal; Be made up of dual port RAM circuit and handwheel modular circuit;

Signal processing module is the core of Multi-axis motion control hardware circuit, restructural and other some logic controls of control algolithm, system all realize in this module, mainly contain master controller DSP circuit, reconfigurable cell CPLD circuit and FPGA circuit composition, wherein DSP circuit completes the instruction code transmitted host computer and deals with the work and the realization of Fuzzy Adaptive PID Control algorithm, CPLD circuit completes the expansion of I/O interface and external memory storage, and FPGA circuit completes filtering and the tally function of encoder feedback signal;

Signal output module mainly completes D/A converting circuit and driven by servomotor signal exports, and is made up of D/A converting circuit, amplifying circuit and interface circuit;

1, dual port RAM

Described dual port RAM is 8Kx16 twoport static ram chip, and preferably, its model is CY7C025; This chip is produced by CYPRESS company, why selects this chip, is that top speed can reach 15ns because this chip has access speed soon; The complete asynchronous operation of each port, it has the address wire of two groups of full symmetrics, data line and control line, allows two CPU to conduct interviews to storer simultaneously; Its circuit structure be connected with host computer, DSP main controller circuit as shown in Figure 3;

In the connection of circuit, Multi-axis motion control end uses data line and the address wire of right side port, host computer uses data line and the address wire of left side port, DSP is used as the address wire be connected with dual port RAM by low order address line A0-A12, high address line A13-A18 carries out logic control input decoding scheme together with/XZCS0 pin, the data line of dual port RAM, the data line D0-D15 of D0-D15 with DSP is directly connected, UB pin and the drop-down direct ground connection of LB pin, do not use Busy signal can be unsettled by it, by dual port RAM /OER, / R/WR and INTR pin respectively with DSP /XRD, / XRW is connected with/XINT2 pin,

2, handwheel modular circuit

Manual pulse generator, is called for short handwheel, is used for manual setting numerically-controlled machine, complete the functions such as the setting of cutter far point, the input of interrupt operation and fine setting; Handwheel adopts metering-type grating disc to produce pulse signal, is provided with a light source, through condenser in CD one side, light is mapped on CD, through light and shade striped through original screen panel, is mapped on light activated element, light hurdle has two stripeds, its mutual relationship phase pi/2, is used for distinguishing both forward and reverse directions, and the photosignal obtained from light activated element is through amplification, shaping, be square-wave signal, send into circuit by interface circuit again, processed by main frame, realize Non-follow control; The two-way waveform relationship of handwheel as shown in Figure 4;

Handwheel sends into core processor DSP by interrupt mode, and in concrete Software for Design, being defined in A=1, B=0 handwheel when occurring to interrupt is forward feeding pulse, otherwise A=0, B=1 handwheel is feed reversing pulse; The interrupt service routine of handwheel mainly comprises several content below: judge the feeding pulse direction of handwheel, send out feeding pulse and adjust relevant coordinate figure, its responding process as shown in Figure 5;

3, DSP main controller circuit

As shown in Figure 6, described DSP main controller circuit comprises DSP control chip, reset circuit, crystal oscillation clock circuit, sheet outer SRAM circuit, jtag interface circuit, power circuit, real time clock circuit; Described DSP control chip, to be connected with reset circuit, crystal oscillation clock circuit, the outer SRAM circuit of sheet, jtag interface circuit, power circuit, real time clock circuit respectively;

Preferably, the model of described DSP control chip is TMS320F2812; Why select this chip, the real-time mainly in order to adapt to multi-shaft motion control system be high, process data volume large and and each module between cooperation control;

1), power circuit:

Its concrete circuit structure as shown in Figure 7;

TMS320F2812 chip adopts dual power supply power supply mechanism, reduces the power consumption of chip, simultaneously again for the interface between dsp chip and peripheral hardware provides conveniently;

The normal need of work of TMS320F2812 three kinds of power supplys: (1), dsp chip kernel 1.8V power supply, the internal logic circuit be mainly used to as device provides voltage support, mainly comprises peripheral hardware in clock circuit, CPU and sheet; (2) I/O mouth 3.3V power supply, the external interface circuit of dsp chip adopts 3.3V power voltage supply; (3), mimic channel 1.8V power supply, this power supply is specially for the mimic channel in the ADC module in dsp chip provides power supply;

The external power source of dsp chip adopts 5V power supply, in outside power supply source circuit, we select the power supply special chip TPS767D318 of TI company to provide power supply for dsp chip, and add magnetic bead formation passive filter circuit in circuit, magnetic bead impedance when high frequency is very high, when low frequency, impedance is very low, and the object done like this is exactly to absorb electrostatic pulse, filtering digital circuit noise, suppressing the high frequency noise on power lead, signal wire and spike to disturb; This mode structure is simple, and can meet circuit performance requirement;

2), crystal oscillating circuit and reset circuit

In the kernel of dsp chip, sheet, peripheral hardware and external interface all need to introduce clock signal from outside, therefore special outer clock circuit is needed, because TMS320F2812 chip internal is integrated with phase-locked loop circuit PLL, lower external clock can be passed through phase-locked loop circuit frequency multiplication to required cpu clock; The crystal oscillator of usual employing 30MHz or quartz crystal are as external clock reference, and after frequency multiplication of phase locked loop, frequency can reach 15 ~ 150MHz, substantially can meet system requirements; In addition, the external clock of lower frequency is adopted can to reduce the interference of external signal to clock signal on the one hand; On the other hand, avoid the interference of high frequency clock to other signals on plate, be conducive to anti-interference and the Electro Magnetic Compatibility of raising system; What adopt in this clock circuit is the mode combined with the sheet internal oscillator of dsp chip inside without source crystal, its connected mode as shown in Figure 8, the problem of level match is there is not without source crystal, clock signal is decided by oscillatory circuit, and price is relatively low, reduce the cost of system on the whole;

Reset circuit adopts touch-switch SW-PB as the reset signal of dsp chip and whole circuit, as long as click reset while switch just can complete whole system like this, the synchronism of system is improved greatly;

3), jtag interface circuit

Jtag interface is mainly used in the boundary scan testing of circuit and the on-line system debugging of programmable chip, the jtag interface adopted in the utility model is in order to complete debugging and access dsp chip, this mode only needs the JTAG emulation interface (the double contact pin of 7x2) designing a standard when design circuit plate, be connected with the interface of emulator, its circuit structure as shown in Figure 9, can realize debugging designed DSP circuit, complete that hardware circuit detects, code is downloaded, real-time simulation and to operations such as Flash and ram in slice programmings;

4), real time clock circuit

Kinetic control system needs inner timing system, in order to the information of real time record lathe, and outwardly can provide the data with temporal information, for the analysis of data in the future and extraction provide conveniently; In the utility model, the TMS320F2812 adopted does not possess inner RTC function, in order to make the function of digital control system more complete, in the design process by RTC chip for it extends RTC function;

Real-time clock (RTC) be one by crystal oscillator control accuracy, to the integrated circuit of the time that system provides binary-coded decimal to represent, date and time information and memory function; Be commonly used for signal source of clock and the parameter storage circuit of digital display circuit;

In this circuit, selected clock chip is the DS1501 real-time timepiece chip that Dallas company produces, and this chip has that volume is little, low in energy consumption, feature promptly and accurately; Because the precision of real-time clock and the frequency of crystal oscillator have much relations, we adopt the crystal oscillator of 32.768KHZ as external clock reference, 32768 why are selected to be because it is 15 powers of 2, realize the timing of 1s easily via frequency division, DS1501 has following functions and feature: (1) real-time clock can complete the year, month, day phase, sky, hour, minute and second etc. output; (2), clock data adopts BCD said shank; (3), the date in leap year is processed automatically; (4) programmable Watch Dog Timer and real-time clock warning function; (5), adopt special register, eliminate " in thousand " problem; (6) ,+3.3 or+5V operation is adopted, compatible with power supply; (7), accurate electrification reset function; (8) NVSRAM of 256 byte cell support is had in sheet; (9) provide Millisecond interrupt function, this function can coordinate the core clock in the middle of digital control system to use;

In actual applications, system time and other various information all may be lost because of power down, adopt duplicate supply structure in circuit for this reason, the power supply provided by motherboard power supply is under normal circumstances chip power supply, backup battery-lithium battery can be automatically switched to when being motherboard power supply power down under fortuitous event, so just provide larger guarantee for the safety of system data;

5), the outer SRAM circuit of sheet

The high speed of CYPRESS company is selected in the expansion of the chip external memory of TMS320F2812, low-power consumption, size is the memory device CY7C1041DV33 of 256K*16bit, can by the external memory storage of DSP expansion 256K with it, use as program's memory space or data space, low 14 (A13 ~ A0) of address bus are directly connected with data bus (D15 ~ D0) by the interface circuit of DSP and SRAM, high 5 are used for carrying out address decoding to address bus, the chip selection signal pin of SRAM is selected by the pin sheet of DSP simultaneously, read and write, pin connects through gating circuit, the BHE of SRAM is realized by ground connection, the Low level effective of BLE and OE pin, its circuit structure as shown in Figure 10,

3, Interface Expanding circuit

Described Interface Expanding circuit comprises storer and I/O expansion interface; Described I/O expansion interface is arranged on the surrounding of CPLD storer, and is connected with CPLD storer;

Described storer comprises CPLD chip, CPLD reset circuit and emulation interface circuit; Described CPLD chip is connected with described reset circuit, emulation interface circuit respectively;

1), CPLD chip

Its inner structure as shown in figure 11,

This circuit adopts CPLD chip to expand TMS320F2812, and I/O interface can be made to increase 48 tunnels, when DSP conducts interviews to the I/O interface that CPLD expands by the control of decoding gating circuit as the I/O interface of access self;

In this circuit, CPLD chip mainly completes address decoding and decoding gating function, preferably, the CPLD chip adopted selects the XC9500 family chip of XILINX company, as complete I/O expansion and chip external memory expand chip used, XC9500 family chip is the FPGA (Field Programmable Gate Array) solution that user provides low cost, high reliability, in addition, on the high performance basis of maintenance, XC9500 family chip can also provide maximum dirigibility for user's wiring, its feature comprises: (1) integrated level is high, gate count available 800 ~ 6400; (2) pin compatibility is good, and input pin can the compatible voltage accepting multiple different size; (3) dirigibility is strong, and support online programming, device can be programmed 10,000 times repeatedly; (4) good confidentiality, one-time programming data can complete preservation 20 years; (5) I/O rich interface, maximum I/O number can reach 192; (6) simple to operate, substantially do not need external auxiliary equipment; (7) adopt Flash technology, device travelling speed is fast, and the time delay between pin is 5ns; (8), system clock is up to 178MHz;

2), CPLD reset circuit

The effect of reset circuit is mainly used for completion system program and is running the reset function flown or in other situations, and its circuit structure as shown in figure 12; What reset key adopted is that a kind of soft-touch type closes button; Upper resistance makes reseting interface keep high level, and after button is pressed, I/O is connected to reference to ground, exports as low level, and increasing electric capacity in circuit is to prevent key jitter from producing burr;

3), emulation interface circuit

Its circuit structure as shown in figure 13, but can realize the selection of different chip by the position of mobile jumper wire cap when downloading;

4, described encoder to count circuit comprises encoder feedback circuit and filtering circuit;

Described encoder feedback circuit comprises fpga chip, FPGA power circuit (as shown in figure 14), FPGA crystal oscillating circuit, chip external memory circuit (as shown in figure 15), configuration bit selection circuit (as shown in figure 16), FPGA reset circuit (sharing a reset circuit with CPLD) and FPGA relay indicating light circuit;

Preferably, the model of described fpga chip is Spartan-3;

Chip external memory circuit (as shown in figure 15), the PROM chip selected by chip external memory is XCF02SVO20C, and the storage space of this chip can reach 2Mbit, supply voltage 3.3V and FPGA external interface voltage compatibility;

5, D/A change-over circuit

The digital signal that core processor DSP exports mainly is converted into simulating signal in order to control servomotor by D/A change-over circuit;

Be provided with analog-digital chip in described D/A change-over circuit, described analog-digital chip is the D/A converter of 12, and preferably, its model is DAC7725; This chip is the chip produced by BURR-BROWN company, has four road modulating output, and its effect is that the digital signal that DSP exports is converted to the simulating signal controlling servomotor, exports expression formula as follows:

$V_{OUT}=-V_{REF}\×\frac{data}{4096}---\left(1\right)$

Wherein, the digital quantity that data representative exports, its value is a unsigned number of 0 ~ 4095;

DAC7725 is connected with the CPLD of I/O expanded circuit by this circuit; Concrete syndeton as shown in figure 17;

6, amplifying circuit and interface circuit

Be provided with operation amplifier chip in described amplifying circuit, its model is LM324; Its concrete circuit structure as shown in figure 18,

In interface circuit, because the I/O interface driver power supply of DSP, CPLD and FPGA is+3.3V, and the power supply major part that peripheral components adopts is+5V, for ensureing that the security of the components and parts work such as DSP, CPLD, FPGA need be changed the level of signal, have selected 74LVTH16245 chip, this chip can not only complete the level conversion between+3.3V and+5V for this reason, the more important thing is that it can by arranging, complete the direction by the flowing of byte control data, and do not need pull-up resistor; In addition, the electrical isolation that this circuit also utilizes dual channel optoelectronic coupling mechanism to realize between output terminal and load, improves the antijamming capability of circuit to greatest extent;

The utility model utilizes dsp chip as main control chip, completes the signal transmission between each module, process and output services; The circuit design of whole system, adopt modular design structure, ensure that the utility model product is when working environment changes, when not carrying out any hardware circuit amendment, in time can adjust the structure of self according to the change of external condition, meet the demand of different control system; In addition, adopt modular design structure, reduce the electromagnetic interference (EMI) between signal with different type to greatest extent, the accuracy tool improving system is of great significance;

The utility model is not limited to above-mentioned concrete embodiment, and those of ordinary skill in the art is from above-mentioned design, and without performing creative labour, done all conversion, all drop within protection domain of the present utility model.

Claims (10)

1. a multi-shaft motion control system, comprises host computer, interface convertor, control mainboard, servo-driver and servomotor; Described host computer is connected with interface convertor; Described interface convertor is connected with control mainboard; Described control mainboard is connected with servo-driver; Described servo-driver is connected with servomotor; It is characterized in that: described control mainboard comprises signal input module, signal processing module and signal output module; Dual port RAM, handwheel modular circuit is provided with in described signal input module; DSP main controller circuit, Interface Expanding circuit, encoder to count circuit is provided with in described signal processing module; D/A change-over circuit, amplifying circuit, motor interface circuit is provided with in described signal output apparatus; Described dual port RAM is connected with interface convertor by bus; Described handwheel modular circuit is connected with DSP main controller circuit; Described DSP main controller circuit is connecting interface expanded circuit, encoder to count circuit respectively; Described DSP main controller circuit is also connected with D/A change-over circuit; Described D/A change-over circuit is connected with amplifying circuit; Described amplifying circuit is connected with motor interface circuit; Described motor interface circuit is connected with servo-driver.

2. a kind of multi-shaft motion control system according to claim 1, is characterized in that: described dual port RAM is 8Kx16 twoport static ram chip, and its model is CY7C025.

3. a kind of multi-shaft motion control system according to claim 1, is characterized in that: described DSP main controller circuit comprises DSP control chip, reset circuit, crystal oscillation clock circuit, sheet outer SRAM circuit, jtag interface circuit, power circuit, real time clock circuit; Described DSP control chip is connected with reset circuit, crystal oscillation clock circuit, the outer SRAM circuit of sheet, jtag interface circuit, power circuit, real time clock circuit respectively.

4. a kind of multi-shaft motion control system according to claim 3, is characterized in that: the model of described DSP control chip is TMS320F2812.

5. a kind of multi-shaft motion control system according to claim 1, is characterized in that: described Interface Expanding circuit comprises storer and I/O expansion interface; Described I/O expansion interface is arranged on the surrounding of CPLD storer, and is connected with CPLD storer.

6. a kind of multi-shaft motion control system according to claim 5, is characterized in that: described storer comprises CPLD chip, CPLD reset circuit and emulation interface circuit; Described CPLD chip is connected with described reset circuit, emulation interface circuit respectively.

7. a kind of multi-shaft motion control system according to claim 1, is characterized in that: described encoder to count circuit comprises encoder feedback circuit and filtering circuit.

8. a kind of multi-shaft motion control system according to claim 7, is characterized in that: described encoder feedback circuit comprises fpga chip, FPGA power circuit, FPGA crystal oscillating circuit, chip external memory circuit, configuration bit selection circuit, FPGA reset circuit and FPGA relay indicating light circuit.

9. a kind of multi-shaft motion control system according to claim 1, is characterized in that: be provided with analog-digital chip in described D/A change-over circuit, and described analog-digital chip is the D/A converter of 12, and its model is DAC7725.

10. a kind of multi-shaft motion control system according to claim 1, is characterized in that: be provided with operation amplifier chip in described amplifying circuit, its model is LM324.