CN202189386U - Opening and closing state monitoring circuit and electronic label adopting same - Google Patents
Opening and closing state monitoring circuit and electronic label adopting same Download PDFInfo
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- CN202189386U CN202189386U CN2011202855754U CN201120285575U CN202189386U CN 202189386 U CN202189386 U CN 202189386U CN 2011202855754 U CN2011202855754 U CN 2011202855754U CN 201120285575 U CN201120285575 U CN 201120285575U CN 202189386 U CN202189386 U CN 202189386U
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Abstract
The utility model discloses an opening and closing state monitoring circuit and an electronic label adopting the same. The opening and closing state monitoring circuit comprises a PMOS (p-channel metal oxide semiconductor) pipe, a nand gate, a first phase inverter, a level conversion unit and a latch. The level conversion unit comprises a second phase inverter and a third phase inverter. Compared with the prior opening and closing state acquiring circuit, the opening and closing state monitoring circuit disclosed by the utility model can be implemented by adopting an integrated circuit component having the same process as the electronic label, has a simple structure, consumes less power and can be hereby integrated in an electronic label chip. As the monitoring node of the internet of things for the flow of a container and a safety case, the electronic label with which the opening and closing state monitoring circuit is integrated can be used to monitor the opening and closing state of the container and the safety case timely so as to ensure the safety of the flow of the container and the safety case.
Description
Technical field
The utility model belongs to the electronic circuit technology field, particularly a kind of clutch state supervisory circuit and adopt the electronic tag of this circuit.
Background technology
RF identification (RFID, Radio Frequency Identification) technology is to utilize the RF-wise purposes such as identification, tracking, location and management of communication to reach article at a distance.REID is in industrial automation, business automation, and the communications and transportation control and management, various fields such as false proof, even military use is with a wide range of applications, and caused at present widely and paid close attention to.
Utilize electronic tag that REID makes and reader by use widely, particularly as the electronic tag of the node of Internet of Things, can effectively store adhere to article various information and through with these information of communications of reader.In logistic industries such as encased conveying management, proof box, people hope and can effectively monitor clutch (opening and closing) status information through the mode of on container, adhering to electronic tag that the behavior of container or proof box is opened in monitoring.
The applicant has proposed two kinds of lock clutch state acquisition circuit at publication number CN101915025A and CN101916353A; Be used for electronic tag, can reach the function of monitoring clutch state, but these two kinds of Acquisition Circuit used more discrete component; And bipolar transistor and DC-DC voltage transitions chip are arranged in the Acquisition Circuit; And electronic label chip all is to adopt cmos device to realize, the two manufacturing process is different, makes that Acquisition Circuit is unfavorable for carrying out integrated with electronic tag; And power consumption is excessive, therefore is not suitable for combining to use as the node of Internet of Things with electronic tag.
The utility model content
The purpose of the utility model is for the shortcoming that integrated level is low and power consumption is excessive that solves existing lock clutch state acquisition circuit, has proposed a kind of clutch state supervisory circuit.
The technical scheme of the utility model is: a kind of clutch state supervisory circuit that is used for electronic tag; Comprise: PMOS pipe, Sheffer stroke gate, first phase inverter; Level conversion unit and latch; Wherein, the source electrode of the first input end of said Sheffer stroke gate, said PMOS pipe and the input end of said latch link together, as the input end of the clutch state signal of clutch state supervisory circuit; The body end of said PMOS pipe is connected to outside power-supply battery; Second input end of said Sheffer stroke gate is connected with the output terminal of first phase inverter; The output terminal of said Sheffer stroke gate is connected with the Enable Pin of latch; The positive output end of said latch is connected with the grid of PMOS pipe; The drain electrode of said PMOS pipe is to said electronic tag output supply voltage; Said level conversion unit is used for the status signal that drain voltage with said PMOS pipe converts the digital baseband processor that is used to be input to said electronic tag into; The input end of said first phase inverter is imported the voltage control signal of the digital baseband processor of said electronic tag.
As a preferable scheme; Said level conversion unit comprises second phase inverter and the 3rd phase inverter; The input end of said second phase inverter links to each other with the drain electrode of said PMOS pipe as the input end of said level conversion unit, and the output terminal of said second phase inverter links to each other with the input end of said the 3rd phase inverter; The output terminal of said the 3rd phase inverter is as the output terminal of the said level conversion unit digital baseband processor output status signal to electronic tag.
Another purpose of the utility model is in order to solve the difficulty of electronic tag to the clutch state monitoring, to have proposed a kind of electronic tag that adopts the clutch state supervisory circuit.
To achieve these goals; A kind of electronic tag that adopts the clutch state supervisory circuit is provided; Said electronic tag comprises antenna, rf analog front-end and digital baseband processor; Said rf analog front-end comprises reference voltage-stabilizing circuit, and said digital baseband processor comprises State Control machine module, it is characterized in that; Said electronic tag also comprises the clutch state supervisory circuit; Said clutch state supervisory circuit is connected with the State Control machine module of digital baseband processor and to State Control machine module output status signal, the voltage control signal of accepting state controller module input simultaneously, and said clutch state supervisory circuit is connected with the reference voltage-stabilizing circuit of rf analog front-end and to reference voltage-stabilizing circuit supply voltage is provided.
The beneficial effect of the utility model: the existing relatively lock clutch state acquisition circuit of the clutch state supervisory circuit of the utility model; Can adopt with the IC-components of electronic label chip same process and realize; Circuit structure is simple; And power consumption is lower, thereby can be integrated in electronic label chip inside.The electronic tag of integrated clutch state supervisory circuit is as the Internet of Things monitor node of container, proof box circulation in the logistic industry, and the clutch state of monitoring containers, proof box has timely guaranteed the security of container, proof box circulation.Adopted the electronic tag of clutch state supervisory circuit to take into account the function of ordinary passive ultrahigh frequency electronic tag in the radio-frequency field; And no matter the external world has or not radio-frequency field all can accomplish the record for clutch state; Can also effectively reduce the consumption and volume in kind of power consumption; Reduced dependence, strengthened practicality for various particular application for external power source.
Description of drawings
Fig. 1 is the utility model clutch state supervisory circuit structural representation.
Fig. 2 is the Electronic Tag Structure synoptic diagram that adopts the clutch state supervisory circuit of the utility model.
Description of reference numerals: clutch signaling switch S1, the first phase inverter G1, the second phase inverter G2, the 3rd phase inverter G3; PMOS manages T1; Power-supply battery B1, latch D1, Sheffer stroke gate C1, decoder module 101, cyclic check module 102, input pre-processing module 103, State Control machine module 104, output pre-processing module 105, coder module 106, memory access control module 107, pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111, reset generation module 112, MTP storer 113, rectification circuit 201, reference voltage-stabilizing circuit 202, modulation circuit 203, demodulator circuit 204, reset circuit 205, clock circuit 206.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the utility model is done further explanation.
As shown in Figure 1, the circuit structure of clutch state supervisory circuit is following: comprise the first phase inverter G1, the second phase inverter G2, the 3rd phase inverter G3, PMOS manages T1, latch D1, Sheffer stroke gate C1.Here clutch signaling switch S1 and power-supply battery B1 are as the outside accessory constituent of clutch state supervisory circuit.
In conjunction with Fig. 1, the connected mode of each device and port is following:
The source electrode of the first input end c of said Sheffer stroke gate C1, said PMOS pipe T1 and the input end D of said latch D1 link together, as the input end of the clutch state signal of clutch state supervisory circuit; The body end of said PMOS pipe T1 is connected to outside power-supply battery B1, promptly links to each other with the positive pole of the power-supply battery B1 of outside; The second input end d of said Sheffer stroke gate C1 is connected with the output terminal of the first phase inverter G1; The output terminal of said Sheffer stroke gate C1 is connected with the Enable Pin EN of latch; The positive output end Q of said latch is connected with the grid of PMOS pipe T1; The drain electrode of said PMOS pipe T1 is to said electronic tag output supply voltage; Said level conversion unit is used for the status signal switch_on that drain voltage with said PMOS pipe T1 converts the digital baseband processor that is used to be input to said electronic tag into; The input end of the first phase inverter G1 is imported the voltage control signal power_control of the digital baseband processor of said electronic tag.
In the present embodiment; The clutch state signal characterizes through clutch signaling switch S1; The positive pole of outside power-supply battery B1 is connected with the first end a of clutch signaling switch S1; Minus earth, the second end b of clutch signaling switch S1 links to each other with the input end of the clutch state signal of clutch state supervisory circuit.
As one of present embodiment preferable scheme; Level conversion unit comprises the second phase inverter G2 and the 3rd phase inverter G3; The input end of the said second phase inverter G2 links to each other with the drain electrode of said PMOS pipe T1 as the input end of said level conversion unit, and the output terminal of the said second phase inverter G2 links to each other with the input end of said the 3rd phase inverter G3; The output terminal of said the 3rd phase inverter G3 is as the output terminal of the said level conversion unit digital baseband processor output status signal switch_on to electronic tag.
Here, power-supply battery B1 can adopt the button cell of 3V.
In conjunction with Fig. 1, the clutch state supervisory circuit course of work is following, for the ease of explanation, is example with the clutch state of electronic lock.
When lock cut out, switch S 1 was broken off, and to the label chip power supply, status signal switch_on and voltage control signal power_control are not low level to power-supply battery B1.
When lock was opened, clutch signaling switch S1 was closed, and the source electrode of the c end of Sheffer stroke gate C1, the D end of latch D1, PMOS pipe T1 is connected high voltage; This moment, voltage control signal power_control was a low level, behind the first phase inverter G1, to the d end input high level of Sheffer stroke gate C1; Thereby the Enable Pin EN of latch D1 is a low level; Latch D1 output terminal Q is a low level, PMOS pipe T1 conducting, and power-supply battery B1 opens electronic tag is supplied power; The status signal switch_on of the 3rd phase inverter G3 output high level, digital baseband processor is to the behavior counting of unblanking.
When lockset kept opening, the digital baseband processor of electronic tag was drawn high voltage control signal power_control and is high level, at this moment; Sheffer stroke gate C1 exports high level, the Q end output high level of latch D1, and PMOS pipe T1 ends; Power-supply battery B1 stops electronic tag being supplied power; Status signal switch_on and voltage control signal power_control all change low level into, and the Enable Pin EN end of latch D1 is 0, and the positive output end Q of latch D1 keeps high level; PMOS pipe T1 remain off state, power-supply battery B1 does not supply power to electronic tag.
When lock cut out once more, clutch signaling switch S1 broke off, and power-supply battery B1 does not supply power to electronic tag.
The structure of the electronic tag of employing clutch state supervisory circuit is as shown in Figure 2; Comprise antenna, rf analog front-end and digital baseband processor; Said rf analog front-end comprises reference voltage-stabilizing circuit; Said digital baseband processor comprises State Control machine module; Said electronic tag also comprises the clutch state supervisory circuit; Said clutch state supervisory circuit is connected with the State Control machine module of digital baseband processor and to State Control machine module 104 output status signal switch_on, the voltage control signal power_control of accepting state controller module 104 inputs simultaneously, and said clutch state supervisory circuit is connected with the reference voltage-stabilizing circuit 202 of rf analog front-end and to reference voltage-stabilizing circuit 202 supply voltage is provided.
The rf analog front-end concrete structure of above-mentioned electronic tag comprises rectification circuit 201, reference voltage-stabilizing circuit 202, modulation circuit 203, demodulator circuit 204, reset circuit 205, clock circuit 206; Said antenna directly is connected with rectification circuit 201, modulation circuit 203 and demodulator circuit 204 through the interface PAD of ESD (anti-static protection circuit); The radiofrequency signal that rectification circuit 201 receives antenna is converted into that direct supply is divided into the rectification low-voltage and the rectification high voltage offers reference voltage-stabilizing circuit 202; 202 pairs of power supplys of reference voltage-stabilizing circuit carry out voltage stabilizing; For the electronic tag digital baseband part provides low supply voltage 1V and high power supply voltage 1.8V; For modulation circuit 203 provides 1.8V WV; For demodulator circuit 204, clock circuit 206 and reset circuit 205 provide 1V WV; Reference voltage-stabilizing circuit 202 also is connected with the supply voltage to electronic tag of clutch state supervisory circuit output simultaneously, when lockset is opened, if rectification circuit 201 is not then supplied power to reference voltage-stabilizing circuit 202 by the clutch state supervisory circuit when reference voltage-stabilizing circuit 202 power supplies; Demodulator circuit 204 recovers the required demodulating data of digital baseband processor of RF identification from radiofrequency signal; Modulation circuit 203 adopts the method for backscattered modulation that the modulating data of electronic tag digital baseband processor output is modulated, and realizes the data transmission of electronic tag to reader; Clock circuit 206 provides stable clock signal of system for digital baseband processor, and reset circuit 205 provides required reset signal for digital baseband processor.
The BBP concrete structure of above-mentioned electronic tag comprises that digital baseband part comprises State Control machine module 104, decoder module 101, coder module 106, cyclic check module 102, memory access control module 107, input pre-processing module 103, output pre-processing module 105, pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111, reset generation module 112 and MTP storer 113.Said decoder module 101 is imported pre-processing module 103 respectively and is connected with cyclic check module 102; Said cyclic check module 103 is connected with output pre-processing module 105, coder module 106; Said memory access control module 107 is connected with output pre-processing module 105; Behind the demodulating data that the demodulator circuit 204 of said decoder module 101 received RF AFE(analog front end)s provides; Through decoder module 101 decodings, export decoded data, decoded data divides two-way; One the road to importing pre-processing module 103, a road to cyclic check module 102; Said input pre-processing module 103 is accomplished the input pre-service of decoded data, generates pending data and pending order and outputs to State Control machine module 104; After simultaneously cyclic check module 103 is accomplished the cyclic check to decoded data, generate the cyclic check result and output to State Control machine module 104; State Control machine module 104 detects the result of clutch signal switch_on and 102 inputs of cyclic check module; And carry out clutch according to the situation of inspection and write down or receive pending data and pending order; If clutch signal switch_on is high level (the high level value is 1V, and the low level value is 0V) here, the expression clutch state is for opening; Then carry out the record of unblanking; After 104 analyses place of State Control machine module, the calculated address signal is to memory access control module 107, and the related memory cell that storage is unblanked to write down carries out read-write operation; And the voltage control signal power_control that after being finished, will be input to the clutch state supervisory circuit draws high and is high level; If carry out data and command process, then after State Control machine module 104 is analyzed and handled, generate five tunnel control signal branches and be clipped to pseudorandom number generator module 108, collision counter module 109, timer conter module 110, clock generating module 111 and reset generation module 112; The calculated address signal arrives memory access control module 107, and exports pseudo random number to be sent to output pre-processing module 105; Memory access control module 107 is visited MTP storer 113 through MTP storer IO interface and is exported memory data to be sent to the output pre-processing module according to address signal; Described output pre-processing module 105 receives pseudo random number to be sent and memory data to be sent, generates data to be sent to cyclic check module 102 through the output pre-processing module; Cyclic check module 102 is accomplished the reflected code coding to data to be sent, generates data to be encoded and outputs to coder module 106; Said coder module 106 is accomplished the coding of data to be encoded, generates and treats that modulating data outputs to the modulation circuit 203 of rf analog front-end; The clock signal of system of clock circuit 206 inputs of 111 pairs of rf analog front-ends of said clock generating module carries out frequency division and produces the required clock signal of each module, and the reset signal of reset circuit 205 inputs of 112 pairs of rf analog front-ends of reset generation module is carried out synchronous processing and produced the required reset signal of each module in the digital baseband processor.Digital baseband processor provides 1.8V high level and the low level working power voltage of 1V by the reference voltage-stabilizing circuit 202 of rf analog front-end.
Down the course of work in the face of the electronic tag that adopts the clutch state supervisory circuit is described in detail, and for the ease of explanation, here, is example with the clutch state of electronic lock.
In conjunction with Fig. 2, when the electronic tag (hereinafter to be referred as electronic tag) that adopts the clutch state supervisory circuit was in the RF identification field, its course of work was following:
Step (a): electronic tag gets into the RF identification field; The rf analog front-end of electronic tag works on power; Benchmark Voltage stabilizing module 202 provides low level WV and high level WV (present embodiment low level and high level be value 1V, 1.8V respectively) for digital baseband processor; 112 pairs of State Control machines of reset generation module module 104 resets, the radiofrequency signal that demodulator circuit 204 beginning demodulation antennas receive, and the clutch state supervisory circuit is gathered the clutch state of lockset;
Step (b): State Control machine module 104 detects the clutch state supervisory circuit, and when status signal swith_on is high level (the high level value is 1V here, and the low level value is 0V), the clutch state of promptly representing lockset changes step (c) over to for opening; Otherwise clutch state changes step (d) over to for closing;
Step (c): State Control machine control module 104 calculated address signals are to memory access control module 107; The related memory cell that storage is unblanked to write down carries out read-write operation; New recorded data more; And the voltage control signal power_control that will be input to the clutch state supervisory circuit draws high and is high level, if the power supply power supply finishes to change step (m) over to otherwise changes step (d) over to;
104 pairs of decoder module 101 of step (d) State Control machine module, cyclic check module 102, coder module 106; Input pre-processing module 103, output pre-processing module 105, memory access control module 107; Pseudorandom number generator module 108, collision counter module 109, timer conter module 110; Clock generating module 111 resets, and reads the data in the MTP storer 113, the cyclic check CRC result of computational data;
Step (e) State Control machine module 104 detects the clutch state supervisory circuit, and when status signal swith on was high level, the clutch state of promptly representing lockset changed step (c) over to, otherwise changes step (f) over to for opening;
Step (f): State Control machine module 104 is opened decoder module 101, off state controller module 104 self clock then, and State Control machine module 104 is in dormant state;
Step (g): decoder module 101 begins to detect from the demodulating data of demodulator circuit 204 inputs of rf analog front-end, when detect available frame count according to the time, decoder module 101 wake-up states controller modules 104;
Step (h): State Control machine module 104 is opened input pre-processing module 103 and cyclic check module 102; Decoder module 101 receives demodulating data; Through the decoder module decoding, export decoded data, decoded data divides two-way; One the road to importing pre-processing module 103, a road to cyclic check module 102; Input pre-processing module 103 is accomplished the input pre-service of decoded data, generates pending data and pending order and outputs to State Control machine module 104; The module of cyclic check simultaneously 102 is accomplished the cyclic check of decoded data, generates the cyclic check result and outputs to State Control machine module 104;
Step (i): when State Control machine module 104 detects 102 pairs of cyclic check modules the cyclic check of decoded data has been accomplished; State Control machine module 104 is turn-offed decoder module 101, input pre-processing module 103 and cyclic check module 102; State Control machine module 104 receives pending data and pending order simultaneously; Generate control signal through State Control machine module analysis with after handling; Operate 110 according to the control signal unlatching and to pseudorandom number generator module 108, collision counter module 109 and timer conter module, and after operation is accomplished, close pseudorandom number generator module 108, collision counter module 109 and timer conter module 110;
Step (j): State Control machine module 104 is opened output pre-processing module 105 and memory access control module 107; State Control machine module 104 OPADD signals arrive memory access control module 107, and export pseudo random number to be sent to output pre-processing module 105; The memory access control module through MTP storer 113 IO ports visit MTP storer, is exported memory data to be sent to output pre-processing module 105 according to address signal;
Step (k): State Control machine module 104 ON cycle check code modules 102 and coder module 106; Output pre-processing module 105 receives pseudo random number to be sent and memory data to be sent, generates data to be sent to cyclic check module 102 through output pre-processing module 105; Cyclic check module 102 is accomplished the reflected code coding to data to be sent, and the data to be encoded behind the reflected code coding are outputed to coder module 106; Coder module 106 is accomplished the coding to the data to be encoded behind the reflected code coding, and the modulation circuit of modulating data to rf analog front-end treated in output; After the rf analog front-end modulation circuit is modulated data, through the communication between antenna realization and the read write line.
Step (l): after coder module 106 codings are accomplished; State Control machine module 104 is closed output pre-processing module 105, cyclic check module 102, memory access control module 107 and coder module 106; The whether power down of State Control machine module 104 inspection power supplys; Power down changes step (m) over to, otherwise changes step (e) over to;
Step (m): power supply power-fail, all modules quit work.
When the electronic tag that adopts the clutch state supervisory circuit is in RF identification outside the venue the time, its course of work is following:
Step (A): when lockset is opened; The clutch state supervisory circuit is to the reference voltage-stabilizing circuit 202 output direct current supply voltages of electronic tag rf analog front-end; Rf analog front-end works on power; 112 pairs of State Control machines of reset generation module module 104 of BBP resets the clutch state of clutch state monitor circuit monitors lockset;
Step (B): State Control machine module 104 detects the clutch state supervisory circuit, and when status signal swith on is high level (the high level value is 1V here, and the low level value is 0V), the clutch state of promptly representing lockset changes step (C) over to for opening; Otherwise clutch state changes step (D) over to for closing;
Step (C): State Control machine control module 104 calculated address signals are to memory access control module 107; The related memory cell that storage is unblanked to write down carries out read-write operation; New recorded data more, and the voltage control signal power_control that will be input to the clutch state supervisory circuit draws high and is high level;
Step (D): the power supply power-fail of clutch state supervisory circuit, clutch state supervisory circuit stop reference voltage-stabilizing circuit 202 power supplies to rf analog front-end, and electronic tag quits work.
To sum up; Because the existing relatively lock clutch state acquisition circuit of clutch state supervisory circuit of the utility model can adopt with the IC-components of electronic label chip same process and realize that circuit structure is simple; And power consumption is lower, thereby can be integrated in electronic label chip inside.The electronic tag of integrated clutch state supervisory circuit is as the Internet of Things monitor node of container, proof box circulation in the logistic industry, and the clutch state of monitoring containers, proof box has timely guaranteed the security of container, proof box circulation; Adopt the electronic tag of clutch state supervisory circuit to take into account the function of ordinary passive ultrahigh frequency electronic tag in the radio-frequency field simultaneously, no matter the external world has or not radio-frequency field all can accomplish the record for the clutch state number of times simultaneously.Because what the utility model adopted is passive ultrahigh frequency electronic tag, can also effectively reduce the consumption and volume in kind of power consumption, reduced dependence for external power source, strengthened practicality for various particular application.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help the principle of reader understanding's the utility model, should to be understood that the protection domain of the utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these teachings of the utility model, and these distortion and combination are still in the protection domain of the utility model.
Claims (3)
1. a clutch state supervisory circuit that is used for electronic tag is characterized in that, comprising: the PMOS pipe; Sheffer stroke gate; First phase inverter, level conversion unit and latch, wherein; The source electrode of the first input end of said Sheffer stroke gate, said PMOS pipe and the input end of said latch link together, as the input end of the clutch state signal of clutch state supervisory circuit; The body end of said PMOS pipe is connected to outside power-supply battery; Second input end of said Sheffer stroke gate is connected with the output terminal of first phase inverter; The output terminal of said Sheffer stroke gate is connected with the Enable Pin of latch; The positive output end of said latch is connected with the grid of PMOS pipe; The drain electrode of said PMOS pipe is to said electronic tag output supply voltage; Said level conversion unit is used for the status signal that drain voltage with said PMOS pipe converts the digital baseband processor that is used to be input to said electronic tag into; The input end of said first phase inverter is imported the voltage control signal of the digital baseband processor of said electronic tag.
2. clutch state supervisory circuit according to claim 1; It is characterized in that; Described level conversion unit comprises second phase inverter and the 3rd phase inverter; The input end of said second phase inverter links to each other with the drain electrode of said PMOS pipe as the input end of said level conversion unit, and the output terminal of said second phase inverter links to each other with the input end of said the 3rd phase inverter; The output terminal of said the 3rd phase inverter is as the output terminal of the said level conversion unit digital baseband processor output status signal to electronic tag.
3. electronic tag that adopts claim 1 or 2 described clutch state supervisory circuits; Said electronic tag comprises antenna, rf analog front-end and digital baseband processor; Said rf analog front-end comprises reference voltage-stabilizing circuit; Said digital baseband processor comprises State Control machine module; It is characterized in that said electronic tag also comprises the clutch state supervisory circuit, said clutch state supervisory circuit is connected with the State Control machine module of digital baseband processor and to State Control machine module output status signal; The voltage control signal of while accepting state controller module input, said clutch state supervisory circuit is connected with the reference voltage-stabilizing circuit of rf analog front-end and to reference voltage-stabilizing circuit supply voltage is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202855754U CN202189386U (en) | 2011-08-08 | 2011-08-08 | Opening and closing state monitoring circuit and electronic label adopting same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202855754U CN202189386U (en) | 2011-08-08 | 2011-08-08 | Opening and closing state monitoring circuit and electronic label adopting same |
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| CN202189386U true CN202189386U (en) | 2012-04-11 |
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| CN2011202855754U Expired - Lifetime CN202189386U (en) | 2011-08-08 | 2011-08-08 | Opening and closing state monitoring circuit and electronic label adopting same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102289708A (en) * | 2011-08-08 | 2011-12-21 | 电子科技大学 | Clutch state monitoring circuit and electronic tag adopting same |
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2011
- 2011-08-08 CN CN2011202855754U patent/CN202189386U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102289708A (en) * | 2011-08-08 | 2011-12-21 | 电子科技大学 | Clutch state monitoring circuit and electronic tag adopting same |
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