CN202189386U - Opening and closing state monitoring circuit and electronic label adopting same - Google Patents

Abstract

The utility model discloses an opening and closing state monitoring circuit and an electronic label adopting the same. The opening and closing state monitoring circuit comprises a PMOS (p-channel metal oxide semiconductor) pipe, a nand gate, a first phase inverter, a level conversion unit and a latch. The level conversion unit comprises a second phase inverter and a third phase inverter. Compared with the prior opening and closing state acquiring circuit, the opening and closing state monitoring circuit disclosed by the utility model can be implemented by adopting an integrated circuit component having the same process as the electronic label, has a simple structure, consumes less power and can be hereby integrated in an electronic label chip. As the monitoring node of the internet of things for the flow of a container and a safety case, the electronic label with which the opening and closing state monitoring circuit is integrated can be used to monitor the opening and closing state of the container and the safety case timely so as to ensure the safety of the flow of the container and the safety case.

Description

A clutch state monitoring circuit and an electronic label using the circuit

technical field

The utility model belongs to the technical field of electronic circuits, in particular to a clutch state monitoring circuit and an electronic label using the circuit.

Background technique

Radio Frequency Identification (RFID, Radio Frequency Identification) technology is the use of radio frequency long-distance communication to achieve the identification, tracking, positioning and management of items. Radio frequency identification technology has broad application prospects in many fields such as industrial automation, commercial automation, traffic control management, anti-counterfeiting, and even military use, and has attracted widespread attention.

Electronic tags and readers made using radio frequency identification technology are widely used, especially electronic tags as nodes of the Internet of Things, which can effectively store various information of attached items and transmit these information through communication with readers. In logistics industries such as container transportation management and safes, people hope to effectively monitor clutch (opening and closing) status information by attaching electronic tags to containers, and monitor the behavior of opening containers or safes.

The applicant has proposed two lock clutch state acquisition circuits in publication numbers CN101915025A and CN101916353A, which are used in electronic tags and can achieve the function of monitoring the clutch state, but these two acquisition circuits use more discrete components, and the acquisition circuit There are bipolar transistors and DC-DC voltage conversion chips, while the electronic label chips are all realized by CMOS devices. The manufacturing process of the two is different, which makes the acquisition circuit unfavorable for integration with the electronic label, and the power consumption is too large. Therefore, It is not suitable to be used as a node of the Internet of Things in combination with electronic tags.

Utility model content

The purpose of the utility model is to solve the shortcomings of low integration and excessive power consumption of the existing lock and clutch state acquisition circuit, and propose a clutch state monitoring circuit.

The technical scheme of the utility model is: a clutch state monitoring circuit for electronic tags, including: PMOS tube, NAND gate, first inverter, level conversion unit and latch, wherein, the NAND The first input end of the gate, the source of the PMOS transistor and the input end of the latch are connected together as the input end of the clutch state signal of the clutch state monitoring circuit; the body end of the PMOS transistor is connected to the external The power supply battery of the NAND gate; the second input terminal of the NAND gate is connected with the output terminal of the first inverter; the output terminal of the NAND gate is connected with the enable terminal of the latch; the positive The phase output terminal is connected to the gate of the PMOS transistor; the drain of the PMOS transistor outputs a power supply voltage to the electronic label; the level conversion unit is used to convert the drain voltage of the PMOS transistor to be input to The state signal of the digital baseband processor of the electronic tag; the input terminal of the first inverter inputs the voltage control signal of the digital baseband processor of the electronic tag.

As a preferred solution, the level conversion unit includes a second inverter and a third inverter, and the input terminal of the second inverter serves as the input terminal of the level conversion unit and the PMOS The drain of the tube is connected, the output terminal of the second inverter is connected with the input terminal of the third inverter; the output terminal of the third inverter is used as the output terminal of the level conversion unit to The digital baseband processor of the electronic tag outputs status signals.

Another purpose of the utility model is to solve the difficulty of monitoring the clutch state by the electronic tag, and propose an electronic tag using a clutch state monitoring circuit.

In order to achieve the above purpose, an electronic tag using a clutch state monitoring circuit is provided, the electronic tag includes an antenna, a radio frequency analog front end and a digital baseband processor, the radio frequency analog front end includes a reference voltage stabilizing circuit, and the digital baseband processing The device includes a state control machine module, and it is characterized in that the electronic tag also includes a clutch state monitoring circuit, and the clutch state monitoring circuit is connected with the state control machine module of the digital baseband processor and outputs a state signal to the state control machine module, and at the same time Receiving the voltage control signal input by the state control machine module, the clutch state monitoring circuit is connected with the reference voltage stabilizing circuit of the RF analog front end and provides a power supply voltage to the reference stabilizing circuit.

Beneficial effects of the present utility model: Compared with the existing lock and clutch state acquisition circuit, the clutch state monitoring circuit of the present utility model can be realized by using an integrated circuit device with the same technology as the electronic label chip, the circuit structure is simple, and the power consumption is low, so It can be integrated inside the electronic tag chip. The electronic tag integrated with the clutch state monitoring circuit is used as the IoT monitoring node for the circulation of containers and safes in the logistics industry, which can monitor the clutch state of containers and safes in time, ensuring the safety of the circulation of containers and safes. The electronic tag using the clutch state monitoring circuit takes into account the functions of ordinary passive UHF electronic tags in the radio frequency field, and can complete the record of the clutch state regardless of whether there is an external radio frequency field, and can also effectively reduce power consumption. The consumption and physical volume reduce the dependence on external power supply and enhance the practicability for various special applications.

Description of drawings

Fig. 1 is a schematic structural diagram of the clutch state monitoring circuit of the present invention.

Fig. 2 is a schematic structural diagram of an electronic tag adopting the clutch state monitoring circuit of the present invention.

Explanation of reference numerals: clutch signal switch S1, first inverter G1, second inverter G2, third inverter G3, PMOS transistor T1, power battery B1, latch D1, NAND gate C1, decoding Module 101, cycle check module 102, input preprocessing module 103, state control machine module 104, output preprocessing module 105, encoder module 106, memory access control module 107, pseudorandom number generator module 108, collision counter module 109. Timing counter module 110, clock generation module 111, reset generation module 112, MTP memory 113, rectification circuit 201, reference voltage stabilization circuit 202, modulation circuit 203, demodulation circuit 204, reset circuit 205, clock circuit 206.

Detailed ways

Below in conjunction with accompanying drawing and specific embodiment the utility model is described further.

As shown in Figure 1, the circuit structure of the clutch state monitoring circuit is as follows: including the first inverter G1, the second inverter G2, the third inverter G3, the PMOS transistor T1, the latch D1, and the NAND gate C1 . Here, the clutch signal switch S1 and the power supply battery B1 are used as external accessory parts of the clutch state monitoring circuit.

Combined with Figure 1, the connection methods of each device and port are as follows:

The first input terminal c of the NAND gate C1, the source of the PMOS transistor T1 and the input terminal D of the latch D1 are connected together as the input terminal of the clutch state signal of the clutch state monitoring circuit; The body end of the PMOS transistor T1 is connected to the external power battery B1, that is, connected to the positive pole of the external power battery B1; the second input terminal d of the NAND gate C1 is connected to the output terminal of the first inverter G1; The output terminal of the NAND gate C1 is connected to the enable terminal EN of the latch; the non-inverting output terminal Q of the latch is connected to the gate of the PMOS transistor T1; the drain of the PMOS transistor T1 is connected to the The electronic label outputs a power supply voltage; the level conversion unit is used to convert the drain voltage of the PMOS transistor T1 into a state signal switch_on for inputting to the digital baseband processor of the electronic label; the first inverter The input terminal of G1 inputs the voltage control signal power_control of the digital baseband processor of the electronic tag.

In this embodiment, the clutch state signal is characterized by the clutch signal switch S1, the positive pole of the external power battery B1 is connected to the first terminal a of the clutch signal switch S1, the negative pole is grounded, and the second terminal b of the clutch signal switch S1 is connected to the clutch signal switch S1. The input end of the clutch state signal of the state monitoring circuit is connected.

As a preferred solution of this embodiment, the level conversion unit includes a second inverter G2 and a third inverter G3, and the input terminal of the second inverter G2 is used as the input of the level conversion unit terminal is connected to the drain of the PMOS transistor T1, and the output terminal of the second inverter G2 is connected to the input terminal of the third inverter G3; the output terminal of the third inverter G3 is used as the The output terminal of the level conversion unit outputs the state signal switch_on to the digital baseband processor of the electronic tag.

Here, the power battery B1 can be a 3V button battery.

Combined with Figure 1, the working process of the clutch state monitoring circuit is as follows. For the sake of illustration, the clutch state of the electronic lock is taken as an example.

When the lock is closed, the switch S1 is turned off, the power battery B1 does not supply power to the tag chip, and the status signal switch_on and the voltage control signal power_control are both low.

When the lock is opened, the clutch signal switch S1 is closed, and the c terminal of the NAND gate C1, the D terminal of the latch D1, and the source of the PMOS transistor T1 are connected to a high voltage. At this time, the voltage control signal power_control is at a low level. After an inverter G1, a high level is input to the d terminal of the NAND gate C1, so that the enable terminal EN of the latch D1 is low level, the output terminal Q of the latch D1 is low level, and the PMOS transistor T1 is turned on, the power battery B1 is turned on to supply power to the electronic tag, the third inverter G3 outputs a high-level status signal switch_on, and the digital baseband processor counts the unlocking behavior.

When the lock continues to be in the open state, the digital baseband processor of the electronic tag pulls the voltage control signal power_control to a high level, at this time, the NAND gate C1 outputs a high level, and the Q terminal of the latch D1 outputs a high level , the PMOS tube T1 is cut off, the power supply battery B1 stops supplying power to the electronic tag, the status signal switch_on and the voltage control signal power_control both change to low level, the EN terminal of the latch D1 is 0, and the positive phase of the latch D1 The output terminal Q maintains a high level, the PMOS transistor T1 remains in a cut-off state, and the power battery B1 does not supply power to the electronic tag.

When the lock is closed again, the clutch signal switch S1 is disconnected, and the power supply battery B1 does not supply power to the electronic tag.

The structure of the electronic tag adopting the clutch state monitoring circuit is shown in Figure 2, including an antenna, a radio frequency analog front end and a digital baseband processor, the radio frequency analog front end includes a reference voltage stabilizing circuit, and the digital baseband processor includes a state control machine module , the electronic tag also includes a clutch state monitoring circuit, the clutch state monitoring circuit is connected to the state control machine module of the digital baseband processor and outputs the state signal switch_on to the state control machine module 104, and receives the state control machine module 104 input simultaneously The voltage control signal power_control, the clutch state monitoring circuit is connected to the reference voltage stabilizing circuit 202 of the RF analog front end and provides a power supply voltage to the reference stabilizing circuit 202 .

The specific structure of the RF analog front end of the above-mentioned electronic tag includes a rectification circuit 201, a reference voltage stabilizing circuit 202, a modulation circuit 203, a demodulation circuit 204, a reset circuit 205, and a clock circuit 206. The antenna passes through the interface of an ESD (anti-static protection circuit) The PAD is directly connected to the rectification circuit 201, the modulation circuit 203 and the demodulation circuit 204. The rectification circuit 201 converts the radio frequency signal received by the antenna into a DC power supply and divides the rectification low voltage and the rectification high voltage into the reference voltage stabilizing circuit 202. Voltage circuit 202 stabilizes the power supply, provides low power supply voltage 1V and high power supply voltage 1.8V for the digital baseband part of the electronic tag, provides 1.8V working voltage for modulation circuit 203, and provides 1.8V working voltage for demodulation circuit 204, clock circuit 206 and reset circuit 205 1V working voltage is provided, and the reference voltage stabilizing circuit 202 is also connected with the power supply voltage of the electronic tag output by the clutch state monitoring circuit. The monitoring circuit supplies power to the reference voltage stabilizing circuit 202; the demodulation circuit 204 recovers the demodulated data required by the digital baseband processor of the radio frequency identification from the radio frequency signal; the modulation circuit 203 uses the method of backscatter modulation to output the electronic tag digital baseband processor The modulated data is modulated to realize the data transmission from the electronic tag to the reader; the clock circuit 206 provides a stable system clock signal for the digital baseband processor, and the reset circuit 205 provides the required reset signal for the digital baseband processor.

The specific structure of the baseband processor of the above-mentioned electronic tag includes a digital baseband part including a state control machine module 104, a decoder module 101, an encoder module 106, a cyclic check module 102, a memory access control module 107, an input preprocessing module 103, an output preprocessing module Processing module 105 , pseudo-random number generator module 108 , collision counter module 109 , timer counter module 110 , clock generation module 111 , reset generation module 112 and MTP memory 113 . The decoder module 101 is connected to the input preprocessing module 103 and the cycle check module 102 respectively; the cycle check module 103 is connected to the output preprocessing module 105 and the encoder module 106; the memory access control module 107 is connected to the output preprocessing module 107. The processing module 105 is connected; after the demodulation data provided by the demodulation circuit 204 of the demodulation circuit 204 provided by the demodulator module 101 of the radio frequency analog front end, the decoder module 101 decodes and outputs the decoded data, and the decoded data is divided into two paths, all the way to the input preset Processing module 103, all the way to the cycle check module 102; the input preprocessing module 103 completes the input preprocessing of the decoded data, generates data to be processed and commands to be processed and outputs to the state control machine module 104; while the cycle check module After 103 completes the cyclic check of the decoded data, generate the cyclic check result and output it to the state control machine module 104; the state control machine module 104 detects the result of the clutch signal switch_on and the cyclic check module 102 input, and executes according to the checked situation Clutch records or receives pending data and commands to be processed. If the clutch signal switch_on is high level (here, the high level value is 1V, and the low level value is 0V), it means that the clutch state is on, and the unlock record is executed. , after being analyzed by the state control machine module 104, an address signal is generated to the memory access control module 107, and the relevant storage unit for storing the unlocking record is read and written, and after the execution is completed, the voltage control signal input to the clutch state monitoring circuit power_control is pulled high to a high level, if data and command processing are performed, after the analysis and processing by the state control machine module 104, five control signals are generated and sent to the pseudo-random number generator module 108, the collision counter module 109, and the timing counter module respectively 110, the clock generation module 111 and the reset generation module 112 generate address signals to the memory access control module 107, and output the pseudo-random number to be sent to the output preprocessing module 105; the memory access control module 107 passes the MTP memory input and output interface according to the address signal Access the MTP memory 113 and output the memory data to be sent to the output preprocessing module; the output preprocessing module 105 receives the pseudo-random number to be sent and the memory data to be sent, and generates the data to be sent to the cycle check module through the output preprocessing module 102; the cyclic check module 102 completes the cyclic code encoding of the data to be sent, generates the data to be encoded and outputs it to the encoder module 106; the encoder module 106 completes the encoding of the data to be encoded, generates the data to be modulated and outputs it to the RF analog front end The modulation circuit 203; the clock generation module 111 divides the system clock signal input by the clock circuit 206 of the RF analog front end to generate the clock signal required by each module, and the reset generation module 112 inputs the reset circuit 205 of the RF analog front end. The reset signal is processed synchronously to generate the reset signal required by each module in the digital baseband processor. The digital baseband processor is provided with 1.8V high level and 1V low level operating power supply voltage by the reference voltage stabilizing circuit 202 of the RF analog front end.

The following is a detailed introduction to the working process of the electronic tag using the clutch state monitoring circuit. For the convenience of explanation, here, the clutch state of the electronic lock is taken as an example.

Combined with Figure 2, when the electronic tag using the clutch state monitoring circuit (hereinafter referred to as the electronic tag) is in the radio frequency identification field, its working process is as follows:

Step (a): the electronic tag enters the radio frequency identification field, the radio frequency analog front end of the electronic tag is powered on, and the reference voltage stabilizing module 202 provides a low-level operating voltage and a high-level operating voltage for the digital baseband processor (low power in this embodiment Peaceful and high levels take values 1V, 1.8V respectively), the reset generation module 112 resets the state control machine module 104, the demodulation circuit 204 starts to demodulate the radio frequency signal received by the antenna, and the clutch state monitoring circuit collects the clutch state of the lockset;

Step (b): The state control machine module 104 detects the clutch state monitoring circuit. When the state signal switch_on is at a high level (here, the high level value is 1V, and the low level value is 0V), it means the clutch state of the lock is open, go to step (c); otherwise, the clutch state is off, go to step (d);

Step (c): The state control machine control module 104 generates an address signal to the memory access control module 107, reads and writes the relevant storage unit storing the unlocking record, updates the record data, and inputs the voltage control signal to the clutch state monitoring circuit power_control is pulled high to high level, if the power supply ends, go to step (m), otherwise go to step (d);

Step (d) state control machine module 104 is to decoder module 101, cycle check module 102, encoder module 106, input preprocessing module 103, output preprocessing module 105, memory access control module 107, pseudo-random number generator module 108, the collision counter module 109, the timing counter module 110, and the clock generation module 111 reset, read the data in the MTP memory 113, and calculate the cyclical check CRC result of the data;

Step (e) state control machine module 104 detects clutch state monitoring circuit, when state signal switch on is high level, promptly represents that the clutch state of lockset is to open, and changes over to step (c), otherwise changes over to step (f);

Step (f): the state control machine module 104 opens the decoder module 101, then turns off the clock of the state control machine module 104 itself, and the state control machine module 104 is in a dormant state;

Step (g): the decoder module 101 starts to detect the demodulated data input from the demodulation circuit 204 of the radio frequency analog front end, and when valid frame data is detected, the decoder module 101 wakes up the state control machine module 104;

Step (h): The state control machine module 104 turns on the input preprocessing module 103 and the cyclic check module 102, the decoder module 101 receives the demodulated data, decodes it through the decoder module, and outputs the decoded data, and the decoded data is divided into two paths , all the way to the input preprocessing module 103, all the way to the cycle check module 102; the input preprocessing module 103 completes the input preprocessing to the decoded data, generates the data to be processed and the command to be processed and outputs it to the state control machine module 104; while looping The verification module 102 completes the cyclic verification of the decoded data, generates a cyclic verification result and outputs it to the state control machine module 104;

Step (i): When the state control machine module 104 detects that the cyclic check of the decoded data by the cyclic check module 102 is completed, the state control machine module 104 turns off the decoder module 101, the input preprocessing module 103 and the cyclic check Module 102, while the state control machine module 104 receives the data to be processed and the command to be processed, generates a control signal after analyzing and processing the state control machine module, opens and performs a pseudo-random number generator module 108, a collision counter module 109 and The timing counter module performs operation 110, and closes the pseudo-random number generator module 108, the collision counter module 109 and the timing counter module 110 after the operation is completed;

Step (j): the state control machine module 104 opens the output preprocessing module 105 and the memory access control module 107, the state control machine module 104 outputs the address signal to the memory access control module 107, and outputs the pseudo-random number to be sent to the output preprocessing module 105; the memory access control module accesses the MTP memory through the MTP memory 113 input and output ports according to the address signal, and outputs the memory data to be sent to the output preprocessing module 105;

Step (k): the state control machine module 104 opens the cyclic check code module 102 and the encoder module 106, the output preprocessing module 105 receives the pseudo-random number to be sent and the memory data to be sent, and generates the data to be sent through the output preprocessing module 105 to the cyclic check module 102; the cyclic check module 102 completes the cyclic code encoding of the data to be sent, and outputs the data to be encoded after the cyclic code encoding to the encoder module 106; the encoder module 106 completes the cyclic code encoding after the cyclic code encoding Coding of encoded data, outputting the data to be modulated to the modulation circuit of the RF analog front end; after the RF analog front end modulation circuit modulates the data, the communication with the reader is realized through the antenna.

Step (1): after encoder module 106 encoding is finished, state control machine module 104 closes output preprocessing module 105, cycle check module 102, memory access control module 107 and encoder module 106, and state control machine module 104 checks power supply Whether the power is off, turn to step (m) after power off, otherwise go to step (e);

Step (m): Power down, all modules stop working.

When the electronic tag using the clutch state monitoring circuit is outside the radio frequency identification field, its working process is as follows:

Step (A): When the lock is opened, the clutch state monitoring circuit outputs a DC power supply voltage to the reference voltage stabilizing circuit 202 of the radio frequency analog front end of the electronic tag, and the radio frequency analog front end is powered on to work, and the reset generation module 112 of the baseband processor is to the state control machine module 104 resets, and the clutch state monitoring circuit monitors the clutch state of the lockset;

Step (B): The state control machine module 104 detects the clutch state monitoring circuit. When the state signal switch on is at a high level (here, the value of the high level is 1V, and the value of the low level is 0V), it means the clutch of the lock If the state is open, go to step (C); otherwise, the clutch state is off, go to step (D);

Step (C): The state control machine control module 104 generates an address signal to the memory access control module 107, reads and writes the relevant storage unit that stores the unlock record, updates the record data, and inputs the voltage control signal to the clutch state monitoring circuit power_control is pulled high to high level;

Step (D): The power supply of the clutch state monitoring circuit is powered off, the clutch state monitoring circuit stops supplying power to the reference voltage stabilizing circuit 202 of the RF analog front end, and the electronic tag stops working.

In summary, compared with the existing lock and clutch state acquisition circuit, the clutch state monitoring circuit of the present invention can be realized by using an integrated circuit device with the same technology as the electronic tag chip, the circuit structure is simple, and the power consumption is low, so it can be integrated in Inside the electronic tag chip. The electronic tag integrated with the clutch state monitoring circuit is used as the IoT monitoring node for the circulation of containers and safes in the logistics industry, which can monitor the clutch state of containers and safes in a timely manner, ensuring the safety of the circulation of containers and safes; The electronic tag takes into account the functions of ordinary passive UHF electronic tags in the radio frequency field, and can complete the record of the number of clutch states regardless of whether there is an external radio frequency field or not. Since the utility model adopts the passive ultra-high frequency electronic tag, it can also effectively reduce the consumption of power consumption and the volume of the object, reduce the dependence on external power supply, and enhance the practicability for various special application occasions.

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principle of the utility model, and it should be understood that the protection scope of the utility model is not limited to such specific statements and examples. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the utility model without departing from the essence of the utility model, and these variations and combinations are still within the protection scope of the utility model.

Claims (3)

1. A clutch state monitoring circuit for an electronic tag, characterized in that it includes: a PMOS transistor, a NAND gate, a first inverter, a level conversion unit and a latch, wherein the NAND gate The first input end, the source of the PMOS transistor and the input end of the latch are connected together as the input end of the clutch state signal of the clutch state monitoring circuit; the bulk end of the PMOS transistor is connected to an external power supply battery; the second input end of the NAND gate is connected with the output end of the first inverter; the output end of the NAND gate is connected with the enable end of the latch; the non-phase output of the latch The terminal is connected to the gate of the PMOS transistor; the drain of the PMOS transistor outputs a power supply voltage to the electronic label; the level conversion unit is used to convert the drain voltage of the PMOS transistor to be input to the The state signal of the digital baseband processor of the electronic tag; the input terminal of the first inverter inputs the voltage control signal of the digital baseband processor of the electronic tag. 2. The clutch state monitoring circuit according to claim 1, wherein the level conversion unit comprises a second inverter and a third inverter, and the input terminal of the second inverter serves as the The input end of the level conversion unit is connected to the drain of the PMOS transistor, the output end of the second inverter is connected to the input end of the third inverter; the output of the third inverter The terminal is used as the output terminal of the level conversion unit to output the state signal to the digital baseband processor of the electronic label. 3. An electronic tag adopting the clutch state monitoring circuit according to claim 1 or 2, the electronic tag includes an antenna, a radio frequency analog front end and a digital baseband processor, the radio frequency analog front end includes a reference voltage stabilizing circuit, the The digital baseband processor includes a state control machine module, wherein the electronic tag also includes a clutch state monitoring circuit, and the clutch state monitoring circuit is connected with the state control machine module of the digital baseband processor and outputs the state to the state control machine module signal, while receiving the voltage control signal input by the state control machine module, the clutch state monitoring circuit is connected with the reference voltage stabilizing circuit of the RF analog front end and provides a power supply voltage to the reference stabilizing circuit.

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