CN202182906U - Test socket for semiconductor chip - Google Patents
Test socket for semiconductor chip Download PDFInfo
- Publication number
- CN202182906U CN202182906U CN2011202053325U CN201120205332U CN202182906U CN 202182906 U CN202182906 U CN 202182906U CN 2011202053325 U CN2011202053325 U CN 2011202053325U CN 201120205332 U CN201120205332 U CN 201120205332U CN 202182906 U CN202182906 U CN 202182906U
- Authority
- CN
- China
- Prior art keywords
- chip
- main body
- guide plate
- probe
- socket
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000523 sample Substances 0.000 claims abstract description 21
- 239000011159 matrix material Substances 0.000 claims description 12
- 238000012856 packing Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000012423 maintenance Methods 0.000 abstract 1
- 230000003014 reinforcing effect Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000012797 qualification Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Images
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
Abstract
Provided is a test socket for a semiconductor chip, which is improved based on a conventional corresponding product. The test socket for a semiconductor chip comprises a probe (1), a chip socket main body (2), a probe maintenance plate (3) and a chip guide plate (4). The difference from the prior art is that the chip socket main body (2) is combined by a reinforcing plate (5) on the chip guide plate (4) and a chip socket base body (6) to be one body, thereby enhancing the strength of the chip socket main body (2) and minimizing deformation of the chip socket main body (2). Therefore, the welding ball of a chip is not liable to be contacted with the chip socket main body (2), the wearing level of the welding ball of the chip is reduced, and the qualified rate for testing the semiconductor chip is increased.
Description
Technical field
The utility model belongs to semicon industry, particularly a kind of semiconductor die testing equipment.
Background technology
Before the utility model was made, semiconductor die testing socket of the prior art also was by probe; The chip carrier socket matrix, the probe holding plate, critical pieces such as chip guide plate are formed; For strengthening the rigidity of test jack, stiffening plate is housed also on the chip guide plate generally.Yet; In semiconductor die package technology, spacing is more and more little, thereby causes the space between the solder sphere more and more little; Test jack of the prior art; Can't overcome the deflection of socket in the test process, thereby the solder sphere of chip very easily is worn in test process, cause product percent of pass to descend.
Summary of the invention
The purpose of the utility model; Be the structure of former semiconductor test socket is carried out a kind of improvement; It not only keeps the advantage of original semiconductor die testing socket, and overcomes and produce distortion, the drawback that is prone to be worn in the solder sphere test process of its chip; Thereby improve the semiconductor die testing qualification rate, make semiconductor test socket physical strength obtain further to improve simultaneously.
The purpose of the utility model is to realize through following technical scheme.The semiconductor die testing socket comprises probe, the chip carrier socket matrix; Probe holding plate and chip guide plate, probe are installed in the chip carrier socket matrix, are fixedly connected with the probe holding plate; The another side of chip carrier socket matrix, the spring and be connected with the chip guide plate of packing into is equipped with stiffening plate on its chip guide plate; With original stiffening plate on the chip guide plate, move and be filled on the chip carrier socket matrix, be combined into one; The compositing chip socket main body is simultaneously installed probe at it then, is connected with the probe holding plate again; The another side of chip carrier socket main body, the spring and be connected of packing into the chip guide plate.
Because the stiffening plate in the chip guide plate moves to be filled to and becomes an integral body on the chip carrier socket main body; Thereby strengthened the intensity of chip carrier socket main body; Reduced the distortion of chip carrier socket main body greatly, made the solder sphere of chip be difficult for contacting, greatly reduced the solder sphere degree of wear of chip with the chip carrier socket main body; Prevented chip in test process by secondary damage, improved the chip testing qualification rate.
Description of drawings
Accompanying drawing 1 is the utility model structure scheme of installation.
Accompanying drawing 2 is installed (side) synoptic diagram for the utility model structure.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is described further.
Embodiment, with shown in the accompanying drawing 2, the semiconductor die testing socket comprises probe 1 like accompanying drawing 1, chip carrier socket main body 2, probe holding plate 3 is formed with chip guide plate 4 critical pieces such as grade, and wherein chip carrier socket matrix 2 is made up of stiffening plate 5 and chip carrier socket matrix 6.At first stiffening plate 5 and chip carrier socket matrix 6 are processed into holistic chip carrier socket main body 2.Probe 1 is installed in the chip carrier socket main body 2, covers probe holding plate 3, and fastening with screw, make probe 1 remain in the chip carrier socket main body 2 not; Again by routine; With pack into the other end of chip carrier socket main body 2 of spring, cover chip guide plate 4, also use screw locking; Purpose is to prevent that chip guide plate 4 from scurrying out; Simultaneously also to keep chip guide plate 4 freely up and down within the specific limits, behind the EOT, can chip be ejected test position smoothly.As long as semi-conductor chip is placed on the chip guide plate 4,, just can reach test purpose to pressing down semi-conductor chip.
Claims (1)
1. the semiconductor die testing socket comprises probe (1), chip carrier socket matrix (6); Probe holding plate (3) and chip guide plate (4), probe (1) are installed in the chip carrier socket matrix (6), are fixedly connected with probe holding plate (3); The another side of chip carrier socket matrix (6), the spring and be connected with chip guide plate (4) of packing into is equipped with stiffening plate (5) on its chip guide plate (4); It is characterized in that: chip guide plate (4) is gone up original stiffening plate (5); Move and be filled on the chip carrier socket matrix (6), be combined into one compositing chip socket main body (2); Simultaneously install probe (1) at it then, be connected with probe holding plate (3) again; The another side of chip carrier socket main body (2), the spring and be connected of packing into chip guide plate (4).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011202053325U CN202182906U (en) | 2011-06-17 | 2011-06-17 | Test socket for semiconductor chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2011202053325U CN202182906U (en) | 2011-06-17 | 2011-06-17 | Test socket for semiconductor chip |
Publications (1)
Publication Number | Publication Date |
---|---|
CN202182906U true CN202182906U (en) | 2012-04-04 |
Family
ID=46175938
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2011202053325U Expired - Lifetime CN202182906U (en) | 2011-06-17 | 2011-06-17 | Test socket for semiconductor chip |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN202182906U (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104198772A (en) * | 2014-08-28 | 2014-12-10 | 安拓锐高新测试技术(苏州)有限公司 | Embedded chip testing socket and manufacturing method thereof |
CN106443419A (en) * | 2016-12-28 | 2017-02-22 | 上海捷策创电子科技有限公司 | Wafer level testing device and method |
CN107729581A (en) * | 2016-08-10 | 2018-02-23 | 苏州韬盛电子科技有限公司 | A kind of method and its application based on FEA design of Simulation chip testing socket structures |
-
2011
- 2011-06-17 CN CN2011202053325U patent/CN202182906U/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104198772A (en) * | 2014-08-28 | 2014-12-10 | 安拓锐高新测试技术(苏州)有限公司 | Embedded chip testing socket and manufacturing method thereof |
CN107729581A (en) * | 2016-08-10 | 2018-02-23 | 苏州韬盛电子科技有限公司 | A kind of method and its application based on FEA design of Simulation chip testing socket structures |
CN107729581B (en) * | 2016-08-10 | 2021-03-09 | 苏州韬盛电子科技有限公司 | Method for designing chip test socket structure based on FEA simulation and application thereof |
CN106443419A (en) * | 2016-12-28 | 2017-02-22 | 上海捷策创电子科技有限公司 | Wafer level testing device and method |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20120404 |