CN106443419A - Wafer level testing device and method - Google Patents
Wafer level testing device and method Download PDFInfo
- Publication number
- CN106443419A CN106443419A CN201611238602.6A CN201611238602A CN106443419A CN 106443419 A CN106443419 A CN 106443419A CN 201611238602 A CN201611238602 A CN 201611238602A CN 106443419 A CN106443419 A CN 106443419A
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- Prior art keywords
- test
- chip
- wlcsp
- pedestal
- testing
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000012360 testing method Methods 0.000 title claims abstract description 249
- 238000000034 method Methods 0.000 title abstract description 14
- 239000000523 sample Substances 0.000 claims abstract description 38
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 37
- 239000013078 crystal Substances 0.000 claims description 7
- 238000012546 transfer Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 238000013461 design Methods 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a wafer level testing device and method. The wafer level testing device comprises a testing cover, a testing seat and a testing plate, the testing cover is used for pressing a WLCSP (wafer level chip size packaging) testing chip into the testing seat and contacts with a testing probe inside the testing seat, and the testing seat contacts with the testing plate to transmit a signal output in the testing plate to the WLCSP testing chip through the testing probe. Through the wafer level testing device and method, multiple Sites can be designed on the testing seat for testing, space of the testing device is reduced, and capacity output is increased.
Description
Technical field
The present invention relates to IC design technical field, more particularly to a kind of wafer-level test device and method.
Background technology
In integrated circuit（IC）Be related to, manufacturing technology field, there are the needs that eliminates the false and retains the true, screen defect ware, prevent
Next process is entered, reduces the manufacturing expense of the redundancy in next process, this is accomplished by debugging and tests.
With the development of quasiconductor industry, packaging and testing for expenses such as cost-effective and tests, traditional chip testing one
As be：QFP（Pin）, QFN（Silver-colored foot）, BGA（Ball）Deng, it is packaged according to different requirements in encapsulation, traditional Socket is surveyed
Examination chip volume is big, can all increase cost etc. in packaging and transport.
In this regard, WLCSP（Wafer-Level Chip Scale Packaging Technology, wafer stage chip is encapsulated
Technology）That is wafer stage chip packaged type arises at the historic moment, its be different from traditional chip package mode (first cut and seal survey again, and
At least increase the volume of former chip 20% after encapsulation), the technology is first to carry out packaging and testing on full wafer wafer, then just cuts
Be cut into IC granule one by one, the volume after therefore encapsulating is equal to the life size of IC bare crystalline, its be known as be encapsulation technology not
Carry out main flow.
WLCSP holds on the wafer of wafer manufacturing flow process before the end and is done directly all of operation, in encapsulation process again
Chip is separated from wafer, so that WLCSP can realize the encapsulation volume with chip size identical minimum, this is almost
Final encapsulation microphotography.
However, due to WLCSP small volume, test request height, therefore Socket design part difficulty is increased, current
Testing scheme is typically all single site design, and less efficient and machine space is wasted.
Content of the invention
For overcoming the shortcomings of that above-mentioned prior art is present, the purpose of the present invention be to provide a kind of wafer-level test device and
Method, which can design multiple Site on test bench and be tested, and reduce test device space, increased production capacity output.
For reaching above and other purpose, the present invention proposes a kind of wafer-level test device, including：Test lid, test bench with
And test board, the test is covered for WLCSP test chip is pressed into the test bench, with the test spy inside the test bench
Pin is contacted, and the test bench is contacted with the test board, with the letter by exporting in test board described in the test probe transmission
Number arrive WLCSP test chip.
Further, the test bench includes guide housing, pedestal, and the guide housing is anchored on the pedestal, described
WLCSP test chip is put into the pedestal by the guide housing, is provided with the test probe, the test in the pedestal
Probe is contacted with the WLCSP test chip, and the pedestal is fixed on the test board.
Further, the test bench also includes base plate, and the base plate is used for for the test probe being installed on the base
Fixation after seat.
Further, the guide housing, pedestal and base plate be respectively provided with multiple, to realize multiple WLCSP test chips
Test
Further, the test lid is comprising locker, and the locker is used for for the test cover lock being buckled in described leading
To frame.
Further, the test probe is contacted with the chip ball of the WLCSP test chip.
For reaching above-mentioned purpose, the present invention also provides a kind of crystal wafer testing method, comprises the steps：
Step one, is put into WLCSP test chip in test bench using test lid, and test lid is installed on test bench；
Step 2, the test bench is installed on and is connected on the test board of test machine；
Step 3, requires to transfer signals to WLCSP test chip end by test board, test probe according to chip testing.
Further, step one is further included：
The WLCSP test chip is positioned on the guide housing of the test bench；
Using the locker of the test lid, the test cover lock is buckled in the guide housing；
When test, the WLCSP test chip is put into from the guide housing by pedestal by the pushing for test lid, with institute
State the test probe contact in pedestal.
Further, the pedestal is fixed on the test board.
Further, the test probe is contacted with the chip ball of the WLCSP test chip.
Compared with prior art, WLCSP is surveyed by a kind of wafer-level test device and method of the present invention by using test lid
Examination chip is pushed by guide housing and is put in pedestal, and test bench is installed on test board, by test board, tests probe by signal
It is transferred to WLCSP test chip end, it is achieved that the test of WLCSP, the present invention can design multiple Site on test bench and carry out
Test, reduces test device space, increased production capacity output.
Description of the drawings
Fig. 1 is a kind of structural representation of wafer-level test device of the present invention；
Fig. 2 is the detail structure chart of the wafer-level test device of the specific embodiment of the invention；
The step of Fig. 3 is a kind of crystal wafer testing method of present invention flow chart；
Fig. 4 and Fig. 5 is the schematic diagram of the wafer-level test of varying number chip in the specific embodiment of the invention.
Specific embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Further advantage and effect of the present invention is understood easily by content disclosed in the present specification.The present invention also can be different by other
Instantiation implemented or applied, the every details in this specification can also be based on different viewpoints and application, without departing substantially from
Various modifications and change is carried out under the spirit of the present invention.
Fig. 1 is a kind of structural representation of wafer-level test device of the present invention.As shown in figure 1, a kind of wafer scale of the present invention
Test device, including：Test lid（Socket Lid）1st, test bench（Socket）2 and test board（Load Board）3, its
In, test lid 1 is used for for WLCSP test chip 4 being pressed into test bench 2, contacts with the test probe inside test bench 2, test lid 1
It is mainly used in chip and pushes test, test bench 2, it is internally provided with test probe（Socket Pogo Pin）, test probe with
The chip ball contact of WLCSP test chip 4, carries out test chip function etc., test bench 2 and test by test probe transmission signal
Plate 3 is contacted, for by testing the signal for exporting in probe transmission test board 3 to WLCSP test chip 4, test board 3 is usual
Using test board, be generally connected with test machine, for deriving test signal.
Fig. 2 is the detail structure chart of the wafer-level test device of the specific embodiment of the invention.Wherein, test bench 2 includes to lead
To frame 5, pedestal 6 and base plate 7, test lid 1 is buckled in guide housing for test is covered 1 kayser, specifically with locker 8
Ground is said, the left and right sides of test lid 1 is provided with two buckles（Locker 8）, which can be stuck on guide housing, under chip
Pressure test, guide housing 2 is fixed on pedestal 6 by first fastener 9, during for testing, WLCSP test chip 4 is put into base
Seat 6, to contact in test probe 10, in the specific embodiment of the invention, guide housing is by being arranged at the screw at 4 angles（First
Clamp device 9）Pedestal 6 is directly fixed on, pedestal 6 is fixed on test board 3 by second fastener 11, specifically, pedestal 6 leads to
The fixed screw that crosses positioning pins and be arranged at 4 angles is locked in test board 3, and which is internally provided with test probe 10, its master
It is used for the installation of probe to be tested, connects with WLCSP test chip 4, test board 3 so as to meet test, base plate 7 is used for surveying
Sound out pin 10 and the fixation after pedestal 6 is installed on, in the specific embodiment of the invention, base plate 7 can reserve fixing lock in design
Determine hole to coordinate with pedestal 6, for fixation of the probe 10 after pedestal 6 is tested, allow test probe to be difficult after mounting to take off
Fall
The step of Fig. 3 is a kind of crystal wafer testing method of present invention flow chart.As shown in figure 3, a kind of wafer-level test of the present invention
Method, comprises the steps：
Step 301, is put into WLCSP test chip in test bench using test lid, test lid is installed on test bench, test
Can open under covering.Specifically, step 301 is further included：
Step S1, WLCSP test chip is positioned on the guide housing of test bench；
Step S2, is buckled in guide housing using the locker of test lid by cover lock is tested, in the specific embodiment of the invention, the survey
Examination lid left and right is provided with two buckles, is stuck in lid is tested on guide housing using buckle.
Step S3, when test, is pushed and for WLCSP test chip to be put into pedestal from guide housing by what test was covered, with base
Test probe contact in seat.
Step 302, test bench is installed on and is connected on the test board of test machine.Specifically, by the pedestal of test bench
It is fixed on test board, the pedestal is locked in test board by positioning pins and fixed screw, is mainly used in probe installation is tested,
Connect with WLCSP test chip, test board so as to meet test, the pedestal is installed on pedestal by a base plate by probe is tested
Interior, base plate can be reserved fixing lock hole and coordinate with pedestal in design, be mainly used in testing probe consolidating after pedestal
Fixed, so that test probe is difficult for drop-off after mounting.
Step 303, requires to transfer signals to WLCSP test chip by test board, test probe according to chip testing
End, to realize test purpose.
Here it should be noted that, the present invention is also can achieve using the test bench to multiple WLCSP test chips while carry out
Test, i.e., the test bench includes multiple pedestals and corresponding guide housing, and each pedestal has test probe, as shown in Figures 4 and 5 for
To two chips（Chip 1/2）, four chips（Chip 1/2/3/4）While the schematic diagram of test.
In sum, a kind of wafer-level test device and method of the present invention is covered WLCSP test chip by using test
Pushed by guide housing and be put in pedestal, test bench is installed on test board, transferred signals to by test board, test probe
WLCSP test chip end, it is achieved that the test of WLCSP, the present invention can design multiple Site on test bench and be tested,
Test device space is reduced, increased production capacity output.
Compared with prior art, the invention has the advantages that：
1st, former chip size minimum packaged type is employed：
The maximum feature of WLCSP wafer stage chip packaged type is effectively to reduce encapsulation volume, and packaging appearance is more frivolous.
Therefore can arrange in pairs or groups on running gear and meet the compact property requirements of portable product.
2nd, data transfer path is short, stability is high：
When encapsulating using WLCSP, as the circuit of wiring is short and thick, therefore the frequency range of data transfer can be effectively increased, reduce
Electric current consumes, and also lifts the stability of data transfer.As lightweight nude film is with self-calibrating characteristic in welding process, therefore
Assembling yield is higher.
3 heat dissipation characteristics are good：
As WLCSP has lacked the plastics of conventional seals or ceramic package, therefore heat energy during IC chip computing just effectively can dissipate,
And will not increase the temperature of main body, and this feature is benefited greatly for the heat dissipation problem of running gear.Inductance, raising can be reduced
Electric property.
Above-described embodiment only principle of the illustrative present invention and its effect, not for the restriction present invention.Any
Skilled person all can be modified to above-described embodiment and is changed without prejudice under the spirit and the scope of the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (10)
1. a kind of wafer-level test device, including：Test lid, test bench and test board, the test is covered for surveying WLCSP
Examination chip is pressed into the test bench, contacts with the test probe inside the test bench, and the test bench is connect with the test board
Touch, with the signal by exporting in test board described in the test probe transmission to WLCSP test chip.
2. a kind of wafer-level test device as claimed in claim 1, it is characterised in that：The test bench guide housing, pedestal, institute
State guide housing to be anchored on the pedestal, the WLCSP test chip is put into the pedestal, the pedestal by the guide housing
The test probe is inside provided with, the test probe is contacted with the WLCSP test chip, the pedestal is fixed on described
On test board.
3. a kind of wafer-level test device as claimed in claim 2, it is characterised in that：The test bench also includes base plate, institute
Base plate is stated for the test probe is installed on the fixation after the pedestal.
4. a kind of wafer-level test device as claimed in claim 3, it is characterised in that：The guide housing, pedestal and base plate
Be respectively provided with multiple, to realize the test of multiple WLCSP test chips.
5. a kind of wafer-level test device as claimed in claim 3, it is characterised in that：The test is covered comprising locker,
The locker is used for for the test cover lock being buckled in the guide housing.
6. a kind of wafer-level test device as claimed in claim 1, it is characterised in that：The test probe and the WLCSP
The chip ball contact of test chip.
7. a kind of crystal wafer testing method, comprises the steps：
Step one, is put into WLCSP test chip in test bench using test lid, and test lid is installed on test bench；
Step 2, the test bench is installed on and is connected on the test board of test machine；
Step 3, requires to transfer signals to WLCSP test chip end by test board, test probe according to chip testing.
8. a kind of crystal wafer testing method as claimed in claim 1, it is characterised in that step one is further included：
The WLCSP test chip is positioned on the guide housing of the test bench；
Using the locker of the test lid, the test cover lock is buckled in the guide housing；
When test, the WLCSP test chip is put into from the guide housing by pedestal by the pushing for test lid, with institute
State the test probe contact in pedestal.
9. a kind of crystal wafer testing method as claimed in claim 8, it is characterised in that:The pedestal is fixed on the test
On plate.
10. a kind of crystal wafer testing method as claimed in claim 8, it is characterised in that：The test probe and the WLCSP
The chip ball contact of test chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611238602.6A CN106443419A (en) | 2016-12-28 | 2016-12-28 | Wafer level testing device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611238602.6A CN106443419A (en) | 2016-12-28 | 2016-12-28 | Wafer level testing device and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106443419A true CN106443419A (en) | 2017-02-22 |
Family
ID=58215969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611238602.6A Pending CN106443419A (en) | 2016-12-28 | 2016-12-28 | Wafer level testing device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106443419A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109031102A (en) * | 2018-09-20 | 2018-12-18 | 北方电子研究院安徽有限公司 | A kind of apparatus for testing chip |
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2016
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|---|---|---|---|---|
| US6340838B1 (en) * | 1998-04-08 | 2002-01-22 | Samsung Electronics Co., Ltd. | Apparatus and method for containing semiconductor chips to identify known good dies |
| US20060053346A1 (en) * | 2004-09-07 | 2006-03-09 | Via Technologies, Inc. | Chip tester for testing validity of a chipset |
| TWM299854U (en) * | 2006-04-25 | 2006-10-21 | Chroma Ate Inc | Contacting apparatus for testing electronic components |
| CN101393250A (en) * | 2007-09-20 | 2009-03-25 | 采钰科技股份有限公司 | Test socket and test board for wafer level semiconductor testing |
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| CN109031102B (en) * | 2018-09-20 | 2021-03-30 | 北方电子研究院安徽有限公司 | Chip testing device |
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| PB01 | Publication | ||
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Application publication date: 20170222 |