CN202502116U - Large tray for chip testing - Google Patents

Large tray for chip testing Download PDF

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Publication number
CN202502116U
CN202502116U CN2011204619120U CN201120461912U CN202502116U CN 202502116 U CN202502116 U CN 202502116U CN 2011204619120 U CN2011204619120 U CN 2011204619120U CN 201120461912 U CN201120461912 U CN 201120461912U CN 202502116 U CN202502116 U CN 202502116U
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CN
China
Prior art keywords
test
chip
big pallet
circuit board
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2011204619120U
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Chinese (zh)
Inventor
金英杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN2011204619120U priority Critical patent/CN202502116U/en
Application granted granted Critical
Publication of CN202502116U publication Critical patent/CN202502116U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model relates to the chip test equipment field, especially to a chip test tray on the chip test equipment, wherein the chip test tray is used for loading to-be-tested chips. The provided large tray includes a large tray body that is provided with test socket installation holes, wherein the test socket installation holes on the large tray body are arranged in a vertical and horizontal matrix mode; a circuit board is fixed under the large tray body and test sockets that correspond to all the test socket installation holes and are used for placing to-be-tested chips are arranged on the circuit board. According to the test tray for chip testing provided by the utility model, chip test bits in a matrix arrangement are used to test a plurality of to-be-tested chips. Compared with a previous single or single-row test tray, the provided large tray enables the number of a batch of test chips to be substantially improved and the efficiency of chip batch testing to be enhanced, so that testing of mass and high efficient testing of chip testing machines can be carried out conveniently.

Description

The big pallet of chip testing
Technical field
The utility model relates to the chip testing apparatus field, especially is used to load the chip testing pallet of chip to be measured on the chip testing equipment.
Technical background
In the chip testing field; When using chip testing machine that chip is tested; Need will chip to be measured to be loaded into and get into test machine on the test pallet and test, existing test pallet is generally a plurality of chips single or side by side and places the position, owing to the width limitations of test machine; The quantity of a plurality of chips placements position that is arranged side by side is also very limited, has influenced the efficient of batch testing greatly.
Summary of the invention
It is many to the purpose of this invention is to provide a kind of number of chips of carrying, and improves the big pallet of chip testing of testing efficiency.
In order to realize above purpose, the utility model adopts following technical scheme:
It comprises a big pallet; Said big pallet is provided with the test bench mounting hole; Its improvement is: the test bench mounting hole on the described big pallet is matrix form arrangement in length and breadth; Described big pallet bottom fixing circuit board, the position of corresponding each test bench mounting hole is provided with the test bench of placing chip to be measured on the circuit board.
Preferably, a plurality of circuit boards that comprise discharging arranged side by side under the described big pallet.
Preferably, described each circuit board is provided with two row, eight row test benches.
Preferably, described big pallet is provided with the fixed orifice of a plurality of fixing test seats of matrix in length and breadth.
Preferably, the position of the corresponding test bench of said each circuit board is provided with the dowel hole that is connected of being convenient to test bench and circuit board.
Preferably, described big pallet front end side is provided with the cushion block that extends along big pallet side.
Owing to adopted said structure; The big pallet of the chip testing of the utility model is tested a plurality of chips to be measured through the chip testing position of arranged; With respect to single or single test pallet in the past; Improved the quantity of one batch of test chip greatly, improved the efficient of chip batch testing, helped in enormous quantities, chip testing machine test efficiently.
Description of drawings
Fig. 1 is the parts explosive view of the utility model embodiment.
The utility model purpose, function and advantage will combine embodiment, further specify with reference to accompanying drawing.
Embodiment
As depicted in figs. 1 and 2; The big pallet of the chip testing of present embodiment comprises a big pallet 1; Said big pallet 1 is provided with test bench mounting hole 2; Test bench mounting hole 2 on the described big pallet 1 is matrix form arrangement in length and breadth, described big pallet 1 bottom fixing circuit board 3, and the position of corresponding each test bench mounting hole 2 is provided with the test bench 4 of placing chip to be measured on the circuit board 3.
Because according to the needs that detect, the size of big pallet can have a lot of specifications, if the big pallet of every kind of specification is all fixed the circuit board of a corresponding specification; Then need produce the circuit board of multiple different size, make troubles for the design and the production of circuit board, in order to realize unification to board design and production; The a plurality of circuit boards 3 that comprise discharging arranged side by side under the described big pallet, the combination through polylith circuit board 3 cooperate the position, hole of the big pallet of different size to be provided with, in the present embodiment; Because big pallet mountain is provided with 72 test bench mounting holes 2; Need 72 corresponding test benches, so in the present embodiment, described each circuit board 3 is provided with two row, eight row test benches 3.
In order to realize fixing between big pallet and each circuit board and effectively to utilize limited space, in the present embodiment, described big pallet 1 is provided with a plurality of longitudinally fixed orifices 5, and the position of the corresponding fixed orifice of said each circuit board is provided with dowel hole 6.
In the present embodiment, described big pallet front end side is provided with the cushion block that extends along big pallet side.
The above is merely the preferred embodiment of the utility model; Be not thus the restriction the utility model claim; Every equivalent structure or equivalent flow process conversion that utilizes the utility model instructions and accompanying drawing content to be done; Or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the utility model.

Claims (6)

1. big pallet of chip testing; Comprise a big pallet; Said big pallet is provided with the test bench mounting hole; It is characterized in that: the test bench mounting hole on the described big pallet is matrix form arrangement in length and breadth, described big pallet bottom fixing circuit board, and the position of corresponding each test bench mounting hole is provided with the test bench of placing chip to be measured on the circuit board.
2. the big pallet of chip testing as claimed in claim 1 is characterized in that: a plurality of circuit boards that comprise discharging arranged side by side under the described big pallet.
3. the big pallet of chip testing as claimed in claim 2 is characterized in that: described each circuit board is provided with two row, eight row test benches.
4. the big pallet of chip testing as claimed in claim 3 is characterized in that: described big pallet is provided with a plurality of fixed orifices of matrix in length and breadth, fixing test seat.
5. the big pallet of chip testing as claimed in claim 4 is characterized in that: the position of the corresponding test bench of said each circuit board is provided with dowel hole, is convenient to being connected of test bench and circuit board.
6. the big pallet of chip testing as claimed in claim 5 is characterized in that: described big pallet front end side is provided with the cushion block that extends along big pallet side.
CN2011204619120U 2011-11-18 2011-11-18 Large tray for chip testing Expired - Fee Related CN202502116U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011204619120U CN202502116U (en) 2011-11-18 2011-11-18 Large tray for chip testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011204619120U CN202502116U (en) 2011-11-18 2011-11-18 Large tray for chip testing

Publications (1)

Publication Number Publication Date
CN202502116U true CN202502116U (en) 2012-10-24

Family

ID=47038727

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011204619120U Expired - Fee Related CN202502116U (en) 2011-11-18 2011-11-18 Large tray for chip testing

Country Status (1)

Country Link
CN (1) CN202502116U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106443419A (en) * 2016-12-28 2017-02-22 上海捷策创电子科技有限公司 Wafer level testing device and method
CN107229014A (en) * 2017-06-30 2017-10-03 深圳赛意法微电子有限公司 Chip testing carrier and chip testing devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106443419A (en) * 2016-12-28 2017-02-22 上海捷策创电子科技有限公司 Wafer level testing device and method
CN107229014A (en) * 2017-06-30 2017-10-03 深圳赛意法微电子有限公司 Chip testing carrier and chip testing devices
CN107229014B (en) * 2017-06-30 2023-06-13 深圳赛意法微电子有限公司 Chip test carrier and chip test equipment

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121024

Termination date: 20141118

EXPY Termination of patent right or utility model