CN202177655U - Special digital storage oscillograph for lightning stroke use - Google Patents

Abstract

The utility model provides a special digital storage oscillograph for lightning stroke use. The oscillograph comprises a signal conditioning and trigger signal generating circuit, a time sequence distributor circuit, a sampling keep circuit, an ADC (Analog to Digital Converter) singlechip circuit, a main-control singlechip circuit, a power supply circuit, a display interface unit, and a computer communication serial port, wherein the signal conditioning and trigger signal generating circuit, the sampling keep circuit, and the ADC singlechip circuit are connected sequentially; the time sequence distributor circuit is connected with the sampling keep circuit and the ADC singlechip circuit respectively; the signal conditioning and trigger signal generating circuit, the ADC singlechip circuit, and the power supply circuit are all connected to the main-control singlechip circuit; the computer communication serial port is connected with the main-control singlechip circuit; the signal conditioning and trigger signal generating circuit is connected with the signal end of an external lightning stroke current signal input socket; and the display interface unit is connected with the main-control singlechip circuit, as well as an external display. The utility model can meet special requirement on lightning stroke current waveform collection.

Description

Thunderbolt special digital storage oscilloscope

Technical field

The utility model relates to the oscillograph technical field, particularly a kind of thunderbolt special digital storage oscilloscope.

Background technology

Digital storage oscilloscope DSO (digital storage oscilloscope) is owing to have the incomparable advantage of analog oscilloscope, and development in the last few years very rapidly.Digital storage oscilloscope is one of common instrument of electronic signal measurement, and it all has a wide range of applications like fields such as machinery, electronics, military affairs and research and teachings in all trades and professions.Existing universal digital storage oscillograph involves great expense; Complex design; Be used for high speed acquisition more and analyze periodic waveform clocklike, normal extensive field programmable gate array logic device FPGA, FIFO pushup storage, dma controller, high speed analog-digital conversion A/D converter (being called for short ADC), digital signal microprocessor DSP and other High-speed Control interface chips etc. of adopting on technology realizes.The virtual digit storage oscilloscope generally is based on PC (PC), good use PC High-speed Control and analyze function such as demonstration easily, but the data collecting card of its front end technical sophistication still, cost is high.Because thunder-strike current waveform its own particularity, and consider targetedly that from cost and function aforementioned two kinds of digital storage oscilloscopes all can not satisfy the requirement of being struck by lightning well, the digital storage oscilloscope of necessary design special.

Thunder and lightning is a kind of spontaneous phenomenon that can cause major disaster.Along with the development of human economic society, the disaster that causes because of thunder and lightning also gets more and more.Human monitoring record to the thunder and lightning disaster has for a long time.Several thousand meteorological stations that China sets up in meteorological department all have thunder and lightning observational record in recent decades, but these records mostly lack quantification.At present, country has realized that and builds the necessity of lightning monitoring net on a large scale that meteorological department includes the construction of this system in development plan.The foundation of lightning monitoring net will play a significant role, and the detection of thunder-strike current waveform research is wherein of paramount importance link, abundant thunderbolt parameter can be provided, for quantitative test provides reliable basis.

Thunder-strike current waveform by Rogowski coil (Luo Shi coil) induction generally continues about 10～500us (microsecond), in the about 100us of wave head, and the about 1～5us of wave head rising edge ascending time, and often with vibration.The waveform dominant frequency is composed about 5～7KHz (KHz) near the thunderbolt source region, than the about 10～500KHz in territory, far field.According to Shannon's sampling theorem, maximum available sampling bandwidth is equivalent to the half the of SF, and therefore oscillographic SF must be greater than 1MHz (megahertz).

The utility model content

The fundamental purpose of the utility model is to overcome the shortcoming of above-mentioned prior art with not enough, and a kind of thunderbolt special digital storage oscilloscope that can fine satisfied thunderbolt requirement is provided.

For reaching above-mentioned purpose, the utility model adopts following technical scheme:

Thunderbolt special digital storage oscilloscope; Comprise that signal condition and trigger pip produce circuit, timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit, power circuit, display interface device unit and compunication serial port; Said signal condition and trigger pip generation circuit, sampling hold circuit, ADC single chip circuit connect successively, and timing distribution circuit connects sampling hold circuit, ADC single chip circuit respectively; Said signal condition and trigger pip generation circuit, ADC single chip circuit, power circuit are connected with the main control singlechip circuit respectively; The compunication serial port connects the main control singlechip circuit, and external computing machine; Said signal condition and trigger pip produce the signal end that circuit connects outside thunder-strike current signal input socket; Said power circuit comprises first output terminal, second output terminal and the 3rd output terminal; Its first output terminal, second output terminal, the 3rd output terminal all connect signal condition and trigger pip produces circuit, and said the 3rd output terminal connects timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit respectively; Said display interface device unit connects the main control singlechip circuit, and external display.

Said signal condition and trigger pip produce circuit and comprise impedance inverter circuit, isolation buffer circuit, half-wave rectifying circuit and main control singlechip interrupt control circuit; Said impedance inverter circuit comprises first operational amplifier; First operational amplifier comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input and first output terminal, and the positive source incoming end of said first operational amplifier, power cathode incoming end connect first output terminal, second output terminal of power circuit respectively; First in-phase input end of first operational amplifier connects the signal end of outside thunder-strike current signal input socket; First inverting input of first operational amplifier connects its first output terminal, and first output terminal of first operational amplifier connects half-wave rectifying circuit; Said half-wave rectifying circuit connects first output terminal, second output terminal of power circuit respectively;

Said isolation buffer circuit comprises second operational amplifier; Second operational amplifier comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input, first output terminal, second in-phase input end, second inverting input and second output terminal; The positive source incoming end of second operational amplifier connects first output terminal of power circuit, its power cathode incoming end ground connection; First in-phase input end of second operational amplifier connects half-wave rectifying circuit; First inverting input of second operational amplifier connects its first output terminal, and first output terminal of second operational amplifier connects sampling hold circuit, main control singlechip interrupt control circuit; Second in-phase input end of second operational amplifier connects half-wave rectifying circuit, and second inverting input of second operational amplifier connects its second output terminal, and its second output terminal connects sampling hold circuit, main control singlechip interrupt control circuit;

Said main control singlechip interrupt control circuit connects the 3rd output terminal, the main control singlechip circuit of power circuit respectively.

Half-wave rectifying circuit comprises first resistance, first diode, second diode, the 3rd resistance, the 3rd operational amplifier, the 3rd diode, the 4th diode, second resistance and the 4th resistance; Said the 3rd operational amplifier comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input, first output terminal, second in-phase input end, second inverting input and second output terminal; The positive source incoming end of the 3rd operational amplifier, power cathode incoming end connect first output terminal, second output terminal of power circuit respectively; The positive pole of first diode connects first inverting input of the 3rd operational amplifier, and its negative pole connects first output terminal of the 3rd operational amplifier; The positive pole of second diode connects first output terminal of the 3rd operational amplifier, and its negative pole connects first in-phase input end of second operational amplifier; One end of said first resistance connects the positive pole of first diode, and its other end connects the negative pole of second diode; One end of the 3rd resistance connects first output terminal of first operational amplifier, and its other end connects first inverting input of the 3rd operational amplifier; The first in-phase input end ground connection of the 3rd operational amplifier, its second in-phase input end connects an end of the 4th resistance, and the other end of the 4th resistance connects first output terminal of first operational amplifier; Second inverting input of the 3rd operational amplifier connects the positive pole of the 4th diode, and its second output terminal connects the negative pole of the 4th diode; The positive pole of the 3rd diode connects the negative pole of the 4th diode, and its negative pole connects second in-phase input end of second operational amplifier; One end of second resistance connects the positive pole of the 4th diode, and its other end connects the negative pole of the 3rd diode.

The main control singlechip interrupt control circuit comprises first electric capacity, the 6th resistance, the 7th resistance, the 8th resistance, high-speed comparator and the 5th resistance, and said high-speed comparator comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input, first output terminal, second in-phase input end, second inverting input and second output terminal; One end of the 7th resistance connects the 3rd output terminal of power circuit, and its other end connects first in-phase input end of high-speed comparator; First inverting input of high-speed comparator connects first output terminal of second operational amplifier, and first output terminal of high-speed comparator connects an end of main control singlechip circuit, the 6th resistance respectively; The other end of the 6th resistance connects the 3rd output terminal of power circuit; The positive pole of first electric capacity connects the 3rd output terminal of power circuit, the minus earth of first electric capacity; The two ends of said the 8th resistance connect first in-phase input end of high-speed comparator, the power cathode incoming end of high-speed comparator respectively; The power cathode incoming end ground connection of high-speed comparator, its positive source incoming end connects the 3rd output terminal of power circuit; Second inverting input of high-speed comparator connects second output terminal of second operational amplifier, and second output terminal of high-speed comparator connects the main control singlechip circuit; One end of the 5th resistance connects the positive source incoming end of high-speed comparator, and its other end connects second output terminal of high-speed comparator; Second in-phase input end of high-speed comparator is connected with first in-phase input end.

Signal condition and trigger pip produce circuit and also comprise second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 5th diode, the 6th diode, the 7th diode and the 8th diode; The plus earth of said the 5th diode, its negative pole connect first in-phase input end of second operational amplifier; The plus earth of said the 6th diode, its negative pole connect second in-phase input end of second operational amplifier; The minus earth of the 7th diode, its anodal positive pole that connects the 8th diode, the negative pole of the 8th diode connects first in-phase input end of first operational amplifier; The positive pole of the positive pole of said the 3rd electric capacity, the 4th electric capacity all connects the positive source incoming end of second operational amplifier; The positive pole of the 5th electric capacity connects the positive source incoming end of the 3rd operational amplifier; The positive pole of the 8th electric capacity connects the positive source incoming end of first operational amplifier, and the negative pole of the 3rd electric capacity, the negative pole of the 4th electric capacity, the negative pole of the 5th electric capacity, the equal ground connection of negative pole of the 8th electric capacity; The negative pole of said second electric capacity connects the power cathode incoming end of first operational amplifier; The negative pole of the negative pole of the 6th electric capacity, the 7th electric capacity all connects the power cathode incoming end of the 3rd operational amplifier, and anodal all ground connection of the positive pole of the positive pole of second electric capacity, the 6th electric capacity, the 7th electric capacity.

Said sampling hold circuit comprises that first group of high-speed analog switch, second group of high-speed analog switch and several samplings keep electric capacity; First group of high-speed analog switch, second group of high-speed analog switch comprise several high-speed analog switchs respectively, and each high-speed analog switch includes positive source incoming end, power cathode incoming end, first input end, second input end, the 3rd input end, four-input terminal, the 5th input end, the 6th input end, the 7th input end, the 8th input end, first output terminal, second output terminal, the 3rd output terminal and the 4th output terminal; The positive source incoming end of said each high-speed analog switch all connects the 3rd output terminal of power circuit; The equal ground connection of power cathode incoming end of said each high-speed analog switch; Corresponding respectively several sampling maintenance electric capacity that connects of said each high-speed analog switch; Corresponding respectively first output terminal, second output terminal, the 3rd output terminal, the 4th output terminal that is connected to each high-speed analog switch of positive pole that each is sampled and keeps electric capacity, and the equal ground connection of negative pole of each sampling maintenance electric capacity;

First output terminal of each high-speed analog switch, second output terminal, the 3rd output terminal, the 4th output terminal are connected in the ADC single chip circuit respectively accordingly;

First input end, second input end, the 3rd input end, the four-input terminal of each high-speed analog switch in first group of high-speed analog switch all connects first output terminal of second operational amplifier; First input end, second input end, the 3rd input end, the four-input terminal of each high-speed analog switch in second group of high-speed analog switch all connects second output terminal of second operational amplifier;

The 5th input end of each high-speed analog switch, the 6th input end, the 7th input end, the 8th input end connect timing distribution circuit respectively accordingly.

The positive source incoming end of each high-speed analog switch also is connected with power filtering capacitor respectively, the equal ground connection of the other end of power filtering capacitor.

Said timing distribution circuit comprises sequential distribution control single chip computer, active crystal oscillator, clock chip, clock chip crystal oscillator and battery, and said sequential distributes control single chip computer to comprise control signal output ends, oscillator incoming end, positive source incoming end and power cathode incoming end; Said sequential is distributed the 3rd output terminal of the positive source incoming end connection power circuit of control single chip computer, its power cathode incoming end ground connection; It is several that said sequential is distributed the control signal output ends of control single chip computer; Each control signal output ends is connected to the 5th input end, the 6th input end, the 7th input end, the 8th input end of each high-speed analog switch of every group of high-speed analog switch respectively accordingly, and each control signal output ends also connects the ADC single chip circuit respectively; Said active crystal oscillator comprises positive source input end, power cathode input end and oscillation output end; Its oscillation output end connects the oscillator incoming end that said sequential is distributed control single chip computer; Its positive source input end connects the 3rd output terminal of power circuit, its power cathode input end grounding;

Said clock chip comprises that first input end, second input end, the 3rd input end, four-input terminal, the 5th input end, exterior read-write synchronous clock input end, clock data input/output terminal and sheet select input end; The first input end of said clock chip connects the 3rd output terminal of power circuit, corresponding respectively two output terminals that connect the clock chip crystal oscillator of its second input end, the 3rd input end; The four-input terminal ground connection of clock chip, the 5th input end of clock chip connects the positive pole of battery, the minus earth of battery; Exterior read-write synchronous clock input end, clock data input/output terminal and the sheet of said clock chip select input end to be connected with resistance respectively, and the other end of said resistance all is connected to the 3rd output terminal of power circuit; Exterior read-write synchronous clock input end, clock data input/output terminal and the sheet of said clock chip select input end all to be connected the main control singlechip circuit.

Said ADC single chip circuit comprises several ADC single-chip microcomputers and the active crystal oscillator of several ADC single-chip microcomputers, and each ADC single-chip microcomputer has included serial line interface input end, serial line interface output terminal, active crystal oscillator input end, sequential distributing signal input end, power cathode input end, positive source input end, sampled signal conversion input end, sample conversion concluding time marking signal output terminal and main control singlechip signal input end; The positive source input end of each ADC single-chip microcomputer all connects the 3rd output terminal of power circuit, the equal ground connection of its power cathode input end; Corresponding respectively first output terminal, second output terminal, the 3rd output terminal, the 4th output terminal that connects each high-speed analog switch of sampling hold circuit of sampled signal conversion input end of each ADC single-chip microcomputer; The sequential distributing signal input end of each ADC single-chip microcomputer is connected to the control signal output ends of timing distribution circuit respectively accordingly; The sample conversion concluding time marking signal output terminal of each ADC single-chip microcomputer, main control singlechip signal input end, serial line interface input end, serial line interface output terminal connect the main control singlechip circuit respectively; The active crystal oscillator of each ADC single-chip microcomputer includes positive source input end, power cathode input end and oscillation output end; Its positive source input end all connects the 3rd output terminal of power circuit; The equal ground connection of its power cathode input end, its oscillation output end all connect the active crystal oscillator input end of corresponding ADC single-chip microcomputer;

The main control singlechip circuit comprises main control singlechip, the active crystal oscillator of main control singlechip, first driver, second driver, storage chip and button; The active crystal oscillator of main control singlechip, first driver, second driver, storage chip all are connected with main control singlechip; And the active crystal oscillator of main control singlechip, first driver, second driver, storage chip all are connected with the 3rd output terminal of power circuit, and first driver, second driver also connect the sample conversion concluding time marking signal output terminal of each ADC single-chip microcomputer respectively; Said button connects main control singlechip, and connects the 3rd output terminal of power circuit through resistance.

Thunderbolt special digital storage oscilloscope measuring process by above-mentioned thunderbolt special digital storage oscilloscope is realized comprises the steps:

(1) power circuit insert outside+5V ,+12V ,-the power supply input of 12V; And be translated into+5V ,+9V ,-9V; Be respectively signal condition and trigger pip produce circuit and provide+9V ,-9V ,+input of 5V power supply, provide+the power supply input of 5V for timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit simultaneously;

(2) signal condition and trigger pip produce circuit and receive outside thunder-strike current signal; It is cushioned conditioning handles; And the sampling negative value signal that processing is obtained, sampling are sent in the sampling hold circuit on the occasion of signal; Simultaneously, produce negative trigger pip, positive trigger pip, negative trigger pip, positive trigger pip are sent to the main control singlechip circuit; Specific as follows:

Signal condition and trigger pip produce in the circuit; The signal end of outside thunder-strike current signal input socket is imported outside thunder-strike current signal to first in-phase input end of first operational amplifier; Outside thunder-strike current signal is realized impedance conversion through first operational amplifier; Isolated the influence of late-class circuit, and produced the voltage follow signal, by first output terminal output of first operational amplifier signal input part; This voltage follow signal also carries out strong feedback processing by first inverting input input of first operational amplifier simultaneously, and signal stabilization is followed; The voltage follow signal is as the input signal of the 3rd operational amplifier; And get in first inverting input, second in-phase input end of the 3rd operational amplifier through the 3rd resistance, the 4th resistance respectively; The voltage follow signal is carried out half-wave rectification by the 3rd operational amplifier and is divided into two-way output; Wherein one tunnel isolation waveform is on the occasion of part; Only allow negative loop to pass through and anti-phase generation waveform negative value signal, waveform negative value signal is exported by first output terminal of the 3rd operational amplifier, and imports first in-phase input end of second operational amplifier through first diode, second diode, first resistance; Another road isolation waveform negative loop; Only allow on the occasion of part through producing waveform on the occasion of signal; Waveform is exported by second output terminal of the 3rd operational amplifier on the occasion of signal, and imports second in-phase input end of second operational amplifier through the 3rd diode, the 4th diode, second resistance; Since waveform negative value signal and waveform on the occasion of the driving force of signal very a little less than; So utilize second operational amplifier that waveform negative value signal, waveform are carried out isolation buffer on the occasion of signal once more; Produce sampling negative value signal and sampling on the occasion of signal, be input in the sampling hold circuit respectively and be input to respectively in first inverting input, second inverting input of high-speed comparator by first output terminal, second output terminal of second operational amplifier; Sampling negative value signal is very strong on the occasion of the driving force of signal with sampling, moment output current can reach 1.3A, satisfy late-class circuit fully and drive needs, be used for the A/D conversion; Waveform negative value signal, waveform respectively have a 5.2V amplitude limit stabilivolt (the 5th diode and the 6th diode) on the occasion of signal end; Guarantee that sampling negative value signal is no more than 5.5V with sampling on the occasion of the voltage of signals value; For guaranteeing safety, outside thunder-strike current signal also is limited in by the stabilivolt of two differential concatenations (the 7th diode and the 8th diode) ± 6.8V in; Sampling negative value signal also produces negative trigger pip and positive trigger pip (benchmark voltage is 500mV) respectively through high-speed comparator with sampling on the occasion of signal; Negative trigger pip is sent to the main control singlechip circuit respectively with positive trigger pip; The trigger pip (interruption input signal) that is used for main control singlechip starts the ADC single chip circuit and identification is the triggering that negative pulse or positive pulse cause;

(3) timing distribution circuit produces control signal according to certain rule circulation; And control signal is sent to the 5th input end, the 6th input end, the 7th input end, the 8th input end of each high-speed analog switch in the sampling hold circuit accordingly, be sent to the sequential distributing signal input end of each ADC single-chip microcomputer simultaneously respectively accordingly; Specific as follows:

Sequential in the timing distribution circuit distributes control single chip computer according to [K1=0, K5=1], [K2=0, K6=1], [K3=0; K7=1] ... [K15=0, K3=1], [K16=0, K4=1], [K1=0; K5=1] rule circulation (0 expression low level wherein; 1 expression high level, down together), produce control signal K1～K16; Control signal K1～K16 distributes the control signal output ends of control single chip computer to be sent to the 5th input end, the 6th input end, the 7th input end, the 8th input end of each high-speed analog switch in the sampling hold circuit accordingly through sequential successively, and is sent to the sequential distributing signal input end of each ADC single-chip microcomputer in the ADC single chip circuit respectively accordingly;

In the timing distribution circuit, the oscillation output end of active crystal oscillator distributes the oscillator incoming end of control single chip computer to send the crystal oscillator signal to sequential; Two output terminals of clock chip crystal oscillator send the crystal oscillator signal to second input end, the 3rd input end of clock chip respectively;

System clock is provided by clock chip; The terminals that main control singlechip includes the terminals that are connected with the exterior read-write synchronous clock input end of clock chip, the terminals that are connected with the clock data input/output terminal of clock chip, selects input end to be connected with the sheet of clock chip; The terminals that exterior read-write synchronous clock input end wherein main control singlechip and clock chip is connected are that clock chip provides the synchronous control signal that reads and writes data or order; The terminals that are connected with the clock data input/output terminal of clock chip are that clock chip provides the inputoutput data that reads and writes data or order passage, are that clock chip provides the gating control signal with the terminals that the sheet of clock chip selects input end to be connected;

(4) in the sampling hold circuit; The signal condition of the first input end of each high-speed analog switch, second input end, the 3rd input end, four-input terminal receiving step (2) and trigger pip produce the sampling of circuit input on the occasion of signal, sampling negative value signal; And according to the value of the control signal of timing distribution circuit input in the step (3); Produce accordingly on the occasion of signal, negative value signal; And will be input to the sampled signal conversion input end of ADC single-chip microcomputer respectively on the occasion of signal, negative value signal, obtain Wave data; Specific as follows:

In the sampling hold circuit; The sampling that the first input end of each high-speed analog switch, second input end, the 3rd input end, four-input terminal receiving signal reason and trigger pip produce the circuit input in second group of high-speed analog switch is on the occasion of signal, and first input end, second input end, the 3rd input end, four-input terminal receiving signal reason and the trigger pip of each high-speed analog switch produce the sampling negative value signal of circuit input in first group of high-speed analog switch; Each high-speed analog switch etc. is to be communicated with in 1 o'clock in the value of control signal in first group of high-speed analog switch; The value of control signal is disconnection in 0 o'clock; Sampling negative value signal according to signal condition and the input of trigger pip generation circuit produces the negative value signal accordingly; The sampled signal conversion input end that the negative value signal is input to ADC single-chip microcomputer etc. respectively carries out the A/D conversion, obtains the negative loop of waveform; In like manner; Each high-speed analog switch etc. is to be communicated with in 1 o'clock in the value of its control signal in second group of high-speed analog switch; The value of control signal is disconnection in 0 o'clock; The sampling that produces the circuit input according to signal condition and trigger pip produces on the occasion of signal on the occasion of signal accordingly, and the sampled signal conversion input end that is input to ADC single-chip microcomputer etc. on the occasion of signal respectively carries out the A/D conversion, obtain waveform on the occasion of part; The value of control signal is that corresponding 100P (pico farad) sampling in 1 o'clock keeps electric capacity (wherein; Sampling keep electric capacity etc. totally 16 be used for the negative value signal sampling and keep; Sampling keep electric capacity etc. totally 16 be used for keeping on the occasion of signal sampling) follow the waveform voltage value and change; The value of control signal is that 100P sampling in 0 o'clock keeps the voltage on the electric capacity stable, and the saltus step of the value of control signal since 1 to 0 (abbreviation negative edge) triggers corresponding ADC single-chip microcomputer simultaneously and carries out the A/D conversion immediately.

In the ADC single chip circuit, the ADC single-chip microcomputer be responsible for changing negative loop that the negative value signal is a waveform, on the occasion of signal be waveform on the occasion of part, wherein, active crystal oscillator sends the crystal oscillator signal to the active crystal oscillator incoming end of ADC single-chip microcomputer; The driving force of active crystal oscillator is very strong, and is safe and reliable for guaranteeing, each active crystal oscillator drives four ADC single-chip microcomputers; All ADC single-chip microcomputers begin the A/D conversion at the negative edge of the value of control signal; Sequential distributes control single chip computer can guarantee the time long enough between twice adjacent negative edge of value of same control signal, satisfies corresponding in check ADC single-chip microcomputer and accomplishes A/D conversion and other routine processes function time requirements; Two groups of each 16 ADC single-chip microcomputers are correspondence " synchronously " fully in time one by one; Between 16 ADC single-chip microcomputers in same group because of being controlled the control of signal; The time that begins to carry out the A/D conversion is the fixing phase place that clocklike staggers; I.e. " asynchronous " is convenient to the negative loop of waveform and waveform synthesized complete waveform on the occasion of part; Waveform must be 0 on the occasion of its negative value sampling of section, and it must be 0 on the occasion of sampling waveform negative value section;

(5) in the main control singlechip circuit; Signal condition and trigger pip produce negative trigger pip, the positive trigger pip that circuit sends in the main control singlechip receiving step (2); And the middle timing distribution circuit of refer step (3) produces the rule of control signal; Produce the main control singlechip control signal; And being sent to the main control singlechip signal input end of each ADC single-chip microcomputer by main control singlechip, each ADC single-chip microcomputer upgrades its sample conversion concluding time marking signal according to the main control singlechip control signal respectively, and its sample conversion concluding time marking signal is sent to first driver, second driver respectively; First driver, second driver are converted into order accordingly with sample conversion concluding time marking signal respectively and judge sequence signal; Main control singlechip sends the driver control signal to first driver, second driver, judges sequence signal so that read in order; Be specially:

The ADC single-chip microcomputer is constantly carrying out the A/D conversion always under the control of control signal; The main control singlechip control signal is the overall situation " synchronously " order that main control singlechip sends; The value of main control singlechip control signal is 1 at ordinary times; The A/D transformation result of ADC single-chip microcomputer is not preserved, in case negative trigger pip or positive trigger pip effective (negative edge is effective), then the value of main control singlechip control signal is 0; The ADC single-chip microcomputer begins to preserve the A/D transformation result, after the value of main control singlechip control signal is 1, just stops to preserve; The ADC single-chip microcomputer of the responsible waveform negative loop sampling of suspension control signal control can be exported sample conversion concluding time marking signal; The value of main control singlechip control signal is that the value of 1 o'clock sample conversion concluding time marking signal is 1; The value of main control singlechip control signal be 0 and the ADC single-chip microcomputer accomplish A/D conversion back ADC single-chip microcomputer can to export the value of sample conversion concluding time marking signal be 0; Because the value of control signal has cycline rule; Therefore the value of sample conversion concluding time marking signal is that the appearance of 0 state also has the sequencing rule; The state of these sample conversion concluding time marking signals is used to judge that its value is to accomplish the numbering of the ADC single-chip microcomputer of A/D conversion and saving result first after 0, so that read Wave data and carry out waveform synthetic.

Each ADC single-chip microcomputer all has unique address number, and they communicate by letter with main control singlechip through serial port; Main control singlechip sends order, and all ADC single-chip microcomputers all receive, but the ADC single-chip microcomputer can be made different reactions according to the address format in the order; In any moment, the ADC single-chip microcomputer has only one to allow to send, in order to avoid cause bus collision

(6) main control singlechip reads Wave data by sequence signal according to judging in proper order from the ADC single-chip microcomputer, and Wave data is synthesized complete waveform signal; Main control singlechip is sent to waveform signal in the storage chip and preserves, and is sent to the compunication serial port, and then and compunication; Simultaneously; Main control singlechip sends reseting controling signal, address selection control signal, gating control signal, read control signal, write control signal to the display interface device unit; The waveform signal that measures is shown, accomplish the measurement and the demonstration of outside thunder-strike current signal.

The utility model produces in the circuit at signal condition and trigger pip, waveform is separated with negative loop on the occasion of part, so that carry out the A/D conversion respectively; When Wave data storage and demonstration, the two is synthesized complete waveform at last; That utilizes waveform produces trigger pip on the occasion of part respectively with negative loop, so that identification triggers attribute, gathers a waveform and only triggers once; Can just be provided with and trigger, the negative triggering or the mixing trigger mode.

The sampling hold circuit of the utility model adopts time crossing parallel synchronous sampling technique; Can significantly improve the sampling rate of existing ADC; Utilize a plurality of parallel ADC single-chip microcomputers jointly same analog input signal to be carried out the A/D conversion; The sampling clock of each ADC single-chip microcomputer stagger successively a fixing phase place (360 °/N); Each ADC single-chip microcomputer is circulated to input signal with a regular time at interval successively carry out the A/D conversion, the Wave data stream of final output is to be intersected according to identical order by the data that each ADC single-chip microcomputer is exported to produce, and this has improved N doubly with regard to the sampling rate that is equivalent to ADC.

The collection (the about 300KHz of the sampling rate of its ADC) of the chip microcontroller signal waveform of the utility model utilization band low speed ADC is respectively used 16 on the occasion of part with negative loop.ADC single-chip microcomputer executive routine is preserved adc data, and identification control signal and output state etc. need the time, and therefore all the overall equivalent sampling speed of ADC is not theoretic 16 times of raising, but actual 10 times, i.e. 3MHz.Because the phase place to each ADC single-chip microcomputer requires very strict; Adopt the single-chip microcomputer STC12C5202 of 28 pin to export 16 tunnel control signals realizations " time intersection "; And symmetry control is on the occasion of each 16 ADC single-chip microcomputer of part and negative loop; Make they corresponding one by one " synchronously " in time synthesize so that realize waveform.Adopt LCD (LCD) to realize the demonstration of waveform and parameter thereof, and can with compunication, satisfy performance and cost requirement, cost performance is very high.

The utility model utilizes low speed devices to realize the high speed waveform acquisition; Such as the ADC that uses the sampling rate that carries sampling hold circuit as 100MHz; The dma controller of speeds match and RAM with it; Substitute the design's analog switch, sampling keeps electric capacity and ADC single-chip microcomputer, substitutes sequential with FPGA or DSP (speed satisfies sequential switching interval 10ns and gets final product) and distributes single-chip microcomputer; (frequency of operation gets final product greater than 10MHz with DSP; Look the refreshing frequency of gathering waveform and demonstration and decide) substitute main control singlechip or continue to use single-chip microcomputer, as long as the signal condition of front end partly can reach the reaction velocity more than the 1GHz, then total system can easily reach the equivalent sampling speed of 1GHz; If the signal condition of front end part can reach the above reaction velocity of 3GHz, only need do simple modifications, total system can reach 3GHz even higher equivalent sampling speed.Therefore for the gordian technique bottleneck that solves this DSO of sampling rate possible scheme is provided.

Low speed devices not only has cost advantage, and the wiring board topological design is much simple, helps reducing radiation, improves the stability and the reliability of system works.

Compared with prior art, the utlity model has following advantage and beneficial effect:

1, the SF of the digital storage oscilloscope of the utility model is 3MHz, all uses conventional cheap device, and cost is extremely low, performance is powerful, satisfies the specific (special) requirements of thunder-strike current waveform acquisition fully.Simultaneously the gordian technique that realizes digital storage oscilloscope is inquired into.

2, the utility model utilizes the high speed amplifier to realize the prime isolation, and the positive and negative value part of signal is separated and separate collection, utilizes common comparer identification trigger pip attribute; Use common ADC single-chip microcomputer to accomplish the A/D conversion; Carry out sequential by common single-chip microcomputer and distribute control, realize " time crossing parallel synchronized sampling ", substituted high-end devices such as FPGA in the prior art, FIFO, DMA, high-speed ADC, DSP fully; Reduce cost, improved sampling rate.

3, the utility model circuit design structure simple symmetric is prone to realize modularization, and program is succinct and control is convenient; Only need do simple modifications; Sampling rate is reached more than the 10MHz, promptly reach more than 30 times of ADC singlechip sampling rate, and the cost increase seldom.

Description of drawings

Fig. 1 is the The general frame of the utility model circuit.

Fig. 2 is the structural representation that signal condition shown in Figure 1 and trigger pip produce circuit.

Fig. 3 is the structural representation of sampling hold circuit shown in Figure 1.

Fig. 4 is the structural representation of ADC single chip circuit shown in Figure 1.

Fig. 5 is the structural representation of timing distribution circuit shown in Figure 1.

Fig. 6 is the structural representation of main control singlechip circuit shown in Figure 1.

Fig. 7 is the structural representation of compunication serial port shown in Figure 1, power circuit.

Embodiment

Below in conjunction with embodiment and accompanying drawing the utility model is described in further detail, but the embodiment of the utility model is not limited thereto.

Embodiment

Fig. 1～Fig. 7 shows the concrete structure synoptic diagram of present embodiment; As shown in Figure 1; This thunderbolt special digital storage oscilloscope; Comprise that signal condition and trigger pip produce circuit, timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit, power circuit, display interface device unit J10 and compunication serial port MX1 etc.; Said signal condition and trigger pip generation circuit, sampling hold circuit, ADC single chip circuit connect successively, and timing distribution circuit connects sampling hold circuit, ADC single chip circuit respectively; Said signal condition and trigger pip generation circuit, ADC single chip circuit, power circuit are connected with the main control singlechip circuit respectively; Compunication serial port MX1 connects the main control singlechip circuit, and external computing machine; The signal end that said signal condition and trigger pip generation circuit connect outside thunder-strike current signal input socket J1 is terminals 2; So that producing circuit, signal condition and trigger pip receive outside thunder-strike current signal SS1, terminals 1 ground connection of outside thunder-strike current signal input socket J1; Said power circuit comprises first output terminal, second output terminal and the 3rd output terminal; Its first output terminal, second output terminal, the 3rd output terminal all connect signal condition and trigger pip produces circuit, and said the 3rd output terminal connects timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit etc. respectively; Said display interface device unit J10 connects the main control singlechip circuit, and external display.

As shown in Figure 2; Said signal condition and trigger pip produce circuit and comprise impedance inverter circuit, isolation buffer circuit, half-wave rectifying circuit and main control singlechip interrupt control circuit; Said impedance inverter circuit comprises the first operational amplifier U1; The first operational amplifier U1 comprises positive source incoming end Vcc, power cathode incoming end GND, the first in-phase input end 1+, the first inverting input 1-, the first output terminal 1out, the second in-phase input end 2+, the second inverting input 2-and the second output terminal 2out; Wherein, The second in-phase input end 2+, the second inverting input 2-and three end points of the second output terminal 2out are unsettled need not use, its positive source incoming end Vcc, power cathode incoming end GND connect first output terminal (output of+9V power supply), second output terminal (output of 9V power supply) of power circuit respectively; The signal end that the first in-phase input end 1+ connects outside thunder-strike current signal input socket J1 is terminals 2, terminals 1 ground connection of outside thunder-strike current signal input socket J1; The first inverting input 1-connects the first output terminal 1out, and the first output terminal 1out connects half-wave rectifying circuit; Said half-wave rectifying circuit connects first output terminal, second output terminal of power circuit respectively;

Half-wave rectifying circuit comprises first resistance R 1, the first diode D1, the second diode D2, the 3rd resistance R 3, the 3rd operational amplifier U3, the 3rd diode D3, the 4th diode D4, second resistance R 2 and the 4th resistance R 4; Said the 3rd operational amplifier U3 comprises positive source incoming end Vcc, power cathode incoming end GND, the first in-phase input end 1+, the first inverting input 1-, the first output terminal 1out, the second in-phase input end 2+, the second inverting input 2-and the second output terminal 2out, and its positive source incoming end Vcc, power cathode incoming end GND connect first output terminal (output of+9V power supply), second output terminal (output of 9V power supply) of power circuit respectively; The positive pole of the first diode D1 connects the first inverting input 1-of the 3rd operational amplifier U3, and its negative pole connects the first output terminal 1out of the 3rd operational amplifier U3; The positive pole of the second diode D2 connects the first output terminal 1out of the 3rd operational amplifier U3, and its negative pole connects the first in-phase input end 1+ of the second operational amplifier U2 of isolation buffer circuit; One end of said first resistance R 1 connects the positive pole of the first diode D1, and the other end connects the negative pole of the second diode D2; One end of the 3rd resistance R 3 connects the first output terminal 1out of the first operational amplifier U1, and its other end connects the first inverting input 1-of the 3rd operational amplifier U3; The first in-phase input end 1+ ground connection of the 3rd operational amplifier U3, its second in-phase input end 2+ connects an end of the 4th resistance R 4, and the other end of the 4th resistance R 4 connects the first output terminal 1out of the first operational amplifier U1; The second inverting input 2-of the 3rd operational amplifier U3 connects the positive pole of the 4th diode D4, and its second output terminal 2out connects the negative pole of the 4th diode D4; The positive pole of the 3rd diode D3 connects the negative pole of the 4th diode D4, and its negative pole connects the second in-phase input end 2+ of the second operational amplifier U2 of isolation buffer circuit; One end of second resistance R 2 connects the positive pole of the 4th diode D4, and its other end connects the negative pole of the 3rd diode D3.

Said isolation buffer circuit comprises the second operational amplifier U2; The second operational amplifier U2 comprises positive source incoming end Vcc, power cathode incoming end GND, the first in-phase input end 1+, the first inverting input 1-, the first output terminal 1out, the second in-phase input end 2+, the second inverting input 2-and the second output terminal 2out; Said positive source incoming end Vcc connects first output terminal (output of+9V power supply) of power circuit, power cathode incoming end GND ground connection; The said first in-phase input end 1+ connects the negative pole of the half-wave rectifying circuit second diode D2; The first inverting input 1-connects the first output terminal 1out; The first output terminal 1out connects sampling hold circuit, main control singlechip interrupt control circuit, and the second in-phase input end 2+ connects the negative pole of half-wave rectifying circuit the 3rd diode D3; Its second inverting input 2-connects the second output terminal 2out, and the second output terminal 2out connects sampling hold circuit, main control singlechip interrupt control circuit.

The main control singlechip interrupt control circuit comprises first capacitor C 1, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, high-speed comparator U4 and the 5th resistance R 5, and said high-speed comparator U4 comprises positive source incoming end Vcc, power cathode incoming end GND, the first in-phase input end 1+, the first inverting input 1-, the first output terminal 1out, the second in-phase input end 2+, the second inverting input 2-and the second output terminal 2out; One end of the 7th resistance R 7 connects the 3rd output terminal (output of+5V power supply) of power circuit, and its other end connects the first in-phase input end 1+ of high-speed comparator U4; The first inverting input 1-of high-speed comparator U4 connects the first output terminal 1out of the isolation buffer circuit second operational amplifier U2, and the first output terminal 1out of high-speed comparator U4 connects an end of main control singlechip circuit (the terminals P3.3 of main control singlechip U48), the 6th resistance R 6 respectively; The other end of the 6th resistance R 6 connects the 3rd output terminal (output of+5V power supply) of power circuit, and the positive pole of first capacitor C 1 connects the 3rd output terminal (output of+5V power supply) of power circuit, the minus earth of first capacitor C 1; The two ends of said the 8th resistance R 8 connect the first in-phase input end 1+ of high-speed comparator U4, the power cathode incoming end GND of high-speed comparator U4 respectively; The power cathode incoming end GND ground connection of high-speed comparator U4; Its positive source incoming end Vcc connects the 3rd output terminal (output of+5V power supply) of power circuit, and the benchmark voltage signal BJ (BJ=500mV) that is produced by the 7th resistance R 7 and the 8th resistance R 8 dividing potential drops imports among the high-speed comparator U4 via the first in-phase input end 1+, the second in-phase input end 2+ of high-speed comparator U4 respectively; The second inverting input 2-of high-speed comparator U4 connects the second output terminal 2out of the isolation buffer circuit second operational amplifier U2, and the second output terminal 2out of high-speed comparator U4 connects main control singlechip circuit (the terminals P3.2 of main control singlechip U48); The positive source incoming end Vcc that one end of the 5th resistance R 5 connects high-speed comparator U4 is the 3rd output terminal (output of+5V power supply) of power circuit, and its other end connects the second output terminal 2out of high-speed comparator U4; The second in-phase input end 2+ of high-speed comparator is connected with the first in-phase input end 1+.

Signal condition and trigger pip produce circuit and also comprise second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8, the 5th diode D5, the 6th diode D6, the 7th diode D7 and the 8th diode D8; The plus earth of said the 5th diode D5, its negative pole connect the first in-phase input end 1+ of the second operational amplifier U2; The plus earth of said the 6th diode D6, its negative pole connect the second in-phase input end 2+ of the second operational amplifier U2; The minus earth of the 7th diode D7, its anodal positive pole that connects the 8th diode D8, the negative pole of the 8th diode D8 connects the first in-phase input end 1+ of the first operational amplifier U1; The positive source incoming end Vcc that the positive pole of the positive pole of said the 3rd capacitor C 3, the 4th capacitor C 4 connects the second operational amplifier U2 is first output terminal (output of+9V power supply) of power circuit; The positive source incoming end Vcc that the positive pole of the 5th capacitor C 5 connects the 3rd operational amplifier U3 is first output terminal (output of+9V power supply) of power circuit; The positive source incoming end Vcc that the positive pole of the 8th capacitor C 8 connects the first operational amplifier U1 is first output terminal (output of+9V power supply) of power circuit, and the negative pole of the 3rd capacitor C 3, the negative pole of the 4th capacitor C 4, the negative pole of the 5th capacitor C 5, the equal ground connection of negative pole of the 8th capacitor C 8; The power cathode incoming end GND that the negative pole of said second capacitor C 2 connects the first operational amplifier U1 is second output terminal (output of 9V power supply) of power circuit; The power cathode incoming end GND that the negative pole of the negative pole of the 6th capacitor C 6, the 7th capacitor C 7 all connects the 3rd operational amplifier U3 is second output terminal (output of 9V power supply) of power circuit, and anodal all ground connection of the positive pole of the positive pole of second capacitor C 2, the 6th capacitor C 6, the 7th capacitor C 7.

J1 is the input socket of outside thunder-strike current signal SS1, connects Rogowski coil (Rockwell coil) when measuring the thunder-strike current waveform usually.

The first operational amplifier U1, the second operational amplifier U2, the 3rd operational amplifier U3 are the MAX9651 operational amplifier, and parameter is: peak anode current 1.3A, the full amplitude of oscillation of input and output; Work in single supply 20V or dual power supply ± 10V, electric slew rate 40V/us, bandwidth 35MHz; Every passage quiescent current 5mA, heat radiation is good, drives 2.2 ohm; 0.1uF (microfarad) load time spent 2.0us drives 10 ohm, 100P (pico farad) the load time spent is no more than 10ns (nanosecond).

The parameter of high-speed comparator U4 (model LM393) is: work in single supply 2～36V or dual power supply ± 18V, but output line with, the about 1.3us of maximum response time during 5 kilohms of loads, low-power consumption.

As shown in Figure 3; Said sampling hold circuit comprises that first group of high-speed analog switch, second group of high-speed analog switch and 32 samplings keep electric capacity; First group of high-speed analog switch, second group of high-speed analog switch comprise four high-speed analog switchs respectively; Wherein, First group of high-speed analog switch comprises high-speed analog switch U5, high-speed analog switch U6, high-speed analog switch U7, high-speed analog switch U8, and second group of high-speed analog switch comprises high-speed analog switch U9, high-speed analog switch U10, high-speed analog switch U11, high-speed analog switch U12; And each high-speed analog switch includes positive source incoming end VCC, power cathode incoming end GND, first input end COM1, the second input end COM2, the 3rd input end COM3, four-input terminal COM4, the 5th input end IN1, the 6th input end IN2, the 7th input end IN3, the 8th input end IN4, the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04; Corresponding respectively four samplings of said each high-speed analog switch keep electric capacity; As shown in Figure 3; Sampling keeps the positive pole of capacitor C 9, the positive pole that sampling keeps capacitor C 10, positive pole, the sampling that sampling keeps capacitor C 11 to keep the positive pole of capacitor C 12 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U5 respectively, and sampling keeps the negative pole of capacitor C 9, the negative pole that sampling keeps capacitor C 10, the negative pole that sampling keeps capacitor C 11, the equal ground connection of negative pole that sampling keeps capacitor C 12; Sampling keeps the positive pole of capacitor C 13, the positive pole that sampling keeps capacitor C 14, positive pole, the sampling that sampling keeps capacitor C 15 to keep the positive pole of capacitor C 16 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U6 respectively, and sampling keeps the negative pole of capacitor C 13, the negative pole that sampling keeps capacitor C 14, the negative pole that sampling keeps capacitor C 15, the equal ground connection of negative pole that sampling keeps capacitor C 16; Sampling keeps the positive pole of capacitor C 17, the positive pole that sampling keeps capacitor C 18, positive pole, the sampling that sampling keeps capacitor C 19 to keep the positive pole of capacitor C 20 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U7 respectively, and sampling keeps the negative pole of capacitor C 17, the negative pole that sampling keeps capacitor C 18, the negative pole that sampling keeps capacitor C 19, the equal ground connection of negative pole that sampling keeps capacitor C 20; Sampling keeps the positive pole of capacitor C 21, the positive pole that sampling keeps capacitor C 22, positive pole, the sampling that sampling keeps capacitor C 23 to keep the positive pole of capacitor C 24 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U8 respectively, and sampling keeps the negative pole of capacitor C 21, the negative pole that sampling keeps capacitor C 22, the negative pole that sampling keeps capacitor C 23, the equal ground connection of negative pole that sampling keeps capacitor C 24; Sampling keeps the positive pole of capacitor C 25, the positive pole that sampling keeps capacitor C 26, positive pole, the sampling that sampling keeps capacitor C 27 to keep the positive pole of capacitor C 28 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U9 respectively, and sampling keeps the negative pole of capacitor C 25, the negative pole that sampling keeps capacitor C 26, the negative pole that sampling keeps capacitor C 27, the equal ground connection of negative pole that sampling keeps capacitor C 28; Sampling keeps the positive pole of capacitor C 29, the positive pole that sampling keeps capacitor C 30, positive pole, the sampling that sampling keeps capacitor C 31 to keep the positive pole of capacitor C 32 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U10 respectively, and sampling keeps the negative pole of capacitor C 29, the negative pole that sampling keeps capacitor C 30, the negative pole that sampling keeps capacitor C 31, the equal ground connection of negative pole that sampling keeps capacitor C 32; Sampling keeps the positive pole of capacitor C 33, the positive pole that sampling keeps capacitor C 34, positive pole, the sampling that sampling keeps capacitor C 35 to keep the positive pole of capacitor C 36 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U11 respectively, and sampling keeps the negative pole of capacitor C 33, the negative pole that sampling keeps capacitor C 34, the negative pole that sampling keeps capacitor C 35, the equal ground connection of negative pole that sampling keeps capacitor C 36; Sampling keeps the positive pole of capacitor C 37, the positive pole that sampling keeps capacitor C 38, positive pole, the sampling that sampling keeps capacitor C 39 to keep the positive pole of capacitor C 40 to receive the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of high-speed analog switch U12 respectively, and sampling keeps the negative pole of capacitor C 37, the negative pole that sampling keeps capacitor C 38, the negative pole that sampling keeps capacitor C 39, the equal ground connection of negative pole that sampling keeps capacitor C 40.

The positive source incoming end VCC of said high-speed analog switch U5, high-speed analog switch U6, high-speed analog switch U7, high-speed analog switch U8, high-speed analog switch U9, high-speed analog switch U10, high-speed analog switch U11, high-speed analog switch U12 also is connected with power filtering capacitor C41, power filtering capacitor C42, power filtering capacitor C43, power filtering capacitor C44, power filtering capacitor C45, power filtering capacitor C46, power filtering capacitor C47, power filtering capacitor C48 respectively, and the other end of power filtering capacitor C41, power filtering capacitor C42, power filtering capacitor C43, power filtering capacitor C44, power filtering capacitor C45, power filtering capacitor C46, power filtering capacitor C47, power filtering capacitor C48 is ground connection respectively.Wherein, Power filtering capacitor C41 is the power filtering capacitor of high-speed analog switch U5; Power filtering capacitor C42 is the power filtering capacitor of high-speed analog switch U6; Power filtering capacitor C43 is the power filtering capacitor of high-speed analog switch U7, and power filtering capacitor C44 is the power filtering capacitor of high-speed analog switch U8, and power filtering capacitor C45 is the power filtering capacitor of high-speed analog switch U9; Power filtering capacitor C46 is the power filtering capacitor of high-speed analog switch U10; Power filtering capacitor C47 is the power filtering capacitor of high-speed analog switch U11, and power filtering capacitor C48 is the power filtering capacitor of high-speed analog switch U12, is connected across respectively between the positive source incoming end VCC and power cathode incoming end GND of corresponding high-speed analog switch separately.The positive source incoming end VCC of each high-speed analog switch all connects the 3rd output terminal (output of+5V power supply) of power circuit, the equal ground connection of power cathode incoming end GND of each high-speed analog switch.

The first output terminal N01 of each high-speed analog switch, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 all are connected in the ADC single chip circuit (the sampled signal conversion input end A17 of ADC single-chip microcomputer) accordingly;

In first group of high-speed analog switch, the first input end COM1 of each high-speed analog switch, the second input end COM2, the 3rd input end COM3, four-input terminal COM4 all connect the first output terminal 1out of the second operational amplifier U2; In second group of high-speed analog switch, the first input end COM1 of each high-speed analog switch, the second input end COM2, the 3rd input end COM3, four-input terminal COM4 all connect the second output terminal 2out of the second operational amplifier U2;

The 5th input end IN1 of each high-speed analog switch, the 6th input end IN2, the 7th input end IN3, the 8th input end IN4 connect the control signal output ends of timing distribution circuit respectively.

As shown in Figure 5, said timing distribution circuit comprises sequential distribution control single chip computer U45, active crystal oscillator J11, clock chip U46, clock chip crystal oscillator Y1 and battery BT1; Said sequential distributes control single chip computer U45 to comprise control signal output ends, oscillator incoming end XTAL1, positive source incoming end VCC, power cathode incoming end GND, terminals RST/VPP, terminals (RXD) P3.0, terminals (TXD) P3.1, terminals XTAL2, terminals (INT0) P3.2, terminals (INT1) P3.3, terminals (T0) P3.4, terminals (T1) P3.5 and terminals P3.7/PWM0; Wherein, said terminals RST/VPP, terminals (RXD) P3.0, terminals (TXD) P3.1, terminals XTAL2, terminals (INT0) P3.2, terminals (INT1) P3.3, terminals (T0) P3.4, terminals (T1) P3.5, terminals P3.7/PWM0 do not use in this circuit; Said positive source incoming end VCC connects the 3rd output terminal (output of+5V power supply) of power circuit, its power cathode incoming end GND ground connection; It is 16 that said sequential is distributed the control signal output ends of control single chip computer U45; Be respectively control signal output ends P1.0/ADC0, control signal output ends P1.1/ADC1, control signal output ends P1.2/ADC2, control signal output ends P1.3/ADC3, control signal output ends P1.4/ADC4, control signal output ends P1.5/ADC5, control signal output ends P1.6/ADC6, control signal output ends P1.7/ADC7, control signal output ends P2.0, control signal output ends P2.1, control signal output ends P2.2, control signal output ends P2.3, control signal output ends P2.4, control signal output ends P2.5, control signal output ends P2.6 and control signal output ends P2.7, each control signal output ends is connected to the 5th input end IN1, the 6th input end IN2, the 7th input end IN3, the 8th input end IN4 of each high-speed analog switch of every group of high-speed analog switch respectively accordingly; And each control signal output ends also connects the ADC single chip circuit respectively.Wherein, control signal output ends P1.0/ADC0 is connected on the 5th input end IN1 of the 5th input end IN1, high-speed analog switch U9 of high-speed analog switch U5; Control signal output ends P1.1/ADC1 is connected on the 6th input end IN2 of the 6th input end IN2, high-speed analog switch U9 of high-speed analog switch U5; Control signal output ends P1.2/ADC2 is connected on the 7th input end IN3 of the 7th input end IN3, high-speed analog switch U9 of high-speed analog switch U5; Control signal output ends P1.3/ADC3 is connected on the 8th input end IN4 of the 8th input end IN4, high-speed analog switch U9 of high-speed analog switch U5; Control signal output ends P1.4/ADC4 is connected on the 5th input end IN1 of the 5th input end IN1, high-speed analog switch U10 of high-speed analog switch U6; Control signal output ends P1.5/ADC5 is connected on the 6th input end IN2 of the 6th input end IN2, high-speed analog switch U10 of high-speed analog switch U6; Control signal output ends P1.6/ADC6 is connected on the 7th input end IN3 of the 7th input end IN3, high-speed analog switch U10 of high-speed analog switch U6; Control signal output ends P1.7/ADC7 is connected on the 8th input end IN4 of the 8th input end IN4, high-speed analog switch U10 of high-speed analog switch U6; Control signal output ends P2.0 is connected on the 5th input end IN1 of the 5th input end IN1, high-speed analog switch U11 of high-speed analog switch U7; Control signal output ends P2.1 is connected on the 6th input end IN2 of the 6th input end IN2, high-speed analog switch U11 of high-speed analog switch U7; Control signal output ends P2.2 is connected on the 7th input end IN3 of the 7th input end IN3, high-speed analog switch U11 of high-speed analog switch U7; Control signal output ends P2.3 is connected on the 8th input end IN4 of the 8th input end IN4, high-speed analog switch U11 of high-speed analog switch U7; Control signal output ends P2.4 is connected on the 5th input end IN1 of the 5th input end IN1, high-speed analog switch U12 of high-speed analog switch U8; Control signal output ends P2.5 is connected on the 6th input end IN2 of the 6th input end IN2, high-speed analog switch U12 of high-speed analog switch U8; Control signal output ends P2.6 is connected on the 7th input end IN3 of the 7th input end IN3, high-speed analog switch U12 of high-speed analog switch U8; Control signal output ends P2.7 is connected on the 8th input end IN4 of the 8th input end IN4, high-speed analog switch U12 of high-speed analog switch U8.

Active crystal oscillator J11 comprises positive source input end 4, power cathode input end 2, oscillation output end 3 and unsettled input end 1; The oscillation output end 3 of active crystal oscillator J11 connects the oscillator incoming end XTAL1 that said sequential is distributed control single chip computer U45; Its positive source input end 4 connects the 3rd output terminal (output of+5V power supply) of power circuit; Its power cathode input end 2 ground connection, its unsettled input end 1 is unsettled need not.

Said clock chip U46 comprises that first input end VCC2, the second input end X1, the 3rd input end X2, four-input terminal GND, the 5th input end VCC1, exterior read-write synchronous clock input end (input clock signal SCLK), clock data input/output terminal IO (inputing or outputing data-signal I/O) and sheet select input end (input chip selection signal CE); Said first input end VCC2 connects the 3rd output terminal (output of+5V power supply) of power circuit, and the said second input end X1, the 3rd input end X2 connect two output terminals of clock chip crystal oscillator Y1 respectively; Said four-input terminal GND ground connection, said the 5th input end VCC1 connects the positive pole of battery BT1, the minus earth of battery BT1; Said exterior read-write synchronous clock input end (input clock signal SCLK), clock data input/output terminal IO and sheet select input end (input chip selection signal CE) to be connected with resistance R 12, resistance R 13, resistance R 14 respectively; The other end of said resistance R 12, resistance R 13, resistance R 14 all is connected to the 3rd output terminal of power circuit (output of+5V power supply), plays the effect of drawing on the level; Said exterior read-write synchronous clock input end (input clock signal SCLK), clock data input/output terminal IO and sheet select input end (input chip selection signal CE) also to be connected respectively among the main control singlechip U48.

Said timing distribution circuit also comprises capacitor C 81, capacitor C 82 and capacitor C 83; The positive pole of the positive pole of the positive pole of capacitor C 81, capacitor C 82, capacitor C 83 connects sequential respectively and distributes the positive source incoming end VCC of control single chip computer U45, the first input end VCC2 of clock chip U46, the positive source input end 4 of active crystal oscillator J11; The equal ground connection of negative pole is respectively three devices and carries out power filter.

As shown in Figure 5; Display interface device unit J10 is the LCD display interface unit, comprises input end BL2, input end BL1, output terminal VEE, input end NC, input end VO (the negative power signal Voo through input regulates display brightness), input end VDD, input end VSS, input/output terminal D0～input/output terminal D7, reseting controling signal input end (input reseting controling signal RST), address selection signal input end (INADD is selected control signal A0), gating signal input end CS (input gating control signal CSS), read control signal input end (input read control signal RD) and write control signal input end (input write control signal WR); The input end BL1 of display interface device unit J10 (backlight electric power of LCD display is anodal) and input end VDD (positive source of LCD display) all are connected to the 3rd output terminal (output of+5V power supply) of power circuit; Input end BL2 (the backlight electric power negative pole of LCD display) and input end VSS (power cathode of LCD display) be ground connection all; Input end VO (the brightness regulation end of LCD display) connects the convertible tip of variable resistor R9; Output terminal VEE (negative supply of LCD display produces end) connects the fixed endpoint of variable resistor R9; Another fixed endpoint ground connection of variable resistor R9; The input end NC of display interface device unit J10 unsettled need not, all the other control signals of display interface device unit J10 all are connected the main control singlechip circuit with input/output terminal.The positive pole of capacitor C 84 connects the input end BL1 of LCD display interface unit J10, and minus earth carries out power filter.

As shown in Figure 4, the ADC single chip circuit comprises 32 ADC single-chip microcomputers and the active crystal oscillator of several ADC single-chip microcomputers; 32 ADC single-chip microcomputers are respectively the U13～U44 among the figure; Each ADC single-chip microcomputer has included terminals RST, serial line interface input end RP30, serial line interface output terminal TP31, terminals XT2, active crystal oscillator input end XT1, sequential distributing signal input end A33 (A33), terminals A34, power cathode input end GND, positive source input end VCC, sampled signal conversion input end A17, terminals A16, sample conversion concluding time marking signal output terminals A 15, terminals A12, terminals A11, main control singlechip signal input end A10 and terminals A37; Wherein, terminals RST, terminals XT2, terminals A34, terminals A16, terminals A12, terminals A11, terminals A37 are all unsettled in this circuit does not use; The positive source input end VCC of said ADC single-chip microcomputer all connects the 3rd output terminal (output of+5V power supply) of power circuit, the equal ground connection of its power cathode input end GND; The sampled signal conversion input end A17 of each ADC single-chip microcomputer connects the first output terminal N01, the second output terminal N02, the 3rd output terminal N03, the 4th output terminal N04 of each high-speed analog switch of sampling hold circuit respectively; The sequential distributing signal input end P33 of each ADC single-chip microcomputer is connected to the control signal output ends P1.0/ADC0 of timing distribution circuit respectively accordingly; Control signal output ends P1.1/ADC1; Control signal output ends P1.2/ADC2; Control signal output ends P1.3/ADC3; Control signal output ends P1.4/ADC4; Control signal output ends P1.5/ADC5; Control signal output ends P1.6/ADC6; Control signal output ends P1.7/ADC7; Control signal output ends P2.0; Control signal output ends P2.1; Control signal output ends P2.2; Control signal output ends P2.3; Control signal output ends P2.4; Control signal output ends P2.5; Control signal output ends P2.6 and control signal output ends P2.7; The sample conversion concluding time marking signal output terminals A 15 of each ADC single-chip microcomputer, main control singlechip signal input end A10, serial line interface input end RP30, serial line interface output terminal TP31 connect the main control singlechip circuit through sample conversion concluding time marking signal Wi, main control singlechip control signal PD, serial port signal TXD, serial port signal RXD respectively; The active crystal oscillator input end XT1 of each ADC single-chip microcomputer all connects the active crystal oscillator of ADC single-chip microcomputer, is respectively the active crystal oscillator J2 of ADC single-chip microcomputer, the active crystal oscillator J3 of ADC single-chip microcomputer, the active crystal oscillator J4 of ADC single-chip microcomputer, the active crystal oscillator J5 of ADC single-chip microcomputer, the active crystal oscillator J6 of ADC single-chip microcomputer, the active crystal oscillator J7 of ADC single-chip microcomputer, the active crystal oscillator J8 of ADC single-chip microcomputer, the active crystal oscillator J9 of ADC single-chip microcomputer; The active crystal oscillator of each ADC single-chip microcomputer includes positive source input end 4, power cathode input end 2, oscillation output end 3 and unsettled input end 1; Its positive source input end 4 all connects the 3rd output terminal of power circuit; Its power cathode input end 2 equal ground connection; Its oscillation output end 3 connects the active crystal oscillator input end of corresponding ADC single-chip microcomputer, its unsettled input end 1 is all unsettled need not; Wherein, The oscillation output end 3 of the active crystal oscillator J2 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U13～U16; The oscillation output end 3 of the active crystal oscillator J3 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U17～U20; The oscillation output end 3 of the active crystal oscillator J4 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U21～U24; The oscillation output end 3 of the active crystal oscillator J5 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U25～U28; The oscillation output end 3 of the active crystal oscillator J6 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U29～U32; The oscillation output end 3 of the active crystal oscillator J7 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U33～U36; The oscillation output end 3 of the active crystal oscillator J8 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U37～U40, and the oscillation output end 3 of the active crystal oscillator J9 of ADC single-chip microcomputer connects the active crystal oscillator input end XT1 of ADC single-chip microcomputer U41～U44.

The ADC single chip circuit also includes 32 power filtering capacitors; Be respectively power filtering capacitor C49～power filtering capacitor C80; Connect one to one the respectively positive source input end VCC of ADC single-chip microcomputer U13～U44 of the positive pole of power filtering capacitor C49～power filtering capacitor C80; Connect one to one the respectively power cathode input end GND of ADC single-chip microcomputer U13～U44 of the negative pole of power filtering capacitor C49～power filtering capacitor C80 is for they provide power filter.

Active crystal oscillator J2～active crystal oscillator J9 includes positive source input end, power cathode input end, oscillation output end and unsettled input end; The said ADC single-chip microcomputer of the corresponding respectively connection of the oscillation output end 3 of said active crystal oscillator J2～active crystal oscillator J9; Its positive source input end 4 all connects the 3rd output terminal (output of+5V power supply) of power circuit; Its power cathode input end 2 equal ground connection, its unsettled input end 1 is all unsettled need not.

As shown in Figure 6, the main control singlechip circuit comprises main control singlechip U48, the active crystal oscillator J13 of 25MHz main control singlechip, the first driver U47, the second driver U49, storage chip U50, capacitor C 85, capacitor C 86, capacitor C 87, capacitor C 88, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, resistance R 22, button KSW1, button KSW2, button KSW3, button KSW4, button KSW5, button KSW6, button KSW7 and button KSW8.Main control singlechip U48 comprises terminals P0.0; Terminals P0.1; Terminals P0.2; Terminals P0.3; Terminals P0.4; Terminals P0.5; Terminals P0.6; Terminals P0.7; Terminals P2.0; Terminals P2.1; Terminals P2.2; Terminals P2.3; Terminals P2.4; Terminals P2.5; Terminals P2.6; Terminals P2.7; Terminals P1.0; Terminals P1.1; Terminals P1.2 (unsettled need not); Terminals P1.3 (unsettled need not); Terminals P1.4; Terminals P1.5; Terminals P1.6; Terminals P1.7; Terminals P3.0 (being used to receive serial port signal RXD1); Terminals P3.1 (being used to receive serial port signal TXD1); Terminals P3.2; Terminals P3.3; Terminals P3.4 (unsettled need not); Terminals P3.5 (unsettled need not); Terminals P3.6; Terminals P3.7; Terminals P4.0; Terminals P4.1; Terminals P4.2; Terminals P4.3; Terminals P4.4; Terminals P4.5; Terminals P4.6; Terminals P4.7; Oscillator incoming end XTAL1; Oscillator incoming end XTAL2 (unsettled need not); Positive source incoming end VCC and power cathode incoming end GND.Terminals Q1～terminals Q8 of the first driver U47 connects terminals P0.0～terminals P0.7 of main control singlechip U48 respectively; Terminals D1～terminals D8 of the first driver U47 connects the sample conversion concluding time marking signal output terminal P15 of each ADC single-chip microcomputer of U13～U20 in the ADC single chip circuit respectively; The terminals OC of the first driver U47 connects the terminals P1.4 of main control singlechip U48; The terminals VCC of the terminals G of the first driver U47, the first driver U47 all connects the 3rd output terminal (output of+5V power supply) of power circuit, the terminals GND ground connection of the first driver U47; Terminals Q1～terminals Q8 of the second driver U49 connects terminals P2.0～terminals P2.7 of main control singlechip U48 respectively; Terminals D1～terminals D8 of the second driver U49 connects the sample conversion concluding time marking signal output terminal P15 of each ADC single-chip microcomputer of U21～U28 in the ADC single chip circuit respectively; The terminals OC of the second driver U49 connects the terminals P1.4 of main control singlechip U48; The terminals VCC of the terminals G of the second driver U49, the second driver U49 all connects the 3rd output terminal (output of+5V power supply) of power circuit, the terminals GND ground connection of the second driver U49.

The 8th terminals Vcc of storage chip U50 connects the 3rd output terminal (output of+5V power supply) of power circuit; The 7th terminals WP of storage chip U50, the first terminals NC1, the second terminals A1, the 3rd terminals NC2, the equal ground connection of the 4th terminals GND; The 6th terminals of storage chip U50 (receiving serial line interface signal SCL) connect an end of resistance R 10 and the terminals P4.4 of main control singlechip U48; The 5th terminals of storage chip U50 (receiving serial line interface signal SDA) connect an end of resistance R 11 and the terminals P4.5 of main control singlechip U48; The other end of resistance R 10, resistance R 11 all connects the 3rd output terminal (output of+5V power supply) of power circuit, plays the effect of drawing on the level.

The power cathode input end of the active crystal oscillator J13 of main control singlechip is terminals 2 ground connection; Oscillation output end is the oscillator incoming end XTAL1 that terminals 3 connect main control singlechip U48; The positive source input end is the 3rd output terminal (output of+5V power supply) that terminals 4 connect power circuits, and unsettled input end is that terminals 1 are unsettled need not.The positive pole of capacitor C 85, capacitor C 86, capacitor C 87, capacitor C 88 connects the positive source incoming end VCC of main control singlechip U48, the terminals VCC of the first driver U47, the terminals VCC of the second driver U49, the terminals Vcc of storage chip U50 respectively; The negative pole of the negative pole of the negative pole of the negative pole of capacitor C 85, capacitor C 86, capacitor C 87, capacitor C 88 connects the power cathode incoming end GND of main control singlechip U48, the terminals GND of the first driver U47, the terminals GND of the second driver U49, the terminals GND of storage chip U50 respectively, for they provide power filter; Resistance R 15, resistance R 17, resistance R 19, resistance R 21 are connected successively; The other end of resistance R 21 is connected to the terminals 4 (connecting through signal K0X) of button KSW8; The other end of resistance R 15 is connected to the 3rd output terminal (output of+5V power supply) of power circuit; Resistance R 16, resistance R 18, resistance R 20, resistance R 22 are connected successively; The other end of resistance R 22 is connected to the terminals 4 (connecting through signal K4X) of button KSW4, and the other end of resistance R 16 is connected to the 3rd output terminal (output of+5V power supply) of power circuit; Outconnector and be connected to the terminals 4 (K3X is connected through signal) of button KSW5 between resistance R 15 and the resistance R 17; Outconnector and be connected to the terminals 4 (K2X is connected through signal) of button KSW6 between resistance R 17 and the resistance R 19; Outconnector and be connected to the terminals 4 (K1X is connected through signal) of button KSW7 between resistance R 19 and the resistance R 21; Outconnector and be connected to the terminals 4 (K7X is connected through signal) of button KSW1 between resistance R 16 and the resistance R 18; Outconnector and be connected to the terminals 4 (K5X is connected through signal) of button KSW3 between the outconnector and be connected to the terminals 4 (K6X is connected through signal) of button KSW2 between resistance R 18 and the resistance R 20, resistance R 20 and resistance R 22; The terminals 1 of said button KSW1～button KSW8 are connected on the terminals 4 of oneself respectively separately, and its terminals 2 are connected on oneself the terminals 3 and ground connection respectively separately.

Terminals P0.0～terminals P0.7 of main control singlechip U48; Terminals P3.6; Terminals P3.7; Terminals P4.1; Terminals P4.6; Terminals P4.7 is connected respectively to input/output terminal D0～input/output terminal D7 of LCD display interface unit J10; Write control signal input end (input write control signal WR); Read control signal input end (input read control signal RD); Gating signal input end CS; Address selection signal input end (INADD is selected control signal A0); Reseting controling signal input end (input reseting controling signal RST).Wherein, Input/output terminal D0～input/output terminal D7 of LCD display interface unit J10 is the data bus of main control singlechip U48 read-write LCD display data message; The data message of LCD display comprises video data, the status information data of order data and LCD display etc.; The write control signal WR of LCD display interface unit J10 is the write control signal from the terminals P3.6 of main control singlechip U48; The read control signal RD of LCD display interface unit J10 is the read control signal from the terminals P3.7 of main control singlechip U48; The gating signal input end CS of LCD display interface unit J10 is the gating control signal from the terminals P4.1 of main control singlechip U48; The address selection control signal A0 of LCD display interface unit J10 is the address selection control signal from the terminals P4.6 of main control singlechip U48; The reseting controling signal RST of LCD display interface unit J10 is the reseting controling signal from the terminals P4.7 of main control singlechip U48.

RS232 modular connection P1 as shown in Figure 7, that this thunderbolt special digital storage oscilloscope also comprises capacitor C 89, capacitor C 90, capacitor C 92, capacitor C 96, capacitor C 97, compunication serial port MX1 and communicates by letter with outer computer.The terminals T2in of compunication serial port MX1 is connected to the terminals P4.3 of main control singlechip U48; The terminals T2out of compunication serial port MX1 is connected to first terminals of modular connection P1 through rs 232 serial interface signal RXD3; The terminals R2out of compunication serial port MX1 is connected to the terminals P4.2 of main control singlechip U48 through rs 232 serial interface signal RXD2, and the terminals R2in of compunication serial port MX1 connects second terminals of modular connection P1 through rs 232 serial interface signal TXD3; The 3rd terminals ground connection of modular connection P1, all the other 6 terminals are all unsettled need not; One end of capacitor C 90 is connected to the 3rd output terminal (output of+5V power supply) of power circuit and the terminals Vcc of compunication serial port MX1, and its other end is connected to terminals GND and the ground connection of compunication serial port MX1; The positive pole of capacitor C 89 is connected to the terminals C1+ of compunication serial port MX1, and its negative pole is connected to the terminals C1-of compunication serial port MX1; The positive pole of capacitor C 96 is connected to the terminals C2+ of compunication serial port MX1, and its negative pole is connected to the terminals C2-of compunication serial port MX1; Capacitor C 92 is connected in series with capacitor C 97; The positive pole of capacitor C 92 is connected to the terminals Vs+ of compunication serial port MX1, and the negative pole of capacitor C 97 is connected to the terminals Vs-of compunication serial port MX1.4 terminals T1out of all the other of compunication serial port MX1, terminals R1in, terminals R1out and terminals T1in is all unsettled need not.

Power circuit comprises three terminal regulator U51, capacitor C 91, capacitor C 93, capacitor C 94, capacitor C 95, three terminal regulator U52, capacitor C 99, capacitor C 100, capacitor C 101, capacitor C 98, pilot hole J14, pilot hole J15, pilot hole J17, pilot hole J18, external power source input socket J16, capacitor C 102, capacitor C 103, capacitor C 104, external power source input socket J19, power switch button KSW9, outside 220V AC in connector J20.Capacitor C 91 is parallelly connected with capacitor C 93, and capacitor C 91 is connected the terminals VOUT of three terminal regulator U51 with the negative pole common port of capacitor C 93, and capacitor C 91 is connected terminals GND and the ground connection of three terminal regulator U51 with the anodal common port of capacitor C 93; Capacitor C 94 is parallelly connected with capacitor C 95, and capacitor C 94 is connected the terminals VIN of three terminal regulator U51 with the negative pole common port of capacitor C 95, and capacitor C 94 is connected terminals GND and the ground connection of three terminal regulator U51 with the anodal common port of capacitor C 95; The terminals VOUT of three terminal regulator U51 is second output terminal (output of 9V power supply) of said power circuit; The terminals VIN of three terminal regulator U51 connects the negative input 3 (input of 12V power supply) of external power source input socket J16, the terminals GND ground connection of three terminal regulator U51; Capacitor C 99 is parallelly connected with capacitor C 100, and capacitor C 99 is connected the terminals VOUT of three terminal regulator U52 with the anodal common port of capacitor C 100, and capacitor C 99 is connected terminals GND and the ground connection of three terminal regulator U52 with the negative pole common port of capacitor C 100; Capacitor C 101 is parallelly connected with capacitor C 98, and capacitor C 101 is connected the terminals VIN of three terminal regulator U52 with the anodal common port of capacitor C 98, and capacitor C 101 is connected terminals GND and the ground connection of three terminal regulator U52 with the negative pole common port of capacitor C 98; The terminals VOUT of three terminal regulator U52 is first output terminal (output of+9V power supply) of said power circuit; The terminals VIN of three terminal regulator U52 connects the electrode input end 5 (input of+12V power supply) of external power source input socket J16, the terminals GND ground connection of three terminal regulator U52; Pilot hole J14, pilot hole J15, pilot hole J17 and pilot hole J18 are convenient to installing and locating as punching in the circuit board, are not connected with any device; The terminals 1 of external power source input socket J16 connect the terminals 1 of external power source input socket J19 through signal A; The terminals 2 of external power source input socket J16 connect the terminals 2 of external power source input socket J19 through signal N; The terminals 3 of external power source input socket J16 connect the terminals VIN of three terminal regulator U51; Terminals 4 ground connection of external power source input socket J16, the terminals 5 of external power source input socket J16 connect the terminals VIN of three terminal regulator U52; Capacitor C 102, capacitor C 103, capacitor C 104 parallel connections; And the negative pole common port of capacitor C 102, capacitor C 103, capacitor C 104 is connected to terminals 3 and the ground connection of external power source input socket J19; The anodal common port of capacitor C 102, capacitor C 103, capacitor C 104 is connected to the terminals 4 of external power source input socket J19, and the terminals 4 of external power source input socket J19 are the 3rd output terminal (output of+5V power supply) of said power circuit; The terminals 1 of outside 220V AC in connector J20 are connected to the terminals 4 of power switch button KSW9 through signal L, and the terminals 2 of outside 220V AC in connector J20 are connected to the terminals 2 of external power source input socket J19 through signal N; The terminals 1 of power switch button KSW9 are connected to its terminals 4, and its terminals 2 are connected to its terminals 3, and its terminals 3 are connected to the terminals 1 of external power source input socket J19.

The thunderbolt special digital storage oscilloscope measuring process that is realized by above-mentioned thunderbolt special digital storage oscilloscope may further comprise the steps:

(1) as shown in Figure 1; Power circuit insert outside+5V ,+12V ,-the power supply input of 12V; And be translated into+5V ,+9V ,-9V; Be respectively signal condition and trigger pip produce circuit and provide+9V ,-9V ,+input of 5V power supply, provide+the power supply input of 5V for timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit etc. simultaneously.

(2) as depicted in figs. 1 and 2; Signal condition and trigger pip produce circuit and receive outside thunder-strike current signal SS1, it is cushioned conditioning handle, and sampling negative value signal VF, the sampling that processing obtains is sent in the sampling hold circuit on the occasion of signal VZ; Simultaneously; Produce negative trigger pip UTF, positive trigger pip UTZ, negative trigger pip UTF, positive trigger pip UTZ are sent to the main control singlechip circuit, and be specific as follows:

Signal condition and trigger pip produce in the circuit; The signal end of outside thunder-strike current signal input socket J1 is that terminals 2 are imported outside thunder-strike current signal SS1 to the first in-phase input end 1+ of the first operational amplifier U1; Terminals 1 ground connection of outside thunder-strike current signal input socket J1; Outside thunder-strike current signal SS1 realizes impedance conversion through the first operational amplifier U1; Isolated the influence of late-class circuit, and produced voltage follow signal SS2, by the first output terminal 1out output of the first operational amplifier U1 signal input part; This voltage follow signal SS2 also carries out strong feedback processing by the first inverting input 1-input of the first operational amplifier U1 simultaneously, and signal stabilization is followed; Voltage follow signal SS2 is as the input signal of the 3rd operational amplifier U3; And get among the first inverting input 1-, the second in-phase input end 2+ of the 3rd operational amplifier U3 through the 3rd resistance R 3, the 4th resistance R 4 respectively; Voltage follow signal SS2 is carried out half-wave rectification by the 3rd operational amplifier U3 and is divided into two-way output; Wherein one tunnel isolation waveform is on the occasion of part; Only allow negative loop to pass through and anti-phase generation waveform negative value signal VVF, waveform negative value signal VVF is exported by the first output terminal 1out of the 3rd operational amplifier U3, and imports the first in-phase input end 1+ of the second operational amplifier U2 through the first diode D1, the second diode D2, first resistance R 1; Another road isolation waveform negative loop; Only allow on the occasion of part through producing waveform on the occasion of signal VVZ; Waveform is exported by the second output terminal 2out of the 3rd operational amplifier U3 on the occasion of signal VVZ, and imports the second in-phase input end 2+ of the second operational amplifier U2 through the 3rd diode D3, the 4th diode D4, first resistance R 2; Since waveform negative value signal VVF and waveform on the occasion of the driving force of signal VVZ very a little less than; So utilize the second operational amplifier U2 that waveform negative value signal VVF, waveform are carried out isolation buffer on the occasion of signal VVZ once more; Produce sampling negative value signal VF and sampling on the occasion of signal VZ, be input in the sampling hold circuit respectively and be input to respectively among the first inverting input 1-, the second inverting input 2-of high-speed comparator U4 by the first output terminal 1out, the second output terminal 2out of the second operational amplifier U2; VF is very strong on the occasion of the driving force of signal VZ with sampling for sampling negative value signal, moment output current can reach 1.3A, satisfy late-class circuit fully and drive needs, be used for the A/D conversion; Waveform negative value signal VVF, waveform respectively have a 5.2V amplitude limit stabilivolt (the 5th diode D5 and the 6th diode D6) on the occasion of signal VVZ end; Guarantee that sampling negative value signal VF is no more than 5.5V with sampling on the occasion of the magnitude of voltage of signal VZ; For guaranteeing safety, outside thunder-strike current signal SS1 also is limited in by the stabilivolt of two differential concatenations (the 7th diode D7 and the 8th diode D8) ± 6.8V in; Sampling negative value signal VF also produces negative trigger pip UTF and positive trigger pip UTZ (benchmark voltage BJ=500mV) respectively through high-speed comparator U4 with sampling on the occasion of signal VZ; Negative trigger pip UTF and positive trigger pip UTZ are sent to the main control singlechip circuit respectively; The trigger pip (interruption input signal) that is used for main control singlechip U48 (STC12C5A32S2) starts the ADC single chip circuit and identification is the triggering that negative pulse or positive pulse cause.

(3) like Fig. 1 and shown in Figure 5; Timing distribution circuit produces control signal K1～K16 according to certain rule circulation; And, be sent to accordingly among the sequential distributing signal input end P33 of each ADC single-chip microcomputer in the ADC single chip circuit simultaneously the 5th input end IN1, the 6th input end IN2, the 7th input end IN3, the 8th input end IN4 that control signal K1～K16 is sent to each high-speed analog switch in the sampling hold circuit accordingly; Specific as follows:

Sequential in the timing distribution circuit distributes control single chip computer U45 according to [K1=0, K5=1], [K2=0, K6=1], [K3=0; K7=1] ... [K15=0, K3=1], [K16=0, K4=1], [K1=0; K5=1] rule circulation (0 expression low level wherein; 1 expression high level, down together), produce control signal K1～K16; Control signal K1～K16 distributes control signal output ends P1.0/ADC0, control signal output ends P1.1/ADC1, control signal output ends P1.2/ADC2, control signal output ends P1.3/ADC3, control signal output ends P1.4/ADC4, control signal output ends P1.5/ADC5, control signal output ends P1.6/ADC6, control signal output ends P1.7/ADC7, control signal output ends P2.0, control signal output ends P2.1, control signal output ends P2.2, control signal output ends P2.3, control signal output ends P2.4, control signal output ends P2.5, control signal output ends P2.6 and the control signal output ends P2.7 of control single chip computer U45 to be sent to the 5th input end IN1, the 6th input end IN2, the 7th input end IN3, the 8th input end IN4 of each high-speed analog switch in the sampling hold circuit accordingly through sequential successively, and is sent to accordingly among the sequential distributing signal input end P33 of each ADC single-chip microcomputer in the ADC single chip circuit.

In the timing distribution circuit, the oscillation output end 3 of active crystal oscillator J11 distributes the oscillator incoming end XTAL1 of control single chip computer U45 to send crystal oscillator signal XYY to sequential; Two output terminals of clock chip crystal oscillator Y1 send crystal oscillator signal XW1, the second input end X1 from crystal oscillator signal XW2 to clock chip U46, the 3rd input end X2 respectively.

System clock is provided by clock chip U46; Exterior read-write synchronous clock input end (input clock signal SCLK), clock data input/output terminal IO, sheet that the terminals P1.7 of main control singlechip U48, terminals P1.6, terminals P1.5 connect clock chip U46 respectively select input end (input chip selection signal CE); Wherein the terminals P1.7 of main control singlechip U48 provides the synchronous control signal that reads and writes data or order for clock chip U46; The terminals P1.5 of main control singlechip U48 provides the gating control signal for clock chip U46, and the terminals P1.6 of main control singlechip U48 provides the inputoutput data that reads and writes data or order passage for clock chip U46.

(4) as shown in figures 1 and 3; In the sampling hold circuit; The first input end COM1 of each high-speed analog switch, the second input end COM2, the 3rd input end COM3, four-input terminal COM4 receiving signal reason and trigger pip produce the sampling of circuit input on the occasion of signal VZ, sampling negative value signal VF; And according to the value of the control signal K1～K16 of timing distribution circuit input; Produce accordingly on the occasion of signal Zi, negative value signal Fi; And will on the occasion of signal Zi (Z1～Z16), negative value signal Fi (F1～F16) is input to the sampled signal conversion input end A17 of ADC single-chip microcomputer U29～U44, ADC single-chip microcomputer U13～U28 respectively, obtains Wave data (being the negative loop on the occasion of part, waveform of waveform) respectively, and is specific as follows:

In the sampling hold circuit; The sampling that the first input end COM1 of high-speed analog switch U9～U12, the second input end COM2, the 3rd input end COM3, four-input terminal COM4 receiving signal reason and trigger pip produce the circuit input is on the occasion of signal VZ, and the first input end COM1 of high-speed analog switch U5～U8, the second input end COM2, the 3rd input end COM3, four-input terminal COM4 receiving signal reason and trigger pip produce the sampling negative value signal VF of circuit input; High-speed analog switch U5～U8 (model MAX4614) etc. is communicated with when Ki=1; Break off during Ki=0; Sampling negative value signal VF according to signal condition and the input of trigger pip generation circuit produces negative value signal Fi accordingly; The sampled signal conversion input end A17 that negative value signal Fi is input to ADC single-chip microcomputer U13～U28 (model STC12C5201AD) etc. respectively carries out the A/D conversion, obtains the negative loop of waveform; In like manner; High-speed analog switch U9～U12 (model MAX4614) etc. is communicated with when Ki=1; Break off during Ki=0; The sampling that produces the circuit input according to signal condition and trigger pip produces on the occasion of signal Zi on the occasion of signal VZ accordingly, is input to sampled signal conversion input end A17 that ADC single-chip microcomputer U29～U44 (model STC12C5201AD) waits respectively on the occasion of signal Zi and carries out A/D and change, obtain waveform on the occasion of part; 100P (pico farad) sampling corresponding during Ki=1 keeps electric capacity (wherein; Sampling keep capacitor C 9～capacitor C 24 grades totally 16 be used for negative value signal Fi sampling and keep; Sampling keep capacitor C 25～capacitor C 40 grades totally 16 be used for keeping on the occasion of signal Zi sampling) follow the waveform voltage value and change; It is stable that the 100P sampling keeps the voltage on the electric capacity during Ki=0, and the saltus step of Ki since 1 to 0 (abbreviation negative edge) triggers corresponding ADC single-chip microcomputer simultaneously and carries out the A/D conversion immediately.

The parameter of each high-speed analog switch (model MAX4614) is: every 4 passage, work in the highest 5.5V of single supply, and ON time 12ns, turn-off time 10ns, conducting resistance is 10 ohm during the work of+5V supply voltage, bandwidth 70MHz;

In the ADC single chip circuit; It is the negative loop of waveform that ADC single-chip microcomputer U13～U28 is responsible for changing negative value signal Fi; J2～J5 is the active crystal oscillator (crystal oscillator) of 4 25MHz; Wherein, Active crystal oscillator J2 sends crystal oscillator signal XAA to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U13～U16; Active crystal oscillator J3 sends crystal oscillator signal XBB to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U17～U20, and active crystal oscillator J4 sends crystal oscillator signal XCC to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U21～U24, and active crystal oscillator J5 sends crystal oscillator signal XDD to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U25～U28; ADC single-chip microcomputer U29～U44 be responsible for changing on the occasion of signal Zi be waveform on the occasion of part; J6～J9 is the active crystal oscillator of 4 25MHz; Wherein, Active crystal oscillator J6 sends crystal oscillator signal XEE to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U29～U32; Active crystal oscillator J7 sends crystal oscillator signal XFF to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U33～U36, and active crystal oscillator J8 sends crystal oscillator signal XGG to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U37～U40, and active crystal oscillator J9 sends crystal oscillator signal XHH to the active crystal oscillator incoming end XT1 of ADC single-chip microcomputer U41～U44; The driving force of active crystal oscillator is very strong, and is safe and reliable for guaranteeing, each active crystal oscillator drives 4 ADC single-chip microcomputers; All ADC single-chip microcomputers begin the A/D conversion at the negative edge of control signal Ki; Sequential distributes control single chip computer U45 can guarantee the time long enough between twice adjacent negative edge of same Ki, satisfies corresponding in check ADC single-chip microcomputer and accomplishes A/D conversion and other routine processes function time requirements; ADC single-chip microcomputer U13 and ADC single-chip microcomputer U29 suspension control signal K1 control " synchronously "; ADC single-chip microcomputer U14 and ADC single-chip microcomputer U30 suspension control signal K2 control " synchronously "; ..., ADC single-chip microcomputer U28 and ADC single-chip microcomputer U44 suspension control signal K16 control " synchronously "; Two groups of each 16 ADC single-chip microcomputers are correspondence " synchronously " fully in time one by one; Between 16 ADC single-chip microcomputers in same group because of being controlled the control of signal Ki; The time that begins to carry out the A/D conversion is the fixing phase place that clocklike staggers; I.e. " asynchronous " is convenient to the negative loop of waveform and waveform synthesized complete waveform on the occasion of part; Waveform must be 0 on the occasion of its negative value sampling of section, and it must be 0 on the occasion of sampling waveform negative value section.

ADC single-chip microcomputer (model STC12C5201AD) related parameter arranged: WV 3.3～5.5V, work clock 0～35MHz, single clock/machine cycle; 8051 kernels, 88 road high-speed ADCs, A/D slewing rate 300KHz; The in-chip FLASH program storage; 256 byte RAM support the ISP programming, and the I/O mouth can be programmed for 4 kinds of patterns.This series has EEPROM version in the strap, can be used as replenishing of storage chip U50 (model is that AT24C512-64KEEPROM or model are AT24C1024-128KEEPROM).

(5) like Fig. 1 and shown in Figure 6; In the main control singlechip circuit; Main control singlechip U48 receiving signal reason and trigger pip produce negative trigger pip UTF, the positive trigger pip UTZ that circuit sends over; And with reference to sequential cycle order; Produce main control singlechip control signal PD; And be sent to the main control singlechip signal input end P10 of each ADC single-chip microcomputer by the terminals P4.0 of main control singlechip U48; Each ADC single-chip microcomputer upgrades its sample conversion concluding time marking signal Wi according to main control singlechip control signal PD respectively; And its sample conversion concluding time marking signal Wi (i=1～8), sample conversion concluding time marking signal Wi (i=9～16) be sent to the first driver U47, the second driver U49 respectively, the first driver U47, the second driver U49 are converted into order accordingly with sample conversion concluding time marking signal Wi (i=1～8), sample conversion concluding time marking signal Wi (i=9～16) respectively and judge that sequence signal P00～P07, order judge sequence signal P20～P27; Main control singlechip U48 sends the control signal WWK of read driver to the first driver U47 and the second driver U49; So that reading in order judges sequence signal P00～P07 and judges sequence signal P20～P27 in proper order; Judge the crucial order foundation of waveform starting point when reading Wave data, be specially as main control singlechip U48:

The ADC single-chip microcomputer is constantly carrying out the A/D conversion always under the control of control signal Ki; Main control singlechip control signal PD (the terminals P4.0 of main control singlechip) is the overall situation " synchronously " order that main control singlechip U48 sends; PD=1 at ordinary times; The A/D transformation result of ADC single-chip microcomputer is not preserved, in case negative trigger pip UTF or positive trigger pip UTZ effective (negative edge is effective), then main control singlechip control signal PD=0; The ADC single-chip microcomputer begins to preserve the A/D transformation result, behind main control singlechip control signal PD=1, just stops to preserve; The ADC single-chip microcomputer of the responsible waveform negative loop sampling of suspension control signal Ki control can be exported sample conversion concluding time marking signal Wi; Sample conversion concluding time marking signal Wi=1 during main control singlechip control signal PD=1; Main control singlechip control signal PD=0 and ADC single-chip microcomputer are accomplished A/D conversion back ADC single-chip microcomputer can export sample conversion concluding time marking signal Wi=0; Because control signal Ki has cycline rule; Therefore the appearance of sample conversion concluding time marking signal Wi=0 state also has the sequencing rule; The state of these sample conversion concluding times marking signal Wi is accomplished the numbering Wm (m=1～16) of the ADC single-chip microcomputer of A/D conversion and saving result after being used to judge PD=0 first, so that read Wave data and carry out waveform synthetic.

Each ADC single-chip microcomputer all has unique address number; They pass through serial port (the serial line interface input end RP30 of ADC single-chip microcomputer is serial port signal TXD, and the serial line interface output terminal TP31 of ADC single-chip microcomputer is serial port signal RXD) and communicate by letter with main control singlechip U48; Main control singlechip U48 sends order, and all ADC single-chip microcomputers all receive, but the ADC single-chip microcomputer can be made different reactions according to the address format in the order; In any moment, the ADC single-chip microcomputer has only one to allow to send, in order to avoid cause bus collision.

(6) like Fig. 1 and shown in Figure 6; Main control singlechip is judged sequence signal according to order; Serial port signal TXD, serial port signal RXD through each ADC single-chip microcomputer read the Wave data (being the negative loop on the occasion of part, waveform of waveform) that obtains in the ADC single-chip microcomputer, and Wave data is synthesized complete waveform signal; Main control singlechip U48 is sent to waveform signal among the storage chip U50 and preserves through serial line interface signal SCL, serial line interface signal SDA; In case waveform signal is lost during power down; And be sent to compunication serial port MX1, and then through rs 232 serial interface signal TXD3, rs 232 serial interface signal RXD3 and compunication through rs 232 serial interface signal TXD2, rs 232 serial interface signal RXD2; Simultaneously; Main control singlechip U48 sends reseting controling signal RST, address selection control signal A0, gating control signal CSS, read control signal RD, write control signal WR to LCD display interface unit J10 respectively through its terminals P4.7, terminals P4.6, terminals P4.1, terminals P3.7, terminals P3.6; The waveform signal that measures is shown, accomplish the measurement and the demonstration of outside thunder-strike current signal.Simultaneously, main control singlechip U48 communicates by letter with the clock chip U46's that produces system clock through its terminals P1.7, terminals P1.6, terminals P1.5 realization, clock read-write and the initialization setting of control clock chip U46.

The active crystal oscillator J13 of main control singlechip is the active crystal oscillator of 25MHz, for U48 work clock is provided separately.In the main control singlechip circuit, the oscillation output end of the active crystal oscillator J13 of main control singlechip is that terminals 3 send crystal oscillator signal XTT to the oscillator incoming end XTAL1 of main control singlechip U48.

Main control singlechip U48 adopts STC12C5A32S2 series; Contain two serial ports; Wherein (TXD～RXD) is used to read the Wave data of all 32 ADC single-chip microcomputers to serial ports 1; Serial ports 2 (TXD2～RXD2) be used to connect compunication serial port MX1, realization is communicated by letter with computing machine, can the Wave data of gathering be transferred to backup or analysis in the computing machine; Storage chip U50 is the eeprom chip AT24C512 (also the eeprom chip AT24C1024 of available 128KB replaces) of a slice 64KB, and (SCL～SDA), be used for backup and preserve Wave data, data can not lost after the power down with the main control singlechip serial line interface.

The first driver U47 and the second driver U49 are two 74HC373 drivers, judge Wm after being used to read sample conversion concluding time marking signal Wi.

Main control singlechip U48 (model STC12C5A32S2 series) has a related parameter: (model STC12C5201AD) is basic identical with the ADC single-chip microcomputer, contains the two serial ports that work alone fully, encapsulates and FLASH program storage capacity is selected as required.We have temporarily selected the STC12C5A08S2 model for use, and 44 pin QFP encapsulation includes the 8K program storage.

The foregoing description is the utility model preferred implementation; But the embodiment of the utility model is not restricted to the described embodiments; Other any do not deviate from change, the modification done under spirit and the principle of the utility model, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within the protection domain of the utility model.

Claims (9)

1. the special digital storage oscilloscope is struck by lightning; It is characterized in that: comprise that signal condition and trigger pip produce circuit, timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit, power circuit, display interface device unit and compunication serial port; Said signal condition and trigger pip generation circuit, sampling hold circuit, ADC single chip circuit connect successively, and timing distribution circuit connects sampling hold circuit, ADC single chip circuit respectively; Said signal condition and trigger pip generation circuit, ADC single chip circuit, power circuit are connected with the main control singlechip circuit respectively; Said compunication serial port connects the main control singlechip circuit, and external computing machine; Said signal condition and trigger pip produce the signal end that circuit connects outside thunder-strike current signal input socket; Said power circuit comprises first output terminal, second output terminal and the 3rd output terminal; Its first output terminal, second output terminal, the 3rd output terminal all connect signal condition and trigger pip produces circuit, and said the 3rd output terminal connects timing distribution circuit, sampling hold circuit, ADC single chip circuit, main control singlechip circuit respectively; Said display interface device unit connects the main control singlechip circuit, and external display.

2. thunderbolt special digital storage oscilloscope according to claim 1 is characterized in that: said signal condition and trigger pip produce circuit and comprise impedance inverter circuit, isolation buffer circuit, half-wave rectifying circuit and main control singlechip interrupt control circuit; Said impedance inverter circuit comprises first operational amplifier, and first operational amplifier comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input and first output terminal; The positive source incoming end of said first operational amplifier, power cathode incoming end connect first output terminal, second output terminal of power circuit respectively; First in-phase input end of first operational amplifier connects the signal end of outside thunder-strike current signal input socket; First inverting input of first operational amplifier connects first output terminal of first operational amplifier, and first output terminal of first operational amplifier connects half-wave rectifying circuit; Said half-wave rectifying circuit connects first output terminal, second output terminal of power circuit respectively;

Said isolation buffer circuit comprises second operational amplifier, and second operational amplifier comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input, first output terminal, second in-phase input end, second inverting input and second output terminal; The positive source incoming end of second operational amplifier connects first output terminal of power circuit, its power cathode incoming end ground connection; First in-phase input end of second operational amplifier connects half-wave rectifying circuit; First inverting input of second operational amplifier connects its first output terminal, and first output terminal of second operational amplifier connects sampling hold circuit, main control singlechip interrupt control circuit; Second in-phase input end of second operational amplifier connects half-wave rectifying circuit, and second inverting input of second operational amplifier connects its second output terminal, and its second output terminal connects sampling hold circuit, main control singlechip interrupt control circuit;

Said main control singlechip interrupt control circuit connects the 3rd output terminal, the main control singlechip circuit of power circuit respectively.

3. thunderbolt special digital storage oscilloscope according to claim 2 is characterized in that: said half-wave rectifying circuit comprises first resistance, first diode, second diode, the 3rd resistance, the 3rd operational amplifier, the 3rd diode, the 4th diode, second resistance and the 4th resistance; Said the 3rd operational amplifier comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input, first output terminal, second in-phase input end, second inverting input and second output terminal, and the positive source incoming end of the 3rd operational amplifier, power cathode incoming end connect first output terminal, second output terminal of power circuit respectively; The positive pole of first diode connects first inverting input of the 3rd operational amplifier, and its negative pole connects first output terminal of the 3rd operational amplifier; The positive pole of second diode connects first output terminal of the 3rd operational amplifier, and its negative pole connects first in-phase input end of second operational amplifier; One end of said first resistance connects the positive pole of first diode, and its other end connects the negative pole of second diode; One end of the 3rd resistance connects first output terminal of first operational amplifier, and its other end connects first inverting input of the 3rd operational amplifier; The first in-phase input end ground connection of the 3rd operational amplifier, its second in-phase input end connects an end of the 4th resistance, and the other end of the 4th resistance connects first output terminal of first operational amplifier; Second inverting input of the 3rd operational amplifier connects the positive pole of the 4th diode, and its second output terminal connects the negative pole of the 4th diode; The positive pole of the 3rd diode connects the negative pole of the 4th diode, and its negative pole connects second in-phase input end of second operational amplifier; One end of second resistance connects the positive pole of the 4th diode, and its other end connects the negative pole of the 3rd diode.

4. thunderbolt special digital storage oscilloscope according to claim 3 is characterized in that: said main control singlechip interrupt control circuit comprises first electric capacity, the 6th resistance, the 7th resistance, the 8th resistance, high-speed comparator and the 5th resistance; Said high-speed comparator comprises positive source incoming end, power cathode incoming end, first in-phase input end, first inverting input, first output terminal, second in-phase input end, second inverting input and second output terminal; One end of the 7th resistance connects the 3rd output terminal of power circuit, and its other end connects first in-phase input end of high-speed comparator; First inverting input of high-speed comparator connects first output terminal of second operational amplifier, and first output terminal of high-speed comparator connects an end of main control singlechip circuit, the 6th resistance respectively; The other end of the 6th resistance connects the 3rd output terminal of power circuit; The positive pole of first electric capacity connects the 3rd output terminal of power circuit, the minus earth of first electric capacity; The two ends of said the 8th resistance connect first in-phase input end of high-speed comparator, the power cathode incoming end of high-speed comparator respectively; The power cathode incoming end ground connection of high-speed comparator, its positive source incoming end connects the 3rd output terminal of power circuit; Second inverting input of high-speed comparator connects second output terminal of second operational amplifier, and second output terminal of high-speed comparator connects the main control singlechip circuit; One end of the 5th resistance connects the positive source incoming end of high-speed comparator, and its other end connects second output terminal of high-speed comparator; Second in-phase input end of high-speed comparator is connected with its first in-phase input end.

5. thunderbolt special digital storage oscilloscope according to claim 4; It is characterized in that: said signal condition and trigger pip produce circuit and also comprise second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 5th diode, the 6th diode, the 7th diode and the 8th diode; The plus earth of said the 5th diode, its negative pole connect first in-phase input end of second operational amplifier; The plus earth of said the 6th diode, its negative pole connect second in-phase input end of second operational amplifier; The minus earth of the 7th diode, its anodal positive pole that connects the 8th diode, the negative pole of the 8th diode connects first in-phase input end of first operational amplifier; The positive pole of the positive pole of said the 3rd electric capacity, the 4th electric capacity all connects the positive source incoming end of second operational amplifier; The positive pole of the 5th electric capacity connects the positive source incoming end of the 3rd operational amplifier; The positive pole of the 8th electric capacity connects the positive source incoming end of first operational amplifier, and the negative pole of the 3rd electric capacity, the negative pole of the 4th electric capacity, the negative pole of the 5th electric capacity, the equal ground connection of negative pole of the 8th electric capacity; The negative pole of said second electric capacity connects the power cathode incoming end of first operational amplifier; The negative pole of the negative pole of the 6th electric capacity, the 7th electric capacity all connects the power cathode incoming end of the 3rd operational amplifier, and anodal all ground connection of the positive pole of the positive pole of second electric capacity, the 6th electric capacity, the 7th electric capacity.

6. thunderbolt special digital storage oscilloscope according to claim 5 is characterized in that: said sampling hold circuit comprises that first group of high-speed analog switch, second group of high-speed analog switch and several samplings keep electric capacity; First group of high-speed analog switch, second group of high-speed analog switch comprise several high-speed analog switchs respectively, and each high-speed analog switch includes positive source incoming end, power cathode incoming end, first input end, second input end, the 3rd input end, four-input terminal, the 5th input end, the 6th input end, the 7th input end, the 8th input end, first output terminal, second output terminal, the 3rd output terminal and the 4th output terminal; The positive source incoming end of said each high-speed analog switch all connects the 3rd output terminal of power circuit; The equal ground connection of power cathode incoming end of said each high-speed analog switch; Corresponding respectively first output terminal, second output terminal, the 3rd output terminal, the 4th output terminal that is connected to each high-speed analog switch of positive pole that each is sampled and keeps electric capacity, and the equal ground connection of negative pole of each sampling maintenance electric capacity;

First output terminal of each high-speed analog switch, second output terminal, the 3rd output terminal, the 4th output terminal are connected in the ADC single chip circuit respectively accordingly;

First input end, second input end, the 3rd input end, the four-input terminal of each high-speed analog switch in first group of high-speed analog switch all connects first output terminal of second operational amplifier; First input end, second input end, the 3rd input end, the four-input terminal of each high-speed analog switch in second group of high-speed analog switch all connects second output terminal of second operational amplifier;

The 5th input end of each high-speed analog switch, the 6th input end, the 7th input end, the 8th input end connect timing distribution circuit respectively accordingly.

7. thunderbolt special digital storage oscilloscope according to claim 6 is characterized in that: the positive source incoming end of each high-speed analog switch also is connected with power filtering capacitor respectively, the other end ground connection of power filtering capacitor.

8. thunderbolt special digital storage oscilloscope according to claim 6 is characterized in that: said timing distribution circuit comprises sequential distribution control single chip computer, active crystal oscillator, clock chip, clock chip crystal oscillator and battery; Said sequential distributes control single chip computer to comprise control signal output ends, oscillator incoming end, positive source incoming end and power cathode incoming end; Said sequential is distributed the 3rd output terminal of the positive source incoming end connection power circuit of control single chip computer, its power cathode incoming end ground connection; It is several that said sequential is distributed the control signal output ends of control single chip computer; Each control signal output ends is connected to the 5th input end, the 6th input end, the 7th input end, the 8th input end of each high-speed analog switch of every group of high-speed analog switch respectively accordingly, and each control signal output ends also connects the ADC single chip circuit respectively; Said active crystal oscillator comprises positive source input end, power cathode input end and oscillation output end; Its oscillation output end connects the oscillator incoming end that said sequential is distributed control single chip computer; Its positive source input end connects the 3rd output terminal of power circuit, its power cathode input end grounding;

Said clock chip comprises that first input end, second input end, the 3rd input end, four-input terminal, the 5th input end, exterior read-write synchronous clock input end, clock data input/output terminal and sheet select input end; The first input end of clock chip connects the 3rd output terminal of power circuit, corresponding respectively two output terminals that connect the clock chip crystal oscillator of its second input end, the 3rd input end; The four-input terminal ground connection of clock chip, the 5th input end of clock chip connects the positive pole of battery, the minus earth of battery; Exterior read-write synchronous clock input end, clock data input/output terminal and the sheet of clock chip select input end to be connected with resistance respectively, and the other end of said resistance all is connected to the 3rd output terminal of power circuit; Exterior read-write synchronous clock input end, clock data input/output terminal and the sheet of clock chip select input end all to be connected the main control singlechip circuit.

9. thunderbolt special digital storage oscilloscope according to claim 8 is characterized in that: said ADC single chip circuit comprises several ADC single-chip microcomputers and the active crystal oscillator of several ADC single-chip microcomputers; Each ADC single-chip microcomputer has included serial line interface input end, serial line interface output terminal, active crystal oscillator input end, sequential distributing signal input end, power cathode input end, positive source input end, sampled signal conversion input end, sample conversion concluding time marking signal output terminal and main control singlechip signal input end; The positive source input end of each ADC single-chip microcomputer all connects the 3rd output terminal of power circuit, the equal ground connection of its power cathode input end; Corresponding respectively first output terminal, second output terminal, the 3rd output terminal, the 4th output terminal that connects each high-speed analog switch of sampling hold circuit of sampled signal conversion input end of each ADC single-chip microcomputer; The sequential distributing signal input end of each ADC single-chip microcomputer is connected to the control signal output ends of timing distribution circuit respectively accordingly; The sample conversion concluding time marking signal output terminal of each ADC single-chip microcomputer, main control singlechip signal input end, serial line interface input end, serial line interface output terminal connect the main control singlechip circuit respectively; The active crystal oscillator of each ADC single-chip microcomputer includes positive source input end, power cathode input end and oscillation output end; Its positive source input end all connects the 3rd output terminal of power circuit; The equal ground connection of its power cathode input end, its oscillation output end connects the active crystal oscillator input end of corresponding ADC single-chip microcomputer;

The main control singlechip circuit comprises main control singlechip, the active crystal oscillator of main control singlechip, first driver, second driver, storage chip and button; The active crystal oscillator of main control singlechip, first driver, second driver, storage chip all are connected with main control singlechip; And the active crystal oscillator of main control singlechip, first driver, second driver, storage chip all are connected with the 3rd output terminal of power circuit, and first driver, second driver also connect the sample conversion concluding time marking signal output terminal of each ADC single-chip microcomputer respectively; Said button connects main control singlechip, and connects the 3rd output terminal of power circuit through resistance.

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