CN201966241U - LED chip and LED wafer - Google Patents

LED chip and LED wafer Download PDF

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Publication number
CN201966241U
CN201966241U CN 201020616973 CN201020616973U CN201966241U CN 201966241 U CN201966241 U CN 201966241U CN 201020616973 CN201020616973 CN 201020616973 CN 201020616973 U CN201020616973 U CN 201020616973U CN 201966241 U CN201966241 U CN 201966241U
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wafer
heat diffusion
diffusion member
led chip
spacer
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CN 201020616973
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秦彪
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

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Abstract

The utility model provides an LED chip packaging structure, a wafer structure and a chip manufacturing method, which aims at reducing heat conduction heat-resistance, lowering the cost and improving the efficiency. A wafer in an LED chip is embedded into a positioning plate (6); and the wafer and the positioning plate are attached on a heat diffusion piece (7) through welding or adhering. The heat diffusion piece is made of copper or aluminum, or copper-aluminum compounded materials, after a high heat-flow density on the wafer passes through the heat diffusion piece, the heat-flow density is effectively reduced, thereby being beneficial for reducing the heat conduction heat-resistance. With the adoption of a conduction line welding, solder welding or conductive paste adhesion method, a wiring bonding pad (1) on the positioning plate is conducted with an electrode bonding pad (2) on the front surface or the side wall of the wafer. A solid crystal protective layer (5) is arranged on the front surface of the wafer, so that the package production of the chip is effective and simple.

Description

A kind of led chip and LED wafer
Technical field
The utility model belongs to the LED lighting technical field, specially refers to the chip architecture of interior heat conducting encapsulating structure of led chip and realization low thermal resistance chip.
Technical background
Heat radiation has become the big key issue in the great power LED development process.The LED heat radiation can be divided into two big processes: inner conduction heat transfer process and outside air convection diabatic process.The interior conduction heat transfer thermal resistance of existing disclosed led chip accounts for the very large ratio of whole heat transfer resistance, and what existing product thermal resistance was minimum also will reach 6 ℃/W, if add the insulating barrier thermal resistance on the aluminium base, minimum also will reach 10 ℃/W.
Diabatic process in the led chip is also uncomplicated, but because thermal conduction study and ripe heat transfer technology knowledge, and with other the related rudimentary knowledge of conducting heat less than fully by personnel's cognition in the LED industry, thereby current LED heat dissipation technology and product be complicated, and is in the junior stage.In addition, existing disclosed led chip encapsulating structure, all be along before the development of low-power LED chip and conditional electronic Chip Packaging thinking come, the conduction heat transfer thermal resistance is high to the above in not only making, and packaging efficiency is low, the sealed in unit costliness, the packaging cost height is difficult for realizing the integrated encapsulation of optical mode group.
Summary of the invention
The purpose of this utility model is exactly at led chip encapsulating structure problem, propose a kind of brand new, not only effectively reduce inner thermal conduction resistance problem, but also help improving packaging efficiency, reduce packaging cost, help to realize the integrated encapsulation of optical mode group especially.
The technical solution of the utility model: led chip mainly includes one or many wafers, spacer and heat diffusion members, feature of the present utility model is: have wafer embedding mouth on the spacer, wafer is embedded in this wafer embedding mouth, wafer and spacer are attached on the one side of heat diffusion member, and this face is called the A face of heat diffusion member; Spacer adopts insulating material to make, and spacer is provided with circuit and lead pad; Electrode pad on the front wafer surface (that face of bright dipping) or the electrode pad on the sidewall are connected with the conducting between the corresponding lead pad on the spacer and have adopted that wire bonds connection, scolder are welded to connect, conductive adhesive connects; Adopted welding or viscose glue to be connected between the A face of wafer and heat diffusion member; Heat diffusion member has adopted copper material or aluminum material or copper aluminum composite material.Be connected at the conducting between the corresponding lead pad on the electrode pad on the wafer and the spacer and adopt that scolder is welded to connect, the conductive adhesive syndeton, the utility model proposes two kinds of new construction LED wafers, the LED wafer includes substrate, LED working lining, electrode pad, new construction (one) be characterised in that: be coated with insulating barrier near on the LED working lining sidewall of outer electrode pad, this insulating barrier reaches substrate; New construction (two) be characterised in that: the sidewall of wafer is provided with electrode pad.
The innovation of the utility model maximum is to adopt the wafer orientation sheet, be laid with circuit and lead pad on the spacer, wafer is embedded in the wafer embedding mouth on the keeper, it is consistent with wafer thickness that the Thickness Design of spacer becomes, make the conducting of the lead pad on electrode pad and the spacer on the front wafer surface be connected, not only can adopt the wire bonding method (as the gold ball bonding method) that is now adopted, can also adopt scolder welding conducting method and conductive adhesive conducting method.Concrete measure: the electrode pad on the wafer is against the edge, nestles up with corresponding lead pad on the spacer, can adopt the method for biting that scolder (tinol) or conducting resinl are set on two pads, and heat fused or curing again realizes two pad conductings.Can once bite with the amalgamation of number multicore sheet together, add thermal weld (or curing) together, production efficiency height like this, cost is low, and the gold ball bonding of saving costliness connects equipment and spun gold.Spacer adopts insulating trip (film) material, adopts clicking technique processed wafer embedding mouth, the efficient height, and the precision height can adopt existing printed circuit technology to lay circuit and lead pad.
Chip for the flip-over type structure, and wafer substrates is the chip (as the chip of silicon carbide substrates) of electric conductor, then can electrode pad be set, just can adopt scolder welding or conductive adhesive method to make the electrode pad of wafer on being be connected conducting with lead pad on the spacer at the sidewall (sidewall of substrate) of wafer.
Be laid with circuit on the spacer, the external chip pin or the circumscripted power line of chip then are connected conducting by the circuit on the spacer with lead pad.Adopt such structural advantages to have: be convenient to be provided with many wafers of number on a heat diffusion member, constitute powerful optical mode core assembly sheet, the serial or parallel connection between these LED wafers then connects realization by the circuit on the spacer; The required auxiliary electron element (such as anti-static component) of led chip also can be arranged on the spacer, even can adopt similar LED wafer to be embedded in structure in the spacer, auxiliary electron element (even wafer of auxiliary electron element) is embedded in the spacer, adopts same welding or conductive adhesive method; The employing wafer is embedded in the structure in the spacer, helps wafer orientation and contraposition, is convenient to produce in enormous quantities, raises the efficiency.Also has narration among the embodiment afterwards.
Heat diffusion member in the utility model, though it is similar with the heat sink diabatic process of existing product, but the utility model is clearly emphasized its most important functions---thermal diffusion effect first, thereby is referred to as heat diffusion member, current common notion and the importance thereof of all not knowing thermal diffusion of LED industry.Because the conductive coefficient height of copper and aluminium, price is low, thereby first-selected copper material or aluminum material or copper aluminum composite material making heat diffusion member.The led chip encapsulation also must be considered the Insulation Problems of electricity, and insulation and heat conduction are again conflicting, particularly for High-Voltage Insulation.
The LED chip area is little, and as the wafer of 1 * 1mm size, even power consumption 1.2W, its density of heat flow rate just reaches 10 6W/m 2More than, very high, it is extremely important to reduce density of heat flow rate.Existing product is for solving the Insulation Problems of electricity, and it is heat sink generally to adopt potsherd to do, and owing to the cost reason, generally adopts Al 2O 3Pottery, Al 2O 3The pottery conductive coefficient be about 20W/mK, the LED wafer is set directly on the potsherd, if potsherd thick be 0.2mm, then the heat conduction temperature difference on potsherd will reach 10 ℃.In the utility model, wafer is set directly at and adopts on the heat diffusion member (A face) that copper or aluminium or copper aluminum composite material makes, reduced the conduction process between wafer and the thermal diffusion sheet, because the conductive coefficient height of copper or aluminium, high heat flux is through heat diffusion member, density of heat flow rate is lowered, for insulation (main High-Voltage Insulation) insulating barrier of problem that solves electricity just can be arranged on that side (the B face that is called heat diffusion member) of heat diffusion member and fin transmission of heat by contact.If density of heat flow rate has reduced by five times, adopt the thick Al of 0.2mm equally 2O 3Potsherd is made insulating barrier, and then the heat conduction temperature difference on the insulating barrier just can be reduced to 2 ℃.
Heat diffusion member as the thermal diffusion effect not only will adopt the high material of thermal conductivity, and it is enough big that its area and thickness are also wanted, if wafer is 1 * 1mm, 1W, the thickness of heat diffusion member should reach more than the 1.0mm, and area should be greater than 5mm 2, its purpose and effect are exactly to make heat effectively diffusion in heat diffusion member, reduce density of heat flow rate.
Wafer preferably makes and directly is welded on the heat diffusion member, because wafer and heat diffusion member junction density of heat flow rate are the highest, the conductive coefficient of the material of faying face (scolder or viscose glue) is high as far as possible, the conductive coefficient height of metal material, conductive coefficient such as tin is 60W/mK, is higher than to several times heat conduction viscose glue (such as elargol).
Description of drawings
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is a kind of feature profile schematic diagram of the utility model led chip, adopts ultrasonic wave spun gold ball method welding lead, and dotting glue method is provided with solid brilliant protective layer.
Fig. 2 is a kind of feature profile schematic diagram of the utility model led chip, adopts pressure welding method welding lead, and The tape casting is provided with solid brilliant protective layer.
Fig. 3 is a kind of feature profile schematic diagram of the utility model led chip, and the electrode pad on welding of employing scolder or the conductive adhesive method realization wafer is connected conducting with the lead pad on the spacer, Gu brilliant protective layer can adopt the film applicator coating setting.
Fig. 4 is a kind of feature profile schematic diagram of the utility model led chip, electrode pad on welding of employing scolder or the conductive adhesive method realization wafer is connected conducting with the lead pad on the spacer, lateral electrode pad on the wafer is arranged on the sidewall of wafer, and the A face of heat diffusion member is provided with the low-voltage insulation layer.
Fig. 5 is a kind of feature profile schematic diagram of the utility model led chip, both sides electrode pad on the wafer all is arranged on the sidewall of wafer, the B face of heat diffusion member is provided with high-voltage insulation layer, is provided with dielectric film between the A face of heat diffusion member and spacer and the wafer part area.
Fig. 6 is the spacer in a kind of the utility model led chip and the back side feature schematic diagram of wafer, and the filleting along wafer and spacer is provided with dielectric film, but the wafer middle part does not have dielectric film.
Fig. 7 is a kind of LED wick that adopts the utility model led chip feature profile schematic diagram of (or claiming the optical mode group), and heat conduction core adopts conical structure.
Fig. 8 is a kind of feature profile schematic diagram that has adopted the LED wick of the utility model led chip, and heat diffusion member and heat conduction core are integrated, and has adopted light-focusing type wick cover.
Fig. 9,10, the 11st, a kind of manufacturing process process schematic diagram of expression the utility model led chip.
Figure 12 is a kind of feature profile schematic diagram of the utility model LED wafer, and substrate is an insulator, and two electrode pads on the wafer are all in the front of wafer.
Figure 13 is a kind of feature profile schematic diagram of the utility model led chip, and substrate is an insulator, formal dress formula structure.
Figure 14 is a kind of feature profile schematic diagram of the utility model LED wafer, and substrate is an electric conductor, and two electrode pads on the wafer are all in the front of wafer.
Figure 15 is a kind of feature profile schematic diagram of the utility model led chip, and substrate is an electric conductor, formal dress formula structure, and wherein a lateral electrode pad is arranged on the sidewall of wafer.
Figure 16 is a kind of feature profile schematic diagram of the utility model led chip, and substrate is an insulator, the flip-over type structure, and wherein a lateral electrode pad is arranged on the sidewall of wafer.
Figure 17 is a kind of feature profile schematic diagram of the utility model led chip, and substrate is an insulator, the flip-over type structure, and the both sides electrode pad on the wafer all is arranged on the sidewall of wafer.
Figure 18 is a kind of LED wafer feature schematic diagram of the present utility model, and electrode pad is in the front of wafer, and is arranged on four angles.
Figure 19 is a kind of LED wafer feature schematic diagram of the present utility model, and electrode pad and is arranged on four angles on the sidewall of wafer.
Figure 20 is a kind of feature schematic diagram of the utility model led chip, represents to be inlaid with many wafers in the wafer embedding mouth.
Among the figure: 1, lead pad, 2, electrode pad, 3, wafer; 4, lead, 5, solid brilliant protective layer, 6, spacer; 7, heat diffusion member, 8, scolder or conducting resinl, 9, the low-voltage insulation layer; 10, dielectric film; 11, high-voltage insulation layer, 12, heat conduction core, 13, screw; 14, lens; 15, fluorophor, 16, the wick cover, 17, transparency electrode; 18, LED working lining (n type semiconductor layer+luminescent layer+p type semiconductor layer); 19, diaphragm, 20, insulating barrier, 21, substrate; 22, thermal land, 23, ceramic insulating film.
Embodiment
The utility model led chip shown in Figure 1, wafer 3 are embedded in the wafer embedding mouth in the spacer 6, and wafer 3 and spacer 6 are attached to the A face of heat diffusion member 7 together; Front wafer surface and part spacer surface are provided with solid brilliant protective layer 5; Electrode pad 2 on the wafer nestles up with the lead pad 1 on the spacer, and the conducting between two pads connects adopts ultrasonic wave ball technology, and lead 4 (gold thread or aluminum steel) two erects from bond pad surface.Because wire diameter is thin, intensity is low, and 5 of solid brilliant protective layers on the front wafer surface should adopt the gluing process setting, as shown in the figure, Gu brilliant protective layer 5 is in uneven thickness.
The utility model led chip shown in Figure 2, lead 4 two are flattened on two pads, adopt the bond technology welding; because lead lies low, intensity is higher relatively, Gu brilliant protective layer 5 just can adopt the casting technique setting; Gu brilliant protective layer thickness just can be even, as shown in FIG..
The utility model led chip shown in Figure 3, distance is nearer between electrode pad 2 on the wafer 3 and the lead pad 1 on the spacer 6, between conducting connect and just can directly adopt scolder (such as tin) welding conducting or the conducting of employing conductive adhesive.Do not have lead, conduct electricity by scolder (or conducting resinl), Gu brilliant protective layer 5 just can adopt viscose glue pad pasting (or paster) method and the setting of printing (biting) method.
The utility model led chip shown in Figure 4, the lateral electrode pad 2 on the wafer are arranged on the sidewall on the wafer 3, and another electrode pad 2 is arranged on the front of wafer 3.Substrate is the wafer of electric conductor (as silicon carbide substrates), is fit to adopt such design.
Also illustrate among Fig. 4, be provided with low-voltage insulation layer 9 at the A of heat diffusion member 7 face, because wafer 3 directly is attached on (weldering or sticking) low-voltage insulation layer 9, density of heat flow rate is very high, the thermal conduction resistance of low-voltage insulation layer 9 must be low, but the conductive coefficient of insulating material is all low, thereby the thickness of insulating barrier just should approach, then the dielectric strength of proof voltage is also just low, so be called as the low-voltage insulation layer.
The ceramic insulating film that adopts vapour deposition process to generate is such as diamond, SiC, AlN, BN, BeO, Al 2O 3Deng ceramic membrane, densification, good insulating, thermal conductivity height, particularly diamond, SiC, AlN, BN, BeO are high thermal conduc tivity ceramics, not only can be used for the low-voltage insulation layer on the thermal diffusion sheet A face in the utility model, after being applicable to more with the ceramic insulating film on the wafer of setting forth.Vapour deposition process includes physical vapor deposition (PVD) and chemical vapour deposition (CVD) (VCD), and these two kinds of technologies all can be used for making the low-voltage insulation layer in the utility model.
Low-voltage insulation layer 9 also can adopt anode oxidation process, the direct pellumina that grows from the metallic aluminium on heat diffusion member surface, but this pellumina thickness is not more than 50 μ m.Because the pellumina that adopts anodic oxidation to generate has hole, handle (as adopting silicone grease) though can carry out sealing of hole, the conductive coefficient of this film is not high, thereby the thickness of film should be too not thick, should be greater than 50 μ m.If heat diffusion member adopts copper material, just should adopt copper aluminum composite material this moment.
The utility model led chip shown in Figure 5, two electrode pads 2 all are arranged on the sidewall of wafer 3 on the wafer, and such design is suitable for flip-chip (also claiming to cover crystalline substance) structure, and more detailed description is arranged later on.Gu brilliant protective layer 5 can adopt with the setting of printing (as biting) method, fluorescent material can be added in the material of solid brilliant protective layer.
Dielectric film 10 also has been shown among Fig. 5, this insulating barrier is located at the back side of spacer and wafer, along the filleting between wafer 3 and the spacer 6, as shown in Figure 6, the chip back surface middle part is left and is not insulated film 10 area coverages, this area will have chip area over half at least, and this area is used for conductive force.Adopt spraying or printing (as biting) method that dielectric film 10 is set, can make in the filleting between insulating varnish infiltration wafer 3 and the spacer 6, improve insulating reliability.Such design for adopting formal dress formula structure, utilizes the structure of wafer substrates (as sapphire) as high-voltage insulation layer, and is even more important.
The high heat flux of wafer, through behind the heat diffusion member, density of heat flow rate reduces, just can derive face, promptly be called the B face of heat diffusion member, be provided with and bear high voltage withstanding insulating barrier at the heat diffusion member heat, this insulating barrier is called high-voltage insulation layer, as shown in Figure 5, at the B of heat diffusion member 7 face, be provided with high-voltage insulation layer 11.
In the utility model, high-voltage insulation layer is defined as and bears dc breakdown voltage and reach the above insulating barrier of 500V.
Fig. 7 illustrates a kind of LED illuminating module that adopts the utility model led chip, be called the LED wick, be provided with many wafers in the led chip, and be fixed on by screw 13 on the heat conduction core 12 of LED wick, heat conduction core 12 has adopted conical structure, the heat that chip produces passes to heat conduction core 12 by the transmission of heat by contact between heat diffusion member 7 and the heat conduction core 12, and taper seat and the transmission of heat by contact between the fin by heat conduction core passes on the fin again, sheds again.The A face of heat diffusion member 7 is provided with low- voltage insulation layer 9, and 11 of high-voltage insulation layers are arranged on the heat conduction core 12.
Among Fig. 7, be provided with lens 14 before each wafer 3, be embedded with fluorophor 15 in the lens 14 again; can be with several lens design parts in aggregates on the led chip; after finishing the setting-in of fluorophor, integral adhesive is before wafer, and lens 15 can become the solid brilliant protective layer of wafer 3 again.
In the LED wick shown in Figure 8, heat diffusion member and heat conduction core 12 are integrated, and are cone.If the demanding words of isolated insulation of electricity, it is the formal dress formula that such design is suitable for wafer, and wafer substrates is insulator (as a Sapphire Substrate).Can adopt the method for biting that solid brilliant protective layer 5 is set, and in solid brilliant protective layer 5, add fluorescent material.Also illustrate among the figure and adopt light-focusing type wick cover 16.
Led chip shown in Fig. 1 to 6, and the led chip among Fig. 7, heat diffusion member 7 is a plank frame.For bearing the thermal diffusion effect, it is enough big that the area of heat diffusion member is wanted, and the area of heat diffusion member 7 should be greater than five times of all LED chip area sums on this heat diffusion member; The thickness of heat diffusion member is also enough thick, gets usually and is not less than 0.5mm, if 1 * 1mm wafer power consumption reaches 1.0W, the thick of heat diffusion member should be greater than 1.0mm.
Fig. 9,10,11 illustrates a kind of the utility model led chip manufacturing process, and operation includes: the pad conducting that the wafer that wafer embeds spacer embeds between the lead pad on electrode pad and the spacer on operation, the wafer is connected operation, welding or bonding process between solid brilliant protective layer operation, wafer and the heat diffusion member is set.Fig. 9 embeds operation for the wafer that wafer 3 is inlaid into spacer 6, and finished electrode pad and be connected operation with pad conducting between the lead pad.For scolder welding or conducting resinl bonding, should adopt a smooth liner plate in this operation shown in the figure, wafer 3 and spacer 6 are attached on this liner plate, preferably, be with some glue on the film, when wafer embeds spacer, can be stuck at a liner plate face upper berth skim, difficult drop-off, glue should select not heatproof, when welding, is subjected to high temperature, glue volatilizees voluntarily, so that later operation is simple, easily film is removed, liner plate is the aid in the production process.
Figure 10 shows that solid brilliant protective layer operation is set, can adopt dotting glue method or spraying process or The tape casting or print process (such as the method for biting) or paster (film) method.The operation that solid brilliant protective layer is set also can be placed on the pad conducting and connect before the operation.Solid brilliant protective layer 5 has been arranged before the wafer 3; wafer 3 is fixed on the spacer 6; can not come off; wafer is protected layer protection again; difficult the entering from this face of water and air touches wafer; this is the cause of solid brilliant protective layer title just, and the solid brilliant process distinction during this technical characterictic is produced with existing led chip is obvious.Wafer is fixed, and wafer and spacer just can take off from liner plate, carries out next process, and dielectric film 10 is set if desired, just can carry out this operation.Operation afterwards has welding adopted or adhering method, wafer is attached to operation on the heat diffusion member, as shown in figure 11.
Can be on a big location sheet material of opening a plurality of spacers of the number of permutations; can embed many wafers of number on each spacer; heat diffusion member too; scolder or conducting resinl (such as the employing method of biting) can be set so simultaneously, and integral body adds thermal weld or curing, and integral body is provided with solid brilliant protective layer; the big spacer of opening is with wafer; whole ground is attached on the heat diffusion member, cuts afterwards again, and production efficiency is improved like this.
Energising detects operation and can be arranged on after the pad conducting connection operation, is provided with before the solid brilliant protective layer operation, so just problematic welding or conductive adhesive can be repaired, or change problematic wafer.This is very beneficial for improving rate of finished products for the production of the led chip that many wafers are arranged, and this technical characterictic does not have in existing led chip manufacturing.
The utility model LED wafer shown in Figure 12; substrate 21 is an insulator; similar with the formal dress formula LED wafer of existing Sapphire Substrate; LED working lining 18 skins are provided with transparency electrode 17; transparency electrode 17 is provided with electrode pad 2 (electrode pad 2 on the left side among the figure); this electrode pad is called the outer electrode pad, and transparency electrode 17 outer surfaces are provided with protective layer 19.The utility model LED wafer principal character different with existing product is: be coated with insulating barrier 20 on the sidewall near the LED working lining 18 of outer electrode pad (electrode pad 2 on the left side in as figure), this insulating barrier reaches substrate 21, its effect and purpose are: when adopting scolder welding conducting or conductive adhesive conducting connection electrode pad and lead pad, prevent that scolder or conducting resinl from touching second half conductor layer in the LED working lining 18, produce short-line problem.The outer electrode pad may be a p lateral electrode pad, also may be n lateral electrode pad (adopting lift-off technology, the conversion substrate).Can adopt gas phase to become embrane method (sedimentation), when generating diaphragm 19, generate insulating barrier 20 simultaneously, also can adopt lithographic plate type printing technology that insulating barrier 20 is set.
In the utility model led chip shown in Figure 13, adopted wafer as shown in figure 12, and substrate 21 is provided with large-area thermal land 22.Wafer adopts welding to be attached on the heat diffusion member 7, and the heat that helps on the wafer passes on the heat diffusion member 7.Shown in the figure, adopt scolder welding conducting to be connected between electrode pad 2 and the lead pad 1 or the conductive adhesive conducting connects, insulating barrier 20 has been arranged, and the scolder in left side or conducting resinl can not touch second half conductor layer in the LED working lining 18 (internal layer among the figure), and phenomenon is short-circuited.
The utility model LED wafer shown in Figure 14, two electrode pads 2 are all in the front of wafer, be the formal dress formula, insulating barrier 20 on LED working lining 18 sidewalls on outer electrode pad next door, not only reach substrate 21, but also reached on the sidewall of substrate 21, this is because the substrate of this wafer 21 is an electric conductor, such as silicon carbide substrates.Also illustrate among the figure, the back side of wafer (below the substrate) is provided with the ceramic insulating film 23 that adopts CVD (Chemical Vapor Deposition) method to generate.
The utility model led chip shown in Figure 15, used crystal chip and shown in Figure 14 similar, substrate is an electric conductor, the insulating barrier 20 on left side electrode pad (outer electrode pad) next door has reached on the sidewall of substrate 21, can guarantee the scolder on the left side or the substrate that conducting resinl 8 is difficult for touching conduction like this, situation is short-circuited.Difference has: other electrode pad 2 on the wafer (the right among the figure) is arranged on the sidewall of wafer, also has chip back surface to be provided with large-area thermal land 22, and wafer is attached on the heat diffusion member 7 by welding.
The utility model led chip shown in Figure 16, adopt flip-over type (also claiming crystal covering type), substrate 21 is front wafer surface (exiting surface), on the wafer wherein a lateral electrode pad be arranged on the sidewall of wafer (substrate), and adopted scolder welding or conductive adhesive method to be connected with lead pad realization conducting on the spacer 6.The opposite side electrode pad is at the back side of wafer on the wafer, and as thermal land 22, heat diffusion member 7 is used as lead.Be provided with high-voltage insulation layer 11. at the B of heat diffusion member 7 face
The utility model led chip shown in Figure 17, also adopt flip-over type, both sides electrode pad 2 on the wafer all is arranged on the sidewall of wafer (substrate), wherein the sidewall of the LED working lining on lateral electrode pad next door is provided with insulating barrier 20, be provided with the ceramic insulating film 23 that has adopted vapour deposition process to generate at the back side of wafer, and be provided with large-area thermal land 22 in this film outside.Insulating barrier 20 also can adopt vapour deposition process to generate simultaneously with ceramic insulating film 23.
The utility model LED wafer shown in Figure 180, both sides electrode pad 2 be all in the front of wafer, and be arranged on the angle of wafer, and wafer is a rectangle, in the time of can preventing that wafer from embedding spacer, wrong court takes place.The utility model LED wafer shown in Figure 19, both sides electrode pad 2 all on the sidewall of wafer, also is arranged on the angle, and four jiaos of wafer are processed to 1/4th garden breach.The advantage that electrode pad is arranged on the wafer angle has: the shared wafer efficient lighting area of electrode pad is little.
The utility model led chip shown in Figure 20, a wafer embedding mouth on the spacer 6 is placed with three wafers, such design can be used for that the synthetic White-light LED chip of three primary colors is made, the White-light LED chip of red wafer complementary color is made and be used for the application of LED display and LCDs backlight in application.

Claims (10)

1. an illuminating led chip includes one or many wafers (3), spacer (6) and heat diffusion member (7), it is characterized in that:
Have wafer embedding mouth on the spacer (6), wafer (3) is embedded in this embedding mouth, and wafer (3) and spacer (6) are attached to the A face of heat diffusion member (7);
Spacer (6) adopts insulating material to make, and is provided with lead pad (1);
On the front wafer surface or sidewall on electrode pad (2) and spacer on corresponding lead pad (1) between conducting connect and adopted that wire bonds connection, scolder are welded to connect, conductive adhesive connects;
Adopted welding or viscose glue to be connected between the A face of wafer (3) and heat diffusion member (7);
Heat diffusion member (7) has adopted copper material or aluminum material or copper aluminum composite material.
2. led chip according to claim 1 is characterized in that: the outer surface positive and partly or entirely spacer (6) of wafer (3) is provided with solid brilliant protective layer (5).
3. led chip according to claim 1, it is characterized in that: at the back side of spacer (6) and wafer (3), along the filleting of wafer (3) with spacer (6), be provided with dielectric film (10), wafer (3) back side has at least area over half to be covered by this dielectric film (10).
4. led chip according to claim 1 is characterized in that: heat diffusion member (7) is a plank frame, and the area of heat diffusion member is greater than five times of all LED chip area sums on this heat diffusion member.
5. led chip according to claim 4 is characterized in that: the B face of heat diffusion member (7) is provided with and bears the high-voltage insulation layer (11) of dc breakdown voltage greater than 500V.
6. led chip according to claim 5 is characterized in that: the high-voltage insulation layer (11) of the B face of heat diffusion member (7), the pellumina that has adopted anode oxidation method directly to grow from the metallic aluminium on heat diffusion member surface.
7. led chip according to claim 4, it is characterized in that: the A face of heat diffusion member (7) is provided with the pellumina that has adopted ceramic insulating film that vapour deposition process generates or anode oxidation method directly to grow from the metallic aluminium on heat diffusion member surface, and this pellumina thickness is not more than 50 μ m.
8. the LED wafer in the illuminating led chip, include substrate (21), LED working lining (18), electrode pad (2), it is characterized in that: be coated with insulating barrier (20) near on the LED working lining sidewall of outer electrode pad, this insulating barrier reaches substrate (21).
9. the LED wafer in the illuminating led chip includes substrate (21), LED working lining (18), electrode pad (2), and it is characterized in that: the sidewall of wafer is provided with electrode pad (2).
10. it is characterized in that according to Claim 8 or 9 described LED wafers: be provided with the ceramic insulating film (23) that adopts vapour deposition process to generate at the back side of wafer.
CN 201020616973 2010-11-10 2010-11-10 LED chip and LED wafer Expired - Fee Related CN201966241U (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
CN 201020616973 CN201966241U (en) 2010-11-10 2010-11-10 LED chip and LED wafer

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227277A (en) * 2013-03-27 2013-07-31 王定锋 Welding-wire-free LED packaging method and LED packaging structure
CN103594613A (en) * 2013-11-30 2014-02-19 广东德力光电有限公司 Forward-installed LED chip without bonding wire and packaging method of forward-installed LED chip
CN106803530A (en) * 2016-11-22 2017-06-06 涂波 A kind of formal dress chip manufacture technique
CN111864031A (en) * 2019-05-06 2020-10-30 上海集耀电子有限公司 LED point light source

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227277A (en) * 2013-03-27 2013-07-31 王定锋 Welding-wire-free LED packaging method and LED packaging structure
CN103594613A (en) * 2013-11-30 2014-02-19 广东德力光电有限公司 Forward-installed LED chip without bonding wire and packaging method of forward-installed LED chip
CN103594613B (en) * 2013-11-30 2016-09-14 广东德力光电有限公司 Forward-installed LED chip without bonding wire and packaging method of forward-installed LED chip
CN106803530A (en) * 2016-11-22 2017-06-06 涂波 A kind of formal dress chip manufacture technique
CN111864031A (en) * 2019-05-06 2020-10-30 上海集耀电子有限公司 LED point light source

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