CN201876704U - Flat knitting machine numerical control system based on FPGA (Field Programmable Gate Array) high-speed communication method - Google Patents
Flat knitting machine numerical control system based on FPGA (Field Programmable Gate Array) high-speed communication method Download PDFInfo
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Abstract
The utility model relates to a flat knitting machine numerical control system based on an FPGA (Field Programmable Gate Array) high-speed communication method, which comprises a management layer with an ARM module as well as a coordination layer and an execution layer with a DSP (Digital Signal Processor) module and an FPGA module. The flat knitting machine numerical control system based on the FPGA high-speed communication method is characterized in that a double-port RAM (Random-Access Memory) high-speed communication module is arranged between the ARM module and the FPGA module, and independent reading/writing effective pins are arranged on the double-port RAM high-speed communication module. The flat knitting machine numerical control system based on the FPGA high-speed communication method has the outstanding essential characteristics that the double-port RAM high-speed communication module is arranged, the independent reading/writing effective pins are arranged on the module so that signals on all layers are matched, signals are prevented from occupying time, and conflict is prevented. In addition, rich logic resources in the FPGA module is adopted, the method of the double-port RAM high-speed communication is realized in a software programming way, and the data communication efficiency between the management layer and the coordination layer is improved, and therefore the weaving efficiency is improved. The control method of the control system cannot only improve the communication velocity, but also has the characteristics of very strong anti-interference performance, generality and the like.
Description
Affiliated technical field
The utility model relates to a kind of straight-bar machines digital control system, relates in particular to a kind of straight-bar machines digital control system based on the FPGA high-speed communication method, improves data communication efficient between administration and supervision authorities and the cooperation layer.
Background technology
Have high-speed data communications between administration and supervision authorities and the cooperation layer in the straight-bar machines digital control system, two-layer between the efficient and the stability of data communication directly influenced the performance of total system.The main at present serial communication mode that adopts is such as RS232/485, CAN etc.And the speed of serial communication can't satisfy the high speed communication demand of straight-bar machines digital control system.
Summary of the invention
The purpose of this utility model is to provide a kind of flat-knitting machine head high speed reverse control method and control system thereof, be provided with dual port RAM high speed communication module, this module is provided with the pin of independent reading and writing, make each layer signal coupling, anti-stop signal holding time is avoided a conflict, and the logical resource that adopts the FPGA inside modules to enrich, realize the method for dual port RAM high speed communication in the mode of software programming, improve data communication efficient between administration and supervision authorities and the cooperation layer, thereby improved weaving efficiency.
The technical scheme that the prior art problem that solves the utility model is adopted is: a kind of straight-bar machines digital control system based on the FPGA high-speed communication method, the administration and supervision authorities that comprise band ARM module, cooperation layer, the execution level of band DSP module and FPGA module, it is characterized in that having dual port RAM high speed communication module between described ARM module and the FPGA module, this module is provided with and independently reads and writes effective pin.Between ARM module and FPGA module, have dual port RAM high speed communication module, and the abundant logical resource of FPGA inside modules, mode with software programming realizes that the method for dual port RAM high speed communication makes each layer signal coupling, anti-stop signal holding time, avoid a conflict, help improving data communication efficient between administration and supervision authorities and the cooperation layer.
As the further of technique scheme improved and replenish, the utility model adopts following technical measures: described dual port RAM high speed communication module comprises four submodules: dual port RAM nucleus module, both-end bus interface matching module, PLL module, bus timing matching module;
Described dual port RAM nucleus module is connected with the ARM module communication;
One end of described both-end bus interface matching module connects ARM module and dual port RAM nucleus module, and the other end connects DSP module and dual port RAM nucleus module;
Described PLL module is connected with the two-port communication of dual port RAM nucleus module;
Described bus timing matching module is connected with the ARM module communication with the DSP module.
The parameter of the systematic parameter of dual port RAM nucleus module, both-end bus interface matching module, bus timing matching module and PLL module can be changed according to system requirements, wherein, the dual port RAM nucleus module is integrated both-end bus interface matching module and bus timing matching module, can work independently, need not to dispose other logical devices again, have higher integrated level and stability.
Described dual port RAM nucleus module is provided with read-write effective pin and clock pin, and communication is connected with the clock pin with the effective pin of read-write respectively after by the sequential coupling for the read-write control signal line in the described dual port RAM nucleus module and data line; Data bus and address bus communication in described both-end bus interface matching module and the ARM module are connected to form signal wire, and this signal wire is connected with the communication of dual port RAM nucleus module.In Quartus II software, the M9K block configuration of FPGA inside modules is become the dual port RAM nucleus module, and the storage space of dual port RAM nucleus module is set to 16K*8bits, promptly data bit width is made as 8, and the address bit wide is made as 14.Data bus on the dual port RAM nucleus module, address bus, read-write control signal line and data useful signal line are connected to both-end bus interface matching module, form signal wire with the dual port RAM coupling.Then, address bus after the coupling and data bus are directly connected on the address bus and data bus interface of dual port RAM; Read-write useful signal after the coupling behind the bus timing matching module, is connected on the respective pins of dual port RAM nucleus module again.
Described both-end bus interface matching module comprises matching module and data bus and the address bus of reading and writing useful signal, described data bus is connected with the three-state buffer communication again with address bus, and the Enable Pin of three-state buffer receives the reading and writing enable signal after coupling respectively.The communication of dual port RAM nucleus module relates to the read-write operation between ARM module, DSP module and the dual port RAM nucleus module, yet three's bus interface has nothing in common with each other, so can not directly dock, needs just can link together after the coupling.With the ARM module is example, and the read-write control signal of ARM module will and also could form the read-write useful signal that mates with the dual port RAM nucleus module after the negate with data useful signal, address chip selection signal.
Three-state buffer helps controlling the signal holding time on the both-end bus interface matching module, prevents bus collision.
Described PLL module is the clock source with the active crystal oscillator of outside 10MHZ, and after frequency multiplication, its frequency of operation is made as 300MHZ.Two ports of dual port RAM nucleus module all are set as same frequency of operation, with unified read-write clock frequency.Clock signal is provided by the PLL module.
Reading enable signal, write enable signal and clock signal according to the dual port RAM nucleus module, described bus timing matching module is to reading enable signal, write enable signal and clock signal is mated on DSP module, the ARM module, make signal and the corresponding signal on the dual port RAM on DSP module, the ARM module synchronous, reach the sequential coupling; When DSP module or ARM module are carried out reading and writing operation, read-write on bus timing matching module timing scan DSP module, the ARM module, when the reading and writing enable signal effective, and when the bus timing matching module captures rising edge clock on DSP, the ARM, make on the dual port RAM corresponding pin effective, at this moment, DSP module or ARM module are finished reading and writing operation; After three clock period, remove reading and writing enable signal and clock signal on DSP module or the ARM module, a reading and writing EO.The control method of this control system has not only improved communication speed, and has characteristics such as very strong anti-interference and versatility.
Described ARM module is S3C2440, and described DSP module is TMS320LF2812, and described FPGA is EP3C10E144C8, and described dual port RAM nucleus module is served as reasons and is embedded in the interior M9K module of FPGA.
The beneficial effect that the utlity model has: be provided with dual port RAM high speed communication module, this module is provided with the pin of independent reading and writing, make each layer signal coupling, anti-stop signal holding time, avoid a conflict, and adopt the abundant logical resource of FPGA inside modules, realize the method for dual port RAM high speed communication in the mode of software programming, improve data communication efficient between administration and supervision authorities and the cooperation layer, thereby improved weaving efficiency.The control method of this control system has not only improved communication speed, and has characteristics such as very strong anti-interference and versatility.
Description of drawings
Fig. 1 is a control system synoptic diagram of the present utility model;
Fig. 2 is the structural representation that administration and supervision authorities and cooperation layer are connected by dual port RAM high speed communication module in the utility model;
Fig. 3 is a dual port RAM nucleus module structural representation in the utility model;
Fig. 4 is a dual port RAM nucleus module internal logic block diagram in the utility model;
Fig. 5 finishes once process flow diagram for the utility model DSP module sends frame data to the ARM module.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is further described.
Embodiment: a kind of straight-bar machines digital control system based on the FPGA high-speed communication method, as depicted in figs. 1 and 2, the administration and supervision authorities that comprise band ARM module, cooperation layer, the execution level of band DSP module and FPGA module, have dual port RAM high speed communication module between ARM module and the FPGA module, this module is provided with and independently reads and writes effective pin.The ARM module is S3C2440, and described DSP module is TMS320LF2812, and described FPGA is EP3C10E144C8, and described dual port RAM nucleus module is served as reasons and is embedded in the interior M9K module of FPGA.Between ARM module and FPGA module, have dual port RAM high speed communication module, and an abundant logical resource of FPGA inside modules, realize that in the mode of software programming the method for dual port RAM high speed communication makes each layer signal coupling.
Dual port RAM high speed communication module comprises four submodules: dual port RAM nucleus module, both-end bus interface matching module, PLL module, bus timing matching module; The dual port RAM nucleus module is connected with the ARM module communication; One end of both-end bus interface matching module connects ARM module and dual port RAM nucleus module, and the other end connects DSP module and dual port RAM nucleus module; The PLL module is connected with the two-port communication of dual port RAM nucleus module; The bus timing matching module is connected with the ARM module communication with the DSP module.
As shown in Figure 3, also be provided with the clock pin on the dual port RAM nucleus module, communication is connected with the clock pin with the effective pin of read-write respectively after by the sequential coupling for the read-write control signal line in the dual port RAM nucleus module and data line; Data bus and address bus communication in both-end bus interface matching module and the ARM module are connected to form signal wire, and this signal wire is connected with the communication of dual port RAM nucleus module.As shown in Figure 4, the inner principle of dual port RAM nucleus module is described.At first, data bus, address bus, read-write control signal line and the data useful signal line with the ARM module is connected to both-end bus interface matching module, the signal wire of formation and dual port RAM nucleus module coupling.Then, address bus after the coupling and data bus are directly connected on the address bus and data bus interface of dual port RAM nucleus module; Read-write useful signal after the coupling after the sequential coupling, is connected on the respective pins of dual port RAM core again.
Both-end bus interface matching module comprises matching module and data bus and the address bus of reading and writing useful signal, described data bus is connected with the three-state buffer communication again with address bus, and the Enable Pin of three-state buffer receives the reading and writing enable signal after coupling respectively.
The PLL module is the clock source with the active crystal oscillator of outside 10MHZ, and after frequency multiplication, its frequency of operation is made as 300MHZ.Two ports of dual port RAM nucleus module all are set as same frequency of operation, with unified read-write clock frequency.Clock signal is provided by the PLL module.
Reading enable signal, write enable signal and clock signal according to the dual port RAM nucleus module, described bus timing matching module is to reading enable signal, write enable signal and clock signal is mated on DSP module, the ARM module, make signal and the corresponding signal on the dual port RAM on DSP module, the ARM module synchronous, reach the sequential coupling; When DSP module or ARM module are carried out reading and writing operation, read-write on bus timing matching module timing scan DSP module, the ARM module, when the reading and writing enable signal effective, and when the bus timing matching module captures rising edge clock on DSP, the ARM, make on the dual port RAM corresponding pin effective, at this moment, DSP module or ARM module are finished reading and writing operation; After three clock period, remove reading and writing enable signal and clock signal on DSP module or the ARM module, a reading and writing EO.
Administration and supervision authorities are the management system that core CPU makes up with ARM.Be responsible on the one hand the local information management: the management of flower type, file management, parameter management, test and management are gathered, handle in a large number from the real time data management of cooperation layer etc. simultaneously; Be responsible on the other hand carrying out data interaction, realize the management of production data, thereby finish the optimum management of integration objective with enterprise information management.Cooperation layer is the cooperation layer system that core CPU makes up with DSP+FPGA.This grade mainly explained and carried out the instruction that administration and supervision authorities send and monitor the operation conditions of each execution level subsystem feedback.Cooperation layer resolves to concrete action data with instruction and the pattern data that administration and supervision authorities send, and sends to each execution level subsystem; Important parameter in the responsible simultaneously reception straight-bar machines operational process and various abnormal signal, guard signal etc., and send administration and supervision authorities to.Execution level is the executive system that core CPU makes up with DSP.This system mainly is responsible for receiving the instruction that sends from cooperation layer, drives the execution unit action by logical device and power amplification, and utilizes sensor that the running-active status of part execution unit is fed back to the cooperation layer system.
Bus timing matching module (VHDL) program:
if(enw_in?or?enr_in)＝’1’then
if?clk_in’event?and?clk_in＝’0’then
if?flag＝0?then
flag:＝1；
elsif?flag＝1?then
cnt:＝cnt+1；
if?cnt＝3?then
cnt:＝0；
flag:＝2；
end?if；
end?if；
end?if；
if?flag＝1then
if?enw_in＝’1’then
enw_out＜＝’1’；
end?if；
if?enr_in＝’1’then
enr_out＜＝’1’；
end?if；
clk_out＜＝clk_in；
else
clk_out＜＝’0’；enw_out＜＝’0’；
enr_out＜＝’0’；
end?if；
else
flag:＝0；cnt:＝0；clk_out＜＝’0’；
enw_out＜＝’0’；enr_out＜＝’0’；
end?if；
Wherein, self-defining data frame format: interrupt identification territory+control domain+data field.The interrupt identification territory is the interrupt identification of data transmission, and control domain is a transmission parameters information, and data field is the data of transmission.
As shown in Figure 5, when sending data, the classification information that twoport ARM nucleus module at first will send data is filled into the control domain on the twoport ARM nucleus module, and the data that will send are filled into the data field on the twoport ARM nucleus module then, and corresponding interrupt flag bit is set at last.
When receiving data, DSP module take over party is the corresponding interrupt flag bit of scanning constantly, then begins to receive data when the interruption sign is effective.When beginning to receive data, at first, read and judge control domain information; Then, read corresponding transmission data; Remove interrupt flag bit at last, finish the process that once receives data.
Claims (6)
1. straight-bar machines digital control system based on the FPGA high-speed communication method, the administration and supervision authorities that comprise band ARM module, cooperation layer, the execution level of band DSP module and FPGA module, it is characterized in that having dual port RAM high speed communication module between described ARM module and the FPGA module, this module is provided with and independently reads and writes effective pin.
2. a kind of straight-bar machines digital control system based on the FPGA high-speed communication method according to claim 1 is characterized in that described dual port RAM high speed communication module comprises four submodules: dual port RAM nucleus module, both-end bus interface matching module, PLL module, bus timing matching module;
Described dual port RAM nucleus module is connected with the ARM module communication;
One end of described both-end bus interface matching module connects ARM module and dual port RAM nucleus module, and the other end connects DSP module and dual port RAM nucleus module;
Described PLL module is connected with the two-port communication of dual port RAM nucleus module;
Described bus timing matching module is connected with the ARM module communication with the DSP module.
3. a kind of straight-bar machines digital control system according to claim 2 based on the FPGA high-speed communication method, it is characterized in that also being provided with the clock pin on the described dual port RAM nucleus module, communication is connected with the clock pin with the effective pin of read-write respectively after by the sequential coupling for the read-write control signal line in the described dual port RAM nucleus module and data line; Data bus and address bus communication in described both-end bus interface matching module and the ARM module are connected to form signal wire, and this signal wire is connected with the communication of dual port RAM nucleus module.
4. according to claim 2 or 3 described a kind of straight-bar machines digital control systems based on the FPGA high-speed communication method, it is characterized in that described both-end bus interface matching module comprises matching module and data bus and the address bus of reading and writing useful signal, described data bus is connected with the three-state buffer communication again with address bus, and the Enable Pin of three-state buffer receives the reading and writing enable signal after coupling respectively.
5. a kind of straight-bar machines digital control system based on the FPGA high-speed communication method according to claim 4 is characterized in that described PLL module is the clock source with the active crystal oscillator of outside 10MHZ, and its frequency parameter is a frequency parameter, and its frequency of operation is made as 300MHZ.
6. a kind of straight-bar machines digital control system according to claim 5 based on the FPGA high-speed communication method, it is characterized in that described ARM module is S3C2440, described DSP module is TMS320LF2812, described FPGA is EP3C10E144C8, and described dual port RAM nucleus module is served as reasons and is embedded in the interior M9K module of FPGA.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102634924A (en) * | 2012-04-24 | 2012-08-15 | 浙江理工大学 | Fully-mechanized circular knitting machine control system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102634924A (en) * | 2012-04-24 | 2012-08-15 | 浙江理工大学 | Fully-mechanized circular knitting machine control system |
| CN102634924B (en) * | 2012-04-24 | 2014-03-26 | 浙江理工大学 | Fully-mechanized circular knitting machine control system |
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