CN201845764U - Lead frame packaged by flip-chip small outline integrated circuit and packaging structure thereof - Google Patents
Lead frame packaged by flip-chip small outline integrated circuit and packaging structure thereof Download PDFInfo
- Publication number
- CN201845764U CN201845764U CN2010202695021U CN201020269502U CN201845764U CN 201845764 U CN201845764 U CN 201845764U CN 2010202695021 U CN2010202695021 U CN 2010202695021U CN 201020269502 U CN201020269502 U CN 201020269502U CN 201845764 U CN201845764 U CN 201845764U
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- lead frame
- chip
- area
- fcsoic
- pin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The utility model provides a lead frame packaged by a flip-chip small outline integrated circuit (FCSOIC), belonging to the technical field of chip package. The FCSOIC lead frame comprises a first area part corresponding to the position of a packaged chip, and a second area part outside the first area, wherein an inner pin of the lead frame extends into the first area part from the second area part roughly in the same plane. An FCSOIC lead frame array comprises a plurality of FCSOIC lead frames arranged in rows and lines. The FCSOIC packaging structure comprises an FCSOIC lead frame, the packaged chip and a packaging body, wherein the chip is directly in flip-chip welding on the lead frame through a flip chip bumping point on the inner pin of the lead frame. The FCSOIC lead frame has the characteristic of being low in cost, high in packaging reliability, simple in packaging procedure, and suitable for the package of chip with large output current.
Description
Technical field
The utility model belongs to the chip encapsulation technology field, be specifically related to a kind of small outline integrated circuit encapsulation (Small Outline Integrated Circuit Package, SOIC) lead frame, relate in particular to the encapsulation of upside-down mounting small outline integrated circuit (Flipchip Small Outline Integrated Circuit Package, lead frame FCSOIC) and encapsulating structure thereof.
Background technology
Encapsulation is very important step in the electronic device manufacture process, by encapsulation process, various chips (chip die) direct circuit can be drawn, so that be electrically connected with external circuit.To various chip, the packing forms that can select it to be suitable for mutually usually.
SOIC (Small Outline Integrated Circuit Package, small outline integrated circuit encapsulation) packing forms is another statement of SOP (Small Outline Package, little outline packages) packing forms.In most encapsulating structures, include the lead frame of metal " skeleton " form that is used for directly being welded to connect chip, lead frame can provide machinery support, and can realize being connected of chip and external circuit for chip.Different packing forms correspondences have different lead frame structure.
Figure 1 shows that the lead frame structure schematic diagram of the SOIC of prior art.Lead frame 100 embodiment illustrated in fig. 1 comprises island (PAD) 120 and is arranged at island 120 8 interior pins 111,112,113,114,115,116,117,118 all around that island 120 is down beaten heavy formation by beating recessed technology.Island 120 zones are used to place the chip that will encapsulate, and carry out gold wire bonding by routing technology then between chip and interior pin and connect; Adopt the plastic-sealed body encapsulated moulding to form integrated circuit (IC) device after further finishing the subsequent technique process.
Simultaneously, along with development of electronic technology, increasing IC device is required to export big electric current with low-voltage, and still, big electric current is responsive unusually to interconnection resistance, and interconnection resistance is high more, and it is big more to generate heat, and loss obviously increases.Therefore, for this IC device, the interconnection resistance problem is more outstanding.Wherein, circuit package is to cause a major reason of high interconnection resistance, for example, the gold wire bonding of the SOIC packing forms of lead frame shown in Figure 1, may bring bigger interconnection resistance, for reducing this part interconnection resistance, obviously be arm and a leg from the angle of overstriking spun gold.Therefore, when adopting SOIC lead frame shown in Figure 1 that big output current chip is carried out the SOIC encapsulation, can not satisfy the requirement of high-termal conductivity, big electric current low cost, low inductive effect.
In view of this, the utility model has proposed the lead frame of a kind of SOIC of new structure in conjunction with SOIC encapsulation technology and upside-down mounting (Flipchip) sealing packing technique.
The utility model content
The technical problems to be solved in the utility model is to satisfy the big output current of chip and the requirement of low packaging cost.
For solving above technical problem, according to an aspect of the present utility model, a kind of lead frame of upside-down mounting small outline integrated circuit encapsulation is provided, it comprises first area part corresponding with packed chip placement location and the second area part outside the first area, wherein, the interior pin of described lead frame is partly extended among the part of described first area by described second area in same plane roughly; A plurality of described interior pins are set to strip structure and cross arrangement forms the interdigital structure.
According to lead frame provided by the utility model, wherein, described interior pin being provided with in described first area corresponding to described bonding pads position.
Interior pin among the part of described first area be provided be used for directly being welded to connect described chip more than one or one plant the ball point.
As the preferred technique scheme.The width of the interior pin of described strip structure is greater than the diameter of planting ball point placed on it.
According to lead frame provided by the utility model, wherein, described lead frame also comprises a plurality of outer pin that is arranged on described second area part, and wherein, the described outer pin of part is connected in a plurality of interior pins simultaneously.
According to another aspect of the present utility model, the utility model provides a kind of array of leadframes of upside-down mounting small outline integrated circuit encapsulation, comprises a plurality of the above arbitrary lead frame that reach of arranging by row and column.
According to one side more of the present utility model, the utility model provides a kind of encapsulating structure of upside-down mounting small outline integrated circuit encapsulation, and it comprises:
Arbitrary lead frame that the above reaches;
Packaged chip; And
Structure matching is in the packaging body of described lead frame;
Wherein, described chip is put direct flip chip bonding and is connected on the described lead frame by the ball of planting on the interior pin of described lead frame.
According to encapsulating structure provided by the utility model, wherein, the output current of described chip is about 10 amperes to 20 amperes.
Technique effect of the present utility model is, this utility model FCSOIC lead frame do not need gold wire bonding, do not need to beat spill becomes island, and therefore, cost is low, the package reliability height, and packaging process is simple, and is applicable to the encapsulation of the chip of big output current.
Description of drawings
Fig. 1 is the lead frame structure schematic diagram of the SOIC of prior art;
Fig. 2 is the structural representation of the FCSOIC lead frame that provided according to the utility model embodiment;
Fig. 3 is the A-A cross section structure schematic diagram behind the FCSOIC lead frame upside-down mounting welding chip shown in Figure 2;
Fig. 4 is the structural representation of the FCSOIC lead frame that provided according to the another embodiment of the utility model.
Embodiment
What introduce below is a plurality of some in may embodiment of the present utility model, aims to provide basic understanding of the present utility model, is not intended to confirm key of the present utility model or conclusive key element or limits claimed scope.In the accompanying drawings, for the sake of clarity, might amplify the thickness of layer or the area in zone, but should not be considered to the proportionate relationship that strictness has reflected physical dimension as schematic diagram.In the accompanying drawing, identical label refers to identical structure division, therefore will omit description of them.
The structural representation of the FCSOIC lead frame that is provided according to the utility model embodiment is provided.As shown in Figure 2, in this embodiment, FCSOIC lead frame 200 comprises 8 outer pins and 9 interior pins, but, the pin number of FCSOIC lead frame is not limited by the utility model embodiment, and those skilled in the art can require to select the lead frame of the pin of concrete quantity according to the circuit function of packaged chip.FCSOIC lead frame 200 is used for upside-down mounting welding chip (chip die), wherein the zone of frame of broken lines 260 lead frame that is this embodiment is welded to connect the position that chip is placed behind the chip, in this utility model, frame of broken lines 260 zone definitions that we place packed chip with shown in Figure 2 being used to are the first area part of FCSOIC lead frame, and the other parts of the lead frame outside the part of first area we be defined as second area difference; Therefore, in this embodiment, frame of broken lines 260 becomes the basic line of demarcation of first area part and second area part.The shape of first area and size can be determined according to packaged chip.Than the SOIC lead frame of prior art shown in Figure 1, packed chip is to be positioned over the island zone, and interior pin is to place fully outside the island zone, therefore, can not directly be welded to connect between chip and the lead frame.
Continue as shown in Figure 2,9 interior pins 221,222,223,224,2251,2252,226,227,228 of FCSOIC lead frame 200 are divided into two rows and arrange side by side.Wherein, interior pin extends among the first area by the second area of FCSOIC lead frame, need to prove, part and the part in first area of interior pin in second area is on same plane roughly, therefore, the FCSOIC lead frame of this structure is not need to form to beat recessed island, than the manufacturing of traditional SOIC lead frame, saved and beaten recessed step, thus the manufacturing cost that can save the FCSOIC lead frame.And the ball point of planting in the structure of its opposed flattened also helps on the pin well contacts with interior pin with chip.
Continuation is shown in 2, and FCSOIC lead frame 200 also comprises a plurality of outer pin 211,212,213,214,215,216,217 and 218 of corresponding with interior pin respectively connection, and is same, and outer pin is divided into two rows and arranges side by side.Wherein, the interior pin that is connected with outer pin 211,212,215 is set to strip, this is that electricity exports on the same interior pin because a plurality of pads (Pad) of the chip on the first area need simultaneously, when adopting traditional spun gold welding, spun gold is tiny relatively, and many spun golds can be welded on the same interior pin simultaneously; And after adopting the upside-down mounting welding, must increase the area of interior pin and make the bonding pads that will connect on its shape energy correspondence.In this embodiment, interior pin 221,222,2251,2252 is set to strip, a plurality of ball points (circle as shown in Figure 2) of planting can be set respectively on the interior pin 221,222,2251,2252, plant the ball point and only be provided with one on the pin 223,224,226,227 and 228 in other; The width of interior pin 221,222,2251,2252 (width dimensions of above-below direction among the figure) is greater than the diameter of planting ball point.Need to prove that the concrete quantity and the shape of pin are not limited by the utility model embodiment in the strip, those skilled in the art can select design according to the distribution of concrete bonding pads, for example, all interior pin can be designed to elongate in shape.
Continuation is shown in 2, and pin 221,222,2251,2252 cross arrangements form the interdigital structure in the strip.Pin 2251,2252 is connected with an outer pin 215 simultaneously in the strip, and therefore, the pad that is welded to connect with interior pin 2251,2252 on chip electricity simultaneously exports outer pin 215 to.
In addition, FCSOIC lead frame 200 also comprises two company's muscle 250 that are arranged on second area, and the production that it is convenient in encapsulation process it is to be noted, be the welding performance of planting ball point on the pin in guaranteeing, the anti-oxidation measure when transportation need be carried out in the top layer of FCSOIC lead frame 200.
Figure 3 shows that the A-A cross section structure schematic diagram behind the FCSOIC lead frame upside-down mounting welding chip shown in Figure 2.As shown in Figure 3, interior pin 222,226 and outer pin 212,216 are on same substantially plane.Interior pin 222,226 is provided with the pad corresponding to chip 500 (being the contact position of planting ball point 400 and chip 500 among Fig. 3) position in (zone under the chip 500) in the first area, and being connected in can making like this between pin and the chip is more simple and convenient; The interior Pin locations of lead frame can design neatly according to the position of chip 500 pads.A plurality of ball points 400 of planting are set on the interior pin 222 of strip, are provided with one on the interior pin 226 and plant ball point 400, the pad of chip 500 is put 400 correspondences and directly is welded to connect on lead frame by planting ball.Therefore, can save spun gold and bonding technology step thereof, cost lowers greatly.And, the form resistance that ball point directly is welded to connect is less, contact area is big to plant, therefore can conducting bigger electric current and generate heat little, the encapsulation of this lead frame is born 5-10 that encapsulation that electric current can reach the encapsulation of the thick spun gold of corresponding employing bears electric current doubly, thereby can satisfy the encapsulation requirement of the chip of big output current.Therefore, chip 500 can be the chip of big output current, and preferably, the output current scope of chip is about 10 amperes to 20 amperes, is in particular 12 amperes.In addition, plant ball point 400 and can adopt terne metal, sn-ag alloy or SAC alloy material, preferably, adopt welding contact resistance materials with smaller.
The structural representation of the FCSOIC lead frame that is provided according to the another embodiment of the utility model is provided.As shown in Figure 4, in this embodiment, FCSOIC lead frame 300 comprises 8 outer pins and 8 interior pins, but, the pin number of FCSOIC lead frame is not limited by the utility model embodiment, and those skilled in the art can require to select the lead frame of the pin of concrete quantity according to the circuit function of packaged chip.FCSOIC lead frame 300 is used for upside-down mounting welding chip (chip die), wherein the zone of frame of broken lines 360 lead frame that is this embodiment is welded to connect the position that chip is placed behind the chip, equally, frame of broken lines 360 zone definitions that we place packed chip with shown in Figure 4 being used to are the first area part of FCSOIC lead frame, and the other parts of the lead frame outside the part of first area we be defined as the second area part; Therefore, in this embodiment, frame of broken lines 360 becomes the basic line of demarcation of first area part and second area part.The shape of first area part and size can design according to packaged chip.
Continuation is arranged around 8 interior pins 321,322,323,324,325,326,327,328 of FCSOIC lead frame 300 shown in 4.Wherein, interior pin extends among the part of first area by the second area of FCSOIC lead frame, need to prove, part and the part in first area of interior pin in second area is on same plane roughly, therefore, the FCSOIC lead frame of this structure is not need to form to beat recessed island, than the manufacturing of traditional SOIC lead frame, saved and beaten recessed step, thus the manufacturing cost that can save the FCSOIC lead frame.And the ball point of planting in the structure of its opposed flattened also helps on the pin well contacts with interior pin with chip.Than FCSOIC lead frame 200 shown in Figure 2, the shape of pin in its main distinction is, at this embodiment, interior pin 321,322,323,324,325,326,327,328 inwardly is extended into strip by the first area.Equally, interior pin 321,322,323,324,325,326,327,328 can distribute and one or more ball points of planting is set to be used for upside-down mounting welding fixed chip.
Continuation is shown in 4, and FCSOIC lead frame 300 also comprises a plurality of outer pin 311,312,313,314,315,316,317 and 318 of corresponding with interior pin respectively connection, and is same, and outer pin is divided into two rows and arranges side by side.Wherein, FCSOIC lead frame 300 also comprises two company's muscle 350 that are arranged on second area.FCSOIC lead frame 300 has adopted the essentially identical design concept of FCSOIC lead frame 200 shown in Figure 2 substantially, and other is this tired no longer one by one stating.
From the above, Fig. 2 and FCSOIC lead frame shown in Figure 4 do not need gold wire bonding, therefore packaging cost is low, operation is simple, and its encapsulation is born 5-10 that encapsulation that electric current can reach the thick spun gold encapsulation of corresponding employing bears electric current doubly, can be applicable to the encapsulation requirement of big output current chip.
The utility model provides the FCSOIC array of leadframes of being made up of a plurality of Fig. 2 or FCSOIC lead frame shown in Figure 4 simultaneously.In the actual package process, be to the encapsulation formation simultaneously side by side of a plurality of chips.Therefore, before encapsulation, the FCSOIC lead frame is not unit independently, but the form that a plurality of Fig. 2 or FCSOIC lead frame shown in Figure 4 are arranged by multiple lines and multiple rows is formed the FCSOIC array of leadframes, helps efficient encapsulation like this.
The utility model further provides a kind of encapsulating structure, this encapsulating structure be by the above and lead frame, packaged chip and structure matching in the packaging body (not shown among Fig. 3) of described lead frame; Chip is put direct flip chip bonding and is connected on the lead frame by the ball of planting on the interior pin of lead frame.Wherein, packaged chip can be the chip of big output current, and preferably, the output current scope of chip is in particular 12 amperes for being about 10 amperes to 20 amperes.The encapsulation of this encapsulating structure is born 5-10 that encapsulation that electric current can reach the encapsulation of the thick spun gold of corresponding employing bears electric current doubly.
Above example has mainly illustrated FCSOIC lead frame of the present utility model, array of leadframes and encapsulating structure.Although only some of them execution mode of the present utility model is described, those of ordinary skills should understand, and the utility model can be in not departing from its purport and scope be implemented with many other forms.Therefore, example of being showed and execution mode are regarded as illustrative and not restrictive, and under situation about not breaking away from as defined the utility model spirit of appended each claim and scope, the utility model may be contained various modifications and replacement.
Claims (8)
1. the lead frame of upside-down mounting small outline integrated circuit encapsulation, comprise first area part corresponding and the second area part outside the first area with packed chip placement location, it is characterized in that the interior pin of described lead frame is partly extended among the part of described first area by described second area in same plane; A plurality of described interior pins are set to strip structure and cross arrangement forms the interdigital structure.
2. lead frame as claimed in claim 1 is characterized in that, described interior pin being provided with corresponding to described bonding pads position in described first area.
3. lead frame as claimed in claim 1 or 2 is characterized in that, the interior pin among the part of described first area be provided be used for directly being welded to connect described chip more than one or one plant the ball point.
4. lead frame as claimed in claim 1 is characterized in that, the width of the interior pin of described strip structure is greater than the diameter of planting ball point placed on it.
5. lead frame as claimed in claim 1 is characterized in that, described lead frame also comprises a plurality of outer pin that is arranged on described second area part, and wherein, the described outer pin of part is connected in a plurality of interior pins simultaneously.
6. the array of leadframes of upside-down mounting small outline integrated circuit encapsulation is characterized in that, comprise a plurality of by row and column arrange as each described lead frame in the claim 1 to 5.
7. the encapsulating structure of a upside-down mounting small outline integrated circuit encapsulation is characterized in that, comprising:
As each described lead frame in the claim 1 to 5;
Packaged chip; And
Structure matching is in the packaging body of described lead frame;
Wherein, described chip is put direct flip chip bonding and is connected on the described lead frame by the ball of planting on the interior pin of described lead frame.
8. encapsulating structure as claimed in claim 7 is characterized in that, the output current of described chip is about 10 amperes to 20 amperes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202695021U CN201845764U (en) | 2010-07-12 | 2010-07-12 | Lead frame packaged by flip-chip small outline integrated circuit and packaging structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202695021U CN201845764U (en) | 2010-07-12 | 2010-07-12 | Lead frame packaged by flip-chip small outline integrated circuit and packaging structure thereof |
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| Publication Number | Publication Date |
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| CN201845764U true CN201845764U (en) | 2011-05-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010202695021U Expired - Lifetime CN201845764U (en) | 2010-07-12 | 2010-07-12 | Lead frame packaged by flip-chip small outline integrated circuit and packaging structure thereof |
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| CN (1) | CN201845764U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332440A (en) * | 2010-07-12 | 2012-01-25 | 无锡华润安盛科技有限公司 | Inverted lead frame and packaging structure thereof |
-
2010
- 2010-07-12 CN CN2010202695021U patent/CN201845764U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332440A (en) * | 2010-07-12 | 2012-01-25 | 无锡华润安盛科技有限公司 | Inverted lead frame and packaging structure thereof |
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| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110525 |
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| CX01 | Expiry of patent term |