CN201749849U - Planar light-emitting diode (LED) structure - Google Patents
Planar light-emitting diode (LED) structure Download PDFInfo
- Publication number
- CN201749849U CN201749849U CN2010202967153U CN201020296715U CN201749849U CN 201749849 U CN201749849 U CN 201749849U CN 2010202967153 U CN2010202967153 U CN 2010202967153U CN 201020296715 U CN201020296715 U CN 201020296715U CN 201749849 U CN201749849 U CN 201749849U
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- Prior art keywords
- led
- epitaxial loayer
- type epitaxial
- electrode
- planar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Abstract
The utility model discloses a planar light-emitting diode (LED) structure. The planar LED structure comprises a metal substrate and a fluorescent cover, wherein a support layer is fixed on the upper surface of the metal substrate along the periphery; the fluorescent cover and the support layer are matched and fixedly connected with each other so as to form a cavity; more than one LED naked chips are arranged in the cavity; the bottom surface of each LED naked chip is fixedly connected with the upper surface of the metal substrate; an insulating layer is fixed on the upper surface of the metal substrate; a metal layer is fixed on the insulating layer and is electrically connected with the electrode of each LED naked chip; and the excitation wavelength of fluorescent powder in the fluorescent cover is the same as the luminescence wavelength of the LED naked chip. The planar LED structure has good radiating effect. Even though one or more LED naked chips fail, the luminescence of the entire planar LED is not affected, the process of the planar LED is simplified, the service life of the planar LED is prolonged and the cost of the planar LED is lowered.
Description
Technical field
The utility model relates to a kind of planar LED structure.
Background technology
Industrial, one of approach that produces light at present is to utilize fluorescent material to cover blue-ray LED to form single LEDs, and wafers such as sapphire, aluminium nitride are used as growth substrates growth LED.The heat conductivility of the dielectric substrate of the LED of this structure is low, and the led chip thermal resistance is bigger, and two electrodes of the LED of this structure are in the same side of epitaxial loayer, and it is congested to face electric current, and CURRENT DISTRIBUTION is inhomogeneous and can not make full use of the problem of luminescent layer.Single LEDs luminous efficiency is not high enough, can not realize large area light emitting preferably.Therefore, great power LED is badly in need of solving following problems: (1) radiating efficiency is low; (2) luminous efficiency and light extraction efficiency still need improve; (3) cost height.These problems depend on the encapsulating structure of LED structure and LED.
The utility model content
Technical problem to be solved in the utility model provides a kind of planar LED structure of good heat dissipation effect.
The technical scheme in the invention for solving the technical problem is: planar LED structure described in the utility model comprises metallic substrates and fluorescence cover, the upper surface of described metallic substrates is fixed with supporting layer along its periphery, and described fluorescence cover and described supporting layer are complementary and are mutually permanently connected and form a cavity; In described cavity, contain an above LED bare chip, fixedly connected with the upper surface of described metallic substrates in the bottom surface of each described LED bare chip, the upper surface of described metallic substrates is fixed with insulating barrier, be fixed with metal level on the described insulating barrier, be electrically connected between the electrode of described metal level and each described LED bare chip, the excitation wavelength of the fluorescent material in the described fluorescence cover is identical with the emission wavelength of described LED bare chip.
Further, LED bare chip described in the utility model is a light emitting diode (LED) chip with vertical structure.
Further, LED bare chip described in the utility model comprises first conductive buffer layer, N type epitaxial loayer electrode, N type epitaxial loayer, multiple quantum well layer, P type epitaxial loayer and P type epitaxial loayer electrode from bottom to top successively, and described P type epitaxial loayer electrode is electrically connected with described metal level by lead.
Further, LED bare chip described in the utility model comprises second conductive buffer layer, P type epitaxial loayer electrode, P type epitaxial loayer, multiple quantum well layer, N type epitaxial loayer and N type epitaxial loayer electrode from bottom to top successively, and described N type epitaxial loayer electrode is electrically connected with described metal level by lead.
Further, lead described in the utility model is gold thread, aluminum steel or copper cash.
Further, metal level described in the utility model is aluminium foil, Copper Foil or goldleaf.
Compared with prior art, the beneficial effects of the utility model are: adopting metallic substrates both to can be used as electrode also can be by its large tracts of land heat radiation, has solved that the heat conductivility of dielectric substrate is low in the prior art, the led chip thermal resistance is big, electrode causes the congested skewness of electric current in the same side of epitaxial loayer, can not make full use of the problem of luminescent layer.The fluorescence cover that the utility model adopted can be the lampshade that fluorescent glass, fluorescence epoxy resin etc. have fluorescence property, more than one LED bare chip forms parallel circuits each other, fluorescent material in the common fluorescence excitation cover, even some like this or several LED bare chips break down, it is luminous also not influence whole planar LED, simplified planar LED technology, increased planar LED useful life, reduced the cost of planar LED.
Description of drawings
Fig. 1 is the schematic diagram of the planar LED structure of the utility model embodiment 1.
Fig. 2 is that the A-A of Fig. 1 is to schematic diagram.
Fig. 3 is the schematic diagram of the planar LED structure of the utility model embodiment 2.
Embodiment
As shown in Figure 1 to Figure 3, planar LED structure of the present utility model comprises metallic substrates 2 and fluorescence cover 3, the upper surface of metallic substrates 2 is fixed with plastic plate or other objects that support strength is arranged as supporting layer 6 along its periphery, and the fluorescent glass of evenly smearing fluorescent material is complementary as fluorescence cover 3 and supporting layer 6 and is mutually permanently connected and forms a cavity.In this cavity, contain an above LED bare chip 1.LED bare chip 1 of the present utility model can be light emitting diode (LED) chip with vertical structure.
In embodiment illustrated in figures 1 and 2, the planar LED structure comprises four LED bare chips 1.As shown in Figure 2, LED bare chip 1 is a light emitting diode (LED) chip with vertical structure, comprise first conductive buffer layer 10, N type epitaxial loayer electrode 11, N type epitaxial loayer 12, multiple quantum well layer 13, P type epitaxial loayer 14 and P type epitaxial loayer electrode 15 from bottom to top successively, P type epitaxial loayer electrode 15 is electrically connected with described metal level 5 by lead.
As a kind of execution mode of the present utility model, can be with the AlTiPtAu hybrid metal layer of 5 μ m as first conductive buffer layer 10, the 100nm Ti/Au alloy-layer of electron beam evaporation or magnetron sputtering growth is as N type epitaxial loayer electrode 11, MOCVD, PLD, the 300nmN type ZnO layer of MBE or magnetron sputtering growth is as N type epitaxial loayer 12, MOCVD, PLD, the 10nmZnMgO/ZnO layer in 10 cycles of MBE or magnetron sputtering growth is as multiple quantum well layer 13, MOCVD, PLD, the 300nmP type ZnO layer of MBE or magnetron sputtering growth as P type epitaxial loayer 14 and with the 100nmNi/Au alloy-layer of electron beam evaporation or magnetron sputtering growth as P type epitaxial loayer electrode 15.
The effect of first conductive buffer layer 10 is conduction connection N type epitaxial loayer electrodes 11 and is the support of whole LED bare chip 1.N type epitaxial loayer electrode 11 is the N utmost point electrodes by the LED that better ohmic contact of having of specific pattern and low specific contact resistivity rate are arranged of lift-off technology formation.P type epitaxial loayer electrode 15 is the P utmost point electrodes by the LED that better ohmic contact of having of specific pattern and low specific contact resistivity rate are arranged of lift-off technology formation.Can use Al metallic plate or other metallic plates or other alloy sheets as metallic substrates 2, metallic substrates 2 both can be used as cathode contact, and to be connected electric action with first conductive buffer layer 10 also be fin.The upper surface fixed insulation adhesive tape of metallic substrates 2 or other megohmite insulants are fixed with Copper Foil or aluminium foil or goldleaf as metal level 5 as insulating barrier 4 on the insulating barrier 4, the effect of insulating barrier 4 is separately metallic substrates 2 and metal levels 5 of insulation.Metal level 5 is to be connected with P type epitaxial loayer electrode 15 as the anode contact, and P type epitaxial loayer electrode 15 is welded on the metal level 5 as metal wire 7 by gold thread or aluminum steel or copper cash.
The excitation wavelength of fluorescent material is identical with the emission wavelength of LED bare chip 1 in the fluorescence cover 3 of the present utility model, and supporting layer 6 is played a supporting role and with in the cavity do not contacted except any other part of metallic substrates 2 and fluorescence cover 3.Be electrically connected respectively between metal level 5 and each LED bare chip 1, be that metal level 5 links together as total anode contact, metallic substrates 2 is as cathode contact, outside corresponding both positive and negative polarity inserts DC power supply, make and form parallel circuits between each LED bare chip 1, can improve luminous efficiency like this, even one, two or three LED bare chips 1 are broken down, it is luminous also not influence whole planar LED.
In another kind of planar LED structure shown in Figure 3, contain four LED bare chips 1, these LED bare chips 1 are light emitting diode (LED) chip with vertical structure, comprise second conductive buffer layer 16, P type epitaxial loayer electrode 15, P type epitaxial loayer 14, multiple quantum well layer 13, N type epitaxial loayer 12 and N type epitaxial loayer electrode 11 from bottom to top successively, N type epitaxial loayer electrode 11 is electrically connected with metal level 5 by lead.
The utility model can use the KrNiPtAu hybrid metal layer of 5 μ m as second conductive buffer layer 16, the 100nm Ni/Au alloy-layer of electron beam evaporation or magnetron sputtering growth is as P type epitaxial loayer electrode 15, MOCVD, PLD, the 300nmP type ZnO layer of MBE or magnetron sputtering growth is as P type epitaxial loayer 14, MOCVD, PLD, the 10nmZnMgO/ZnO layer in 10 cycles of MBE or magnetron sputtering growth is as multiple quantum well layer 13, MOCVD, PLD, the 300nmN type ZnO layer of MBE or magnetron sputtering growth is as N type epitaxial loayer 12, and the 100nmTi/Au alloy-layer of electron beam evaporation or magnetron sputtering growth is as N type epitaxial loayer electrode 11.
The effect of second conductive buffer layer 16 is conduction connection P type epitaxial loayer electrodes 15 and is the support of whole LED bare chip 1.N type epitaxial loayer electrode 11 is the N utmost point electrodes by the LED that better ohmic contact of having of specific pattern and low specific contact resistivity rate are arranged of lift-off technology formation.P type epitaxial loayer electrode 15 is the P utmost point electrodes by the LED that better ohmic contact of having of specific pattern and low specific contact resistivity rate are arranged of lift-off technology formation.Al metallic plate or other metallic plates or other alloy sheets are metallic substrates 2, and both being connected electric action as the anode contact with second conductive buffer layer 16 also is fin.The upper surface fixed insulation adhesive tape of metallic substrates 2 or other megohmite insulants are fixed with Copper Foil or aluminium foil or goldleaf as metal level 5 as insulating barrier 4 on the insulating barrier 4, the effect of insulating barrier 4 is separately metallic substrates 2 and metal levels 5 of insulation.Metal level 5 is to be connected with N type epitaxial loayer electrode 11 as cathode contact, and N type epitaxial loayer electrode 11 is welded on the metal level 5 as metal wire 7 by gold thread or aluminum steel or copper cash.
As shown in Figure 3, the upper surface of metallic substrates 2 is fixed with plastic plate or other objects that support strength is arranged as supporting layer 6 along its periphery, the fluorescent glass of evenly smearing fluorescent material is complementary as fluorescence cover 3 and supporting layer 6 and is mutually permanently connected and forms a cavity, the excitation wavelength of fluorescent material is identical with the emission wavelength of LED bare chip 1 in the fluorescence cover 3, and supporting layer 6 is played a supporting role and with in the cavity do not contacted except any other part of metallic substrates 2 and fluorescence cover 3.Be electrically connected respectively between metal level 5 and each LED bare chip 1, be that metal level 5 links together as total cathode contact, metallic substrates 2 is as the anode contact, outside corresponding both positive and negative polarity inserts DC power supply, make and form parallel circuits between each LED bare chip 1, can improve luminous efficiency like this, even one, two or three LED bare chips 1 are broken down, it is luminous also not influence whole planar LED.
Claims (6)
1. planar LED structure, it is characterized in that: comprise metallic substrates (2) and fluorescence cover (3), the upper surface of described metallic substrates (2) is fixed with supporting layer (6) along its periphery, and described fluorescence cover (3) is complementary with described supporting layer (6) and is mutually permanently connected and forms a cavity; In described cavity, contain an above LED bare chip (1), fixedly connected with the upper surface of described metallic substrates (2) in the bottom surface of each described LED bare chip (1), the upper surface of described metallic substrates (2) is fixed with insulating barrier (4), be fixed with metal level (5) on the described insulating barrier (4), be electrically connected between the electrode of described metal level (5) and each described LED bare chip (1), the excitation wavelength of the fluorescent material in the described fluorescence cover (3) is identical with the emission wavelength of described LED bare chip (1).
2. a kind of planar LED structure according to claim 1 is characterized in that: described LED bare chip (1) is a light emitting diode (LED) chip with vertical structure.
3. a kind of planar LED structure according to claim 2, it is characterized in that: described LED bare chip (1) comprises first conductive buffer layer (10), N type epitaxial loayer electrode (11), N type epitaxial loayer (12), multiple quantum well layer (13), P type epitaxial loayer (14) and P type epitaxial loayer electrode (15) from bottom to top successively, and described P type epitaxial loayer electrode (15) is electrically connected with described metal level (5) by lead.
4. a kind of planar LED structure according to claim 2, it is characterized in that: described LED bare chip (1) comprises second conductive buffer layer (16), P type epitaxial loayer electrode (15), P type epitaxial loayer (14), multiple quantum well layer (13), N type epitaxial loayer (12) and N type epitaxial loayer electrode (11) from bottom to top successively, and described N type epitaxial loayer electrode (11) is electrically connected with described metal level (5) by lead.
5. according to claim 3 or 4 described a kind of planar LED structures, it is characterized in that: described lead is gold thread, aluminum steel or copper cash.
6. according to the described a kind of planar LED structure of claim 1, it is characterized in that: described metal level (5) is aluminium foil, Copper Foil or goldleaf.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202967153U CN201749849U (en) | 2010-08-17 | 2010-08-17 | Planar light-emitting diode (LED) structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202967153U CN201749849U (en) | 2010-08-17 | 2010-08-17 | Planar light-emitting diode (LED) structure |
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| CN201749849U true CN201749849U (en) | 2011-02-16 |
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| CN2010202967153U Expired - Fee Related CN201749849U (en) | 2010-08-17 | 2010-08-17 | Planar light-emitting diode (LED) structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969058A (en) * | 2010-08-17 | 2011-02-09 | 浙江大学 | Planar LED structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101969058A (en) * | 2010-08-17 | 2011-02-09 | 浙江大学 | Planar LED structure |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110216 Termination date: 20160817 |