CN201725798U

CN201725798U - IGBT device with dielectric trapping layer

Info

Publication number: CN201725798U
Application number: CN2010202367559U
Authority: CN
Inventors: 李伟; 何文牧; 沈征
Original assignee: ZHEJIANG HUAXIN TECHNOLOGY Co Ltd
Current assignee: ZHEJIANG HUAXIN TECHNOLOGY Co Ltd
Priority date: 2010-06-24
Filing date: 2010-06-24
Publication date: 2011-01-26
Anticipated expiration: 2020-06-24

Abstract

The utility model provides an IGBT device with a dielectric trapping layer, which comprises a P + type doped body contact region, an N + type doped source region, a P type base region, an N-type doped drift region, an N-type doped electric field cutoff region and a P + type emitter region, wherein the P + type doped body contact region and part of the N + type doped source region are covered with metal emitter electrodes, and the other part of the N + type doped source region, the P type base region and the N-type doped drift region are covered with a gate oxide silicon region; the gate oxide silicon region is covered with polysilicon gate electrodes, and the P + type emitter region is covered with metal collector electrodes; and the dielectric trapping layer is embedded between the P type base region and the N-type doped drift region, and an N type doped region is arranged above the dielectric trapping layer beyond the edge part of the P type base region. The utility model has the beneficial effects that: the dielectric trapping layer and the N type doped region play the role of accumulating excess carriers, enhance the space distribution of the excess carriers, and optimize the performances of the IGBT device performance; and the utility model has few lattice defects, simple and reliable structure and low processing cost.

Description

A kind of IGBT device with dielectric medium trapping layer

Technical field

The utility model belongs to the semiconductor electronic components and parts and makes the field, is specifically related to a kind of IGBT device with dielectric medium trapping layer.

Background technology

IGBT (insulated gate bipolar transistor) is the most representative product of the power electronic technology revolution for the third time of generally acknowledging in the world, is to have one of power device of advantage most in the present electric and electronic technical field.IGBT is a kind of MOS of having input, the MOS of bipolar output function, the bipolar device that combines.On the structure, it is made up of thousands of repetitives (being cellular), is a kind of a kind of high-power integrated device that adopts large scale integrated circuit technology and power device technology to make.IGBT is widely used in electrical machine energy-saving, metallurgy, new forms of energy, power transmission and transformation, automotive electronics, track traffic, and each field of national economy such as household electrical appliance is one of indispensable key technology of China Reconstructs's resource-conserving and friendly environment society.IGBT succeeded in developing at the beginning of the eighties in last century, and its performance is applied to the high-power field of medium-high frequency maturely through twenties years improving constantly and improving., show superior combination properties such as easy driving, low on-state pressure drop, very fast switching speed, high withstand voltage, big electric current, high-frequency in the characteristics that it is little with voltage control, the power controlling of MOSFET, be easy to parallel connection, switching speed is high and the feature set that current density is big, current handling capability strong, saturation pressure reduces of bipolar transistor.Its on state current density is tens times of VDMOS.The present voltage range of IGBT device has diffused into 300 to 6500 volts, and current range has diffused into several amperes to the hundreds of ampere, and frequency range has diffused into hundreds of hertz to tens kilo hertz.It is the multicore sheet power model on basis or traditional discrete power device package form that igbt chip adopts the hybrid package technology according to the electric current range of application.

How further to reduce IGBT conduct positive pressure drop raising device performance and become an important problem.The key that problem solves is how to improve the excess carriers concentration of closing on the P base.Conventional IGBT device comprises P+ type adulterate body contact zone, N+ type doping source region, P type base and N type doped drift region, N type doped electric field cut-off region and P+ type emitter region, P+ type adulterate body contact zone and part N+ type doping source region are covered by the metal emission electrode, N+ type doping source region another part, P type base and N type doped drift region are covered by the gate oxidation silicon area, cover polygate electrodes on the gate oxidation silicon area, P+ type emitter region is covered by metal collector.Because during the IGBT forward conduction, the PN junction that forms between P base and the N type doped drift region is a reverse bias, caused should zone excess carriers concentration on the low side and the IGBT forward voltage drop is too high.Reduce the P base by the whole bag of tricks the influence of excess carriers concentration is become at no distant date research heat subject.Manabu Takei equals to deliver the article that is entitled as " DB (Dielectric Barrier) IGBT with Extreme Injection Enhancement " on June 7th, 2010 on the 22nd International Symposium on Power Semiconductor Devices and IC ' s, proposes to stop buried regions to cover the effect that the P base reaches the excess carriers concentration that improves this district with dielectric medium.But this technology adopts horizontal selective epitaxial growth technology (Lateral Selective epitaxial growth), the cost height, and lattice defect is many, and the practical application of this device concept is brought big difficulty.

The utility model content

The utility model provides a kind of IGBT device of optimizing the spatial distribution of modulation excess carriers at the problem that prior art exists.For achieving the above object, the utility model adopts following solution:

A kind of IGBT device with dielectric medium trapping layer, comprise P+ type adulterate body contact zone, N+ type doping source region, P type base and N type doped drift region, N type doped electric field cut-off region and P+ type emitter region, P+ type adulterate body contact zone and part N+ type doping source region are covered by the metal emission electrode, N+ type doping source region another part, P type base and N type doped drift region are covered by the gate oxidation silicon area, cover polygate electrodes on the gate oxidation silicon area, P+ type emitter region is covered by metal collector, be embedded with dielectric medium trapping layer (Dielectric Barrier or DB) between described P type base and the N type doped drift region, the top that the dielectric medium trapping layer exceeds marginal portion, P type base is provided with N type doped region.

Form the MOS raceway groove between described P type base and the N type doped region and below the grid silicon oxide layer, the dielectric medium trapping layer outside also is provided with the N type fill area that is used to connect MOS raceway groove and N type doped drift region.

Single crystal silicon material is all adopted in described P+ type doped region, N+ type doping source region, P type base, N type doped region, N type doped drift region, N type doped electric field cut-off region and P+ type emitter region, and N type fill area adopts polycrystalline silicon material.

As preferably, described dielectric medium trapping layer adopts earth silicon material.

As another preferred version, described dielectric medium trapping layer adopts silicon nitride material.

The utility model is compared with existing IGBT device, and beneficial effect is: by dielectric medium trapping layer and N type doped region are set, play the effect of savings excess carriers, strengthen the spatial distribution of excess carriers, optimize the IGBT device performance; Lattice defect is few simple and reliable for structure, and processing cost is low.

Description of drawings

Fig. 1 is the internal structure schematic diagram of existing IGBT device;

Fig. 2 is an IGBT device inside structural representation of the present utility model.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is done and to be described in further detail:

Existing IGBT device as shown in Figure 1, form by following zone: P+ type adulterate body contact zone 1, N+ type doping source region 2, P type base 3, N type doped drift region 4, N type doped electric field cut-off region 5, P+ type emitter region 6, P+ type adulterate body contact zone 1 and part N+ type doping source region 2 are covered by metal emission electrode 8, N+ type doping source region 2 another part, P type base 3 and N type doped drift region 4 are covered by gate oxidation silicon area 13, cover polygate electrodes 9 on the gate oxidation silicon area 13, P+ type emitter region 6 is covered by metal collector 8.Because during the IGBT forward conduction, the PN junction of formation is a reverse bias between P type base 3 and the N type doped drift region 4, caused should zone excess carriers concentration on the low side and the IGBT forward voltage drop is too high.

The utility model provides a kind of IGBT device with dielectric medium trapping layer, and structure as shown in Figure 2.Form by following zone: P+ type adulterate body contact zone 1, N+ type doping source region 2, P type base 3, N type doped drift region 4, N type doped electric field cut-off region 5, P+ type emitter region 6, P+ type adulterate body contact zone 1 and part N+ type doping source region 2 are covered by metal emission electrode 8, N+ type doping source region 2 another part, P type base 3 and N type doped drift region 4 are covered by gate oxidation silicon area 13, cover polygate electrodes 9 on the gate oxidation silicon area 13, and P+ type emitter region 6 is covered by metal collector 8.

Be with the IGBT device difference of routine, between P type base 3 and N type doped drift region 4, be embedded with dielectric medium trapping layer 12, stop holoe carrier to flow to P type base 3, to reach the effect that reduces the 3 pairs of excess carriers concentration affects in P type base.This dielectric medium trapping layer 12 can adopt the various dielectric materials that comprise silicon dioxide, silicon nitride, and thickness is between 0.5 to 5 micron, and width is between 1 to 20 micron.Dielectric medium trapping layer 12 thickness and width, with and the thickness of the N type doped

region

10,11 of top, width, doping content is all influential to the puncture voltage and the charge carrier spatial distribution of device, is the important parameter that designs is optimized.This dielectric barrier buried regions 12 can adopt various existing techniques in realizing, comprises using the initial wafer of SOI (silicon on the dielectric substrate).The top that the dielectric medium trapping layer exceeds marginal portion, P type base is provided with N type doped region 10, and thickness is between 0.5 to 5 micron.Dielectric medium trapping layer 12 outsides also are provided with N type fill area 11, play the effect that connects MOS raceway groove and N type drift region 4.

When polysilicon gate 9 places when being lower than threshold voltage and emitter 8 ground connection, this IGBT is in closed condition, and the PN junction that forms between P type base 3 and the N type doped region (10,11, and 4) is in reverse bias, and supports to load the positive voltage on the collector electrode.When institute's making alive on the polysilicon gate 9 is higher than threshold voltage and emitter 8 ground connection, this IGBT is in opening, the interior MOS raceway groove that forms in 3 zones, P type base that is covered by gate oxidation silicon area 13 begins to provide electronic current, and by N type doped single crystal silicon area 10 and adopt the N type fill area 11 of polycrystalline silicon material to be injected into N type doped drift region 4, realize that with P+ type emitter region 6 injected holes electricity leads modulation.The dielectric medium trapping layer that the New IGBT structure is introduced soi wafer stops the hole current that flows to P type base, excess carriers is put aside near the dielectric medium trapping layer, to reach the spatial distribution that strengthens conduction modulation excess carriers, the integral device performance is better than groove grid IGBT structure.

Though the utility model illustrates and describes by the reference preferred embodiment, but those of ordinary skills should understand, and can be not limited to the description of the foregoing description, in the scope of claims, can do the various variations on form and the details.

Claims

1. IGBT device with dielectric medium trapping layer, comprise P+ type adulterate body contact zone, N+ type doping source region, P type base and N type doped drift region, N type doped electric field cut-off region and P+ type emitter region, P+ type adulterate body contact zone and part N+ type doping source region are covered by the metal emission electrode, N+ type doping source region another part, P type base and N type doped drift region are covered by the gate oxidation silicon area, cover polygate electrodes on the gate oxidation silicon area, P+ type emitter region is covered by metal collector, it is characterized in that: be embedded with the dielectric medium trapping layer between described P type base and the N type doped drift region, the top that the dielectric medium trapping layer exceeds marginal portion, P type base is provided with N type doped region.

2. a kind of IGBT device according to claim 1 with dielectric medium trapping layer, it is characterized in that: form the MOS raceway groove between described P type base and the N type doped region and below the grid silicon oxide layer, the dielectric medium trapping layer outside also is provided with the N type fill area that is used to connect MOS raceway groove and N type doped drift region.

3. a kind of IGBT device according to claim 2 with dielectric medium trapping layer, it is characterized in that: single crystal silicon material is all adopted in described P+ type doped region, N+ type doping source region, P type base, N type doped region, N type doped drift region, N type doped electric field cut-off region and P+ type emitter region, and N type fill area adopts polycrystalline silicon material.

4. a kind of IGBT device with dielectric medium trapping layer according to claim 1 is characterized in that: described dielectric medium trapping layer adopts earth silicon material.

5. a kind of IGBT device with dielectric medium trapping layer according to claim 1 is characterized in that: described dielectric medium trapping layer adopts silicon nitride material.

6. according to each described a kind of IGBT device with dielectric medium trapping layer of claim 1 to 5, it is characterized in that: dielectric medium trapping layer thickness is between 0.5 to 5 micron, and width is between 1 to 20 micron.

7. according to each described a kind of IGBT device with dielectric medium trapping layer of claim 1 to 5, it is characterized in that: the dielectric medium trapping layer makes by the initial wafer of SOI.