CN201616819U - Integral analog-to-digital converter - Google Patents

Abstract

The utility model relates to an integral analog-to-digital converter, which comprises an integrator, a comparator and a desampling filter that are connected in sequence, as well as a logic control circuit, an input sampling circuit and a feedback sampling circuit, wherein the input terminal of the logic control circuit is not only connected with the output terminal of the comparator but also connected with the output terminal thereof via a negator, receives a first input control signal and a second input control signal that are input externally, and outputs a first feedback control signal and a second feedback control signal that are used for controlling the feedback sampling circuit. By virtue of the additionally arranged logic control circuit, the utility model controls various sampling switches to open and close alternately in a sampling cycle, thereby reducing the sampling rate ratio of the input signals and the feedback signals, effectively lowering the signal-to-noise ratio caused by overload, and overcoming the defect of the method of reducing the proportion of the input capacitance and the feedback capacitance in the prior art.

Description

A kind of integral analogue-to-digital converter

Technical field

The utility model relates to the electric energy metrical field, relates in particular to a kind of integral analogue-to-digital converter that is used for the analog module of electric energy computation chip.

Background technology

As everyone knows, integral analogue-to-digital converter (being ∑ Δ A/D converter) generally adopts oversampling technique, noise shaping technology and digital filtering technique, by a large amount of noise energies being pushed to the outer high frequency treatment of signal baseband, utilize digital filter filtering out-of-band noise again, thereby obtain very high precision, yet, also just owing to adopted higher over-sampling, limited the bandwidth of signal to a certain extent, therefore ∑ Δ A/D converter is mainly used in low speed, the high accuracy field, especially in the low bandwidth requirement, and need to be commonly employed in the high-precision ammeter design.

In the prior art, with simple single order ∑ Δ A/D converter is example, its structured flowchart as shown in Figure 1, it comprises analog modulator 1 ' and desampling fir filter 2 ', and analog modulator 1 ' comprises sampling hold circuit 11 ', adder 12 ', integrator 13 ', comparator 14 ' and digital to analog converter 15 ', wherein, analog modulator 1 ' is a most important parts in the entire circuit, because it has determined highest resolution and conversion speed that whole ∑ Δ A/D converter can reach; Specifically, when the aanalogvoltage that inputs to integrator 13 ' near through the positive reference voltage signal Vref+ of digital to analog converter 15 ' feedback or negative reference voltage signal Vref-the time, the noise energy level rises rapidly.When the input overload took place, noise increased sharply, and in the long clock cycle, the result of analog modulator 1 ' output remains under the same state, therefore needs a longer clock cycle to stablize the output of integrator 13 ' to obtain accurate output.

Yet in fact, in the analog modulator system of high-order, promptly include under the situation of a plurality of integrators, the unsettled risk of analog modulator system increases, and the scope of signal input is dwindled.It is that a reduction is because the unsettled way of analog modulator system that the input overload causes that integrator gain is dwindled, the method essence that integrator gain is dwindled is to adjust the ratio of integrator input capacitance and feedback capacity, the electric charge that causes being transferred to input capacitance from feedback capacity effectively increases, specifically:

According to the charge balance equation:

RC _inV _in+m(-C _refV _ref)+(1-m)(C _refV _ref)＝0 (1)

In the formula (1),

R: the ratio of input signal sample frequency and benchmark sample rate;

C _In: input capacitance;

V _In: input signal;

M: in the enough big output stream, be output as high density;

V _Ref: reference voltage;

C _Ref: feedback capacity;

Formula (1) gets after deriving:

m＝(1+R)(C _in/C _ref)(V _in/V _ref) (2)

By formula (2) as seen:

Signal to noise ratio $\mathrm{Gain}=\frac{\mathrm{dm}}{{\mathrm{dV}}_{\mathrm{in}}}=\frac{R(C_{\mathrm{in}}/C_{\mathrm{ref}})}{V_{\mathrm{ref}}}---\left(3\right)$

Can see by formula (3), by adjusting input capacitance C _InWith feedback capacity C _RefRatio, can reduce the value of signal to noise ratio Gain, thereby reduce the risk of input overload effectively, improved the scope of input signal.But this method in fact, be by reducing input capacitance, make the ratio of input capacitance and feedback capacity reduce, promptly on addition node, the share that comes from input signal reduces, the share that comes from feedback signal increases, because the signal of input is weakened at the integrator input, thereby has reduced the dynamic range of whole ∑ Δ A/D converter.

The utility model content

In order to overcome the deficiency that above-mentioned prior art exists, the utility model aims to provide a kind of integral analogue-to-digital converter of improvement, to realize improving the input range of input signal, optimizes because the purpose of the unstable situation of system that the input overload causes.

A kind of integral analogue-to-digital converter described in the utility model comprises the integrator, comparator and the desampling fir filter that connect successively, and described transducer also comprises a logic control circuit, an input sampling circuit and a feedback sampling circuit,

The input of described logic control circuit is connected with the output of described comparator on the one hand, be connected with the output of described comparator by a not gate on the other hand, and receiving outside first input control signal and second input control signal of importing, output is used to control first feedback control signal and second feedback control signal of described feedback sampling circuit;

Described input sampling circuit comprises the first input sample switch of series connection successively and the 3rd input sample switch and the 4th input sample switch of the second input sample switch and series connection successively, the output of this second input sample switch is connected the inverting input of described integrator, the output of the 4th input sample switch is connected the in-phase input end of described integrator, and be connected with the 5th input sample switch between the input of the output of the described first input sample switch and the 3rd input sample switch, be connected with the 7th input sample switch between the input of this first input sample switch and the output of the 3rd input sample switch, the output of described first input sample switch and the 3rd input sample switch is also respectively by the 6th input sample switch and the 8th input sample switch ground connection;

Described feedback sampling circuit comprises the first feedback sample switch of series connection successively and the 3rd feedback sample switch and the 4th feedback sample switch of the second feedback sample switch and series connection successively, the output of this second feedback sample switch is connected the in-phase input end of described integrator, the output of the 4th feedback sample switch is connected the inverting input of described integrator, and be connected with the 5th feedback sample switch between the output of the described first feedback sample switch and the 3rd feedback sample switch input terminal, be connected with the 7th feedback sample switch between the input of this first feedback sample switch and the 3rd feedback sample output switching terminal, be connected with the 6th feedback sample switch between the input of the described second feedback sample switch and the 4th feedback sample output switching terminal, be connected with the 8th feedback sample switch between the output of this second feedback sample switch and the 4th feedback sample switch input terminal.

In above-mentioned integral analogue-to-digital converter, described the second, the 4th, the 5th, the 7th input sample switch and the first, the 3rd feedback sample switch receive described first input control signal, described the first, the 3rd, the 6th, the 8th input sample switch and the 5th, the 7th feedback sample switch receive described second input control signal, described the 6th, the 8th feedback sample switch receives described first feedback control signal, and described the second, the 4th feedback sample switch receives described second feedback control signal.

In above-mentioned integral analogue-to-digital converter, series connection first input capacitance between the described first input sample switch and the second input sample switch, series connection second input capacitance between described the 3rd input sample switch and the 4th input sample switch, series connection first feedback capacity between the described first feedback sample switch and the second feedback sample switch, series connection second feedback capacity between described the 3rd feedback sample switch and the 4th feedback sample switch.

Owing to adopted above-mentioned technical solution, the utility model alternately opens and closes in a sampling period to control each sampling switch by setting up logic control circuit, make input voltage signal in an employing cycle, once sample, and the reference voltage signal of feedback is twice of sampling period sampling, thereby reduced the sampling rate ratio of input signal with feedback signal, and the final signal to noise ratio that makes overload cause effectively descends, and improved the existing defective of method of dwindling input capacitance and feedback capacity ratio in the prior art.

Description of drawings

Fig. 1 is the structured flowchart of single order ∑ Δ A/D converter in the prior art;

Fig. 2 is the structural representation of integral analogue-to-digital converter of the present utility model;

Fig. 3 is the sequential chart of the input control signal in the utility model integral analogue-to-digital converter;

Fig. 4 is the sequential chart of the feedback control signal in the utility model integral analogue-to-digital converter;

Fig. 5 is the utility model integral analogue-to-digital converter equivalent structure schematic diagram of 1 o'clock time period in a sampling period;

Fig. 6 is the utility model integral analogue-to-digital converter equivalent structure schematic diagram of 2 o'clock time periods in a sampling period.

Embodiment

Below in conjunction with accompanying drawing, specific embodiment of the utility model is elaborated.

As shown in Figure 2, the utility model, promptly a kind of integral analogue-to-digital converter, it comprises input sampling circuit 1, feedback sampling circuit 2, integrator 3, comparator 4, desampling fir filter 5 and logic control circuit 6, wherein,

The input of logic control circuit 6 directly is connected with the output of comparator 4 on the one hand, receive data-signal Y1, be connected with the output of comparator 4 by a not gate 7 on the other hand, receive anti-phase data signal Y2, also receive the first input control signal T1 and the second input control signal T2 of outside input simultaneously, output is used for the first feedback control signal T1Y1+T2Y2 and the second feedback control signal T2Y1+T1Y2 of Control and Feedback sample circuit 2;

Input sampling circuit 1 comprises the 3rd input sample switch S 13, the second input capacitance Cin2 and the 4th input sample switch S 14 of the first input sample switch S 11, the first input capacitance Cin1 and the second input sample switch S 12 of series connection successively and series connection successively; Wherein, the input of the first input sample switch S 11 receives positive input voltage signal Vin+, and the output of the second input sample switch S 12 is connected with the inverting input of integrator 3; The input of the 3rd input sample switch S 13 receives negative input voltage signal Vin-, and the output of the 4th input sample switch S 14 is connected with the in-phase input end of integrator 3; In addition, be connected with between the input of the output of the first input sample switch S 11 and the 3rd input sample switch S 13 between the output of the input of the 5th input sample switch S 15, the first input sample switch S 11 and the 3rd input sample switch S 13 and be connected with the 7th input sample switch S 17; The output of the first input sample switch S 11 and the 3rd input sample switch S 13 is also respectively by the 6th input sample switch S 16 and the 8th input sample switch S 18 ground connection;

Feedback sampling circuit 2 comprises the 3rd feedback sample switch S 23, the second feedback capacity Cref2 and the 4th feedback sample switch S 24 of the first feedback sample switch S 21, the first feedback capacity Cref1 and the second feedback sample switch S 2 of series connection successively and series connection successively; Wherein, the input of the first feedback sample switch S 21 receives positive reference voltage signal Vref+, and the output of the second feedback sample switch S 22 is connected with the in-phase input end of integrator 3; The input of the 3rd feedback sample switch S 23 receives negative reference voltage signal Vref-, and the output of the 4th feedback sample switch S 24 is connected with the inverting input of integrator 3; In addition, be connected with between the output of the first feedback sample switch S 21 and the 3rd feedback sample switch S 23 inputs between the input of the 5th feedback sample switch S 25, the first feedback sample switch S 21 and the 3rd feedback sample switch S 23 outputs and be connected with the 7th feedback sample switch S 27; Be connected with between the input of the second feedback sample switch S 22 and the 4th feedback sample switch S 24 outputs between the output of the 6th feedback sample switch S 26, the second feedback sample switch S 22 and the 4th feedback sample switch S 24 inputs and be connected with the 8th feedback sample switch S 28.

In the utility model, the second, the 4th, the 5th, the 7th input sample switch S 12, S14, S15, S17 and first, the 3rd feedback sample switch S 21, S23 receive the first input control signal T1, promptly control its switching by the first input control signal T1; The first, the 3rd, the 6th, the 8th input sample switch S 11, S13, S16, S18 and the 5th, the 7th feedback sample switch S 25, S27 are controlled by the second input control signal T2; Six, the 8th feedback sample switch S 26, S28 are controlled by the first feedback control signal T1Y1+T2Y2, and the second, the 4th feedback sample switch S 22, S24 are controlled by the second feedback control signal T2Y1+T1Y2.

See also Fig. 3 to Fig. 6, in the present embodiment, the controlling of sampling principle of a kind of integral analogue-to-digital converter of the present utility model is elaborated.

In preceding half sampling period, i.e. in the time period 1, the first input control signal T1 is a high level, the second, the 4th, the 5th, the 7th input sample switch S 12, S14, S15, S17 and first, the 3rd feedback sample switch S 21, S23 closure; The second input control signal T2 is a low level, first, the 3rd, the 6th, the 8th input sample switch S 11, S13, S16, S18 and the 5th, the 7th feedback sample switch S 25, S27 opens, the integral analogue-to-digital converter sampling just, negative input voltage signal Vin+, Vin-, comparator 4 outputs one data-signal Y1, be Y1=1, then the first feedback control signal T1Y1+T2Y2 of logic control circuit 6 outputs is a high level, the 6th, the 8th feedback sample switch S 26, the S28 closure, the second feedback control signal T2Y1+T1Y2 is a low level, second, the 4th feedback sample switch S 22, S24 opens, integral analogue-to-digital converter is just being sampled simultaneously, negative feedback reference voltage signal Vref+, Vref-, at this moment, the equivalent structure schematic diagram of integral analogue-to-digital converter as shown in Figure 5;

In back half sampling period, i.e. in the time period 2, the first input control signal T1 is a low level, and the second, the 4th, the 5th, the 7th input sample switch S 12, S14, S15, S17 and first, the 3rd feedback sample switch S 21, S23 open; The second input control signal T2 is a high level, first, the 3rd, the 6th, the 8th input sample switch S 11, S13, S16, S18 and the 5th, the 7th feedback sample switch S 25, the S27 closure, just, negative input voltage signal Vin+, Vin-ground connection, the logic control circuit 6 outputs first feedback control signal T1Y1+T2Y2 is a low level, the 6th, the 8th feedback sample switch S 26, S28 opens, the second feedback control signal T2Y1+T1Y2 is a high level, second, the 4th feedback sample switch S 22, the S24 closure, integral analogue-to-digital converter is just only being sampled, negative feedback reference voltage signal Vref+, Vref-this moment, the equivalent structure schematic diagram of integral analogue-to-digital converter as shown in Figure 6.

By above-mentioned controlling of sampling principle as can be known, in the utility model, the sampling rate of positive-negative feedback reference voltage signal Vref+, Vref-is the twice of the sampling rate of positive and negative input voltage signal Vin+, Vin-, therefore, the ratio R of aforesaid input signal sample frequency and benchmark sample rate can be changed into 0.5 by the utility model;

Again by formula $\mathrm{Gain}=\frac{\mathrm{dm}}{{\mathrm{dV}}_{\mathrm{in}}}=\frac{R(C_{\mathrm{in}}/C_{\mathrm{ref}})}{V_{\mathrm{ref}}}$ As can be known,

The utility model can be under the prerequisite of the dynamic range that does not reduce whole analog to digital converter, and the signal to noise ratio Gain of the analog to digital converter that makes effectively reduces.

Below embodiment has been described in detail the utility model in conjunction with the accompanying drawings, and those skilled in the art can make the many variations example to the utility model according to the above description.Thereby some details among the embodiment should not constitute qualification of the present utility model, and the scope that the utility model will define with appended claims is as protection range of the present utility model.

Claims (3)

1. integral analogue-to-digital converter, it comprises integrator, comparator and the desampling fir filter that connects successively, it is characterized in that described transducer also comprises a logic control circuit, an input sampling circuit and a feedback sampling circuit,

The input of described logic control circuit is connected with the output of described comparator on the one hand, be connected with the output of described comparator by a not gate on the other hand, and receiving outside first input control signal and second input control signal of importing, output is used to control first feedback control signal and second feedback control signal of described feedback sampling circuit;

Described input sampling circuit comprises the first input sample switch of series connection successively and the 3rd input sample switch and the 4th input sample switch of the second input sample switch and series connection successively, the output of this second input sample switch is connected the inverting input of described integrator, the output of the 4th input sample switch is connected the in-phase input end of described integrator, and be connected with the 5th input sample switch between the input of the output of the described first input sample switch and the 3rd input sample switch, be connected with the 7th input sample switch between the input of this first input sample switch and the output of the 3rd input sample switch, the output of described first input sample switch and the 3rd input sample switch is also respectively by the 6th input sample switch and the 8th input sample switch ground connection;

Described feedback sampling circuit comprises the first feedback sample switch of series connection successively and the 3rd feedback sample switch and the 4th feedback sample switch of the second feedback sample switch and series connection successively, the output of this second feedback sample switch is connected the in-phase input end of described integrator, the output of the 4th feedback sample switch is connected the inverting input of described integrator, and be connected with the 5th feedback sample switch between the output of the described first feedback sample switch and the 3rd feedback sample switch input terminal, be connected with the 7th feedback sample switch between the input of this first feedback sample switch and the 3rd feedback sample output switching terminal, be connected with the 6th feedback sample switch between the input of the described second feedback sample switch and the 4th feedback sample output switching terminal, be connected with the 8th feedback sample switch between the output of this second feedback sample switch and the 4th feedback sample switch input terminal.

2. integral analogue-to-digital converter according to claim 1, it is characterized in that, described the second, the 4th, the 5th, the 7th input sample switch and the first, the 3rd feedback sample switch receive described first input control signal, described the first, the 3rd, the 6th, the 8th input sample switch and the 5th, the 7th feedback sample switch receive described second input control signal, described the 6th, the 8th feedback sample switch receives described first feedback control signal, and described the second, the 4th feedback sample switch receives described second feedback control signal.

3. integral analogue-to-digital converter according to claim 1, it is characterized in that, series connection first input capacitance between the described first input sample switch and the second input sample switch, series connection second input capacitance between described the 3rd input sample switch and the 4th input sample switch, series connection first feedback capacity between the described first feedback sample switch and the second feedback sample switch, series connection second feedback capacity between described the 3rd feedback sample switch and the 4th feedback sample switch.

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