CN101741387B - Integral analogue-to-digital converter and sampling control method thereof - Google Patents
Integral analogue-to-digital converter and sampling control method thereof Download PDFInfo
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Abstract
The invention relates to an integral analogue-to-digital converter and a sampling control method thereof. The converter comprises an integrator, a comparator and a down-sampling filter which are sequentially connected, and also comprises a logic control circuit, an input sampling circuit and a feedback sampling circuit, wherein the input end of the logic control circuit is connected with the output end of the comparator on the one hand, and is connected with the output end of the comparator through a negation gate on the other hand, and receives a first input control signal and a second input control signal input from the outside and outputs a first feedback control signal and a second feedback control signal for controlling the feedback sampling circuit. The logic control circuit is arranged to control alternate opening and closing of each sampling switch in a sampling period, so the sampling speed ratio between the input signal and the feedback signal is lowered, the signal-to-noise ratio caused by overload is finally and effectively lowered and defects of a method for reducing the ratio of input capacitance to feedback capacitance in the prior art are overcome.
Description
Technical field
The present invention relates to the electric energy metrical field, relate in particular to a kind of integral analogue-to-digital converter and sampling control method thereof of the analog module for electric energy computation chip.
Background technology
As everyone knows, integral analogue-to-digital converter (being ∑ Δ A/D converter) generally adopts oversampling technique, noise shaping technology and digital filtering technique, by a large amount of noise energies being pushed to the outer high frequency treatment of signal baseband, recycling digital filter filtering out-of-band noise, thereby obtain very high precision, yet, also just owing to adopted higher over-sampling, limited to a certain extent the bandwidth of signal, therefore ∑ Δ A/D converter is mainly used in low speed, the high accuracy field, especially in the low bandwidth requirement, and need to be commonly employed in the high-precision ammeter design.
In the prior art, take simple single order ∑ Δ A/D converter as example, its structured flowchart as shown in Figure 1, it comprises analog modulator 1 ' and desampling fir filter 2 ', and analog modulator 1 ' comprises sampling hold circuit 11 ', adder 12 ', integrator 13 ', comparator 14 ' and digital to analog converter 15 ', wherein, analog modulator 1 ' is most important part in the whole circuit, because it has determined highest resolution and conversion speed that whole ∑ Δ A/D converter can reach; Specifically, when the aanalogvoltage that inputs to integrator 13 ' approached through the positive reference voltage signal Vref+ of digital to analog converter 15 ' feedback or negative reference voltage signal Vref-, the noise energy level rose rapidly.When the input overload occured, noise increased sharply, and within the long clock cycle, the result of analog modulator 1 ' output remains under the same state, therefore needs a longer clock cycle to stablize the output of integrator 13 ' to obtain accurate output.
Yet in fact, in the analog modulator system of high-order, namely include in the situation of a plurality of integrators, the unsettled risk of analog modulator system increases, and the scope of signal input is dwindled.It is that a reduction is because the unsettled way of analog modulator system that the input overload causes that integrator gain is dwindled, the method essence that integrator gain is dwindled is to adjust the ratio of integrator input capacitance and feedback capacity, the electric charge that causes being transferred to input capacitance from feedback capacity effectively increases, specifically:
According to the charge balance equation:
RC
inV
in+m(-C
refV
ref)+(1-m)(C
refV
ref)＝0 (1)
In the formula (1),
R: the ratio of input signal sample frequency and benchmark sample rate;
C
In: input capacitance;
V
In: input signal;
M: enough in the large output stream, be output as high density;
V
Ref: reference voltage;
C
Ref: feedback capacity;
Formula (1) gets after deriving:
m＝(1+R)(C
in/C
ref)(V
in/V
ref) (2)
By formula (2) as seen:
Signal to noise ratio
Can be seen by formula (3), by adjusting input capacitance C
InWith feedback capacity C
RefRatio, can reduce the value of signal to noise ratio Gain, thereby effectively reduce the risk of input overload, improved the scope of input signal.But this method in fact, by reducing input capacitance, so that the ratio of input capacitance and feedback capacity reduces, namely on addition node, the share that comes from input signal reduces, the share that comes from feedback signal increases, because the signal of input is weakened at the integrator input, thereby has reduced the dynamic range of whole ∑ Δ A/D converter.
Summary of the invention
The deficiency that exists in order to overcome above-mentioned prior art, the present invention aims to provide a kind of integral analogue-to-digital converter and sampling control method thereof of improvement, to realize improving the input range of input signal, optimize because the purpose of the unstable situation of system that the input overload causes.
The described a kind of integral analogue-to-digital converter of one of the present invention comprises the integrator, comparator and the desampling fir filter that connect successively, and described transducer also comprises a logic control circuit, an input sampling circuit and a feedback sampling circuit,
The input of described logic control circuit is connected with the output of described comparator on the one hand, be connected with the output of described comparator by a not gate on the other hand, and receiving outside the first input control signal and the second input control signal of inputting, output is used for controlling the first feedback control signal and second feedback control signal of described feedback sampling circuit;
Described input sampling circuit comprises the first input sample switch of successively series connection and the 3rd input sample switch and the 4th input sample switch of the second input sample switch and successively series connection, the output of this second input sample switch is connected to the inverting input of described integrator, the output of the 4th input sample switch is connected to the in-phase input end of described integrator, and be connected with the 5th input sample switch between the input of the output of described the first input sample switch and the 3rd input sample switch, be connected with the 7th input sample switch between the input of this first input sample switch and the output of the 3rd input sample switch, the output of described the first input sample switch and the 3rd input sample switch is also respectively by the 6th input sample switch and the 8th input sample switch ground connection;
Described feedback sampling circuit comprises the first feedback sample switch of successively series connection and the 3rd feedback sample switch and the 4th feedback sample switch of the second feedback sample switch and successively series connection, the output of this second feedback sample switch is connected to the in-phase input end of described integrator, the output of the 4th feedback sample switch is connected to the inverting input of described integrator, and be connected with the 5th feedback sample switch between the output of described the first feedback sample switch and the 3rd feedback sample switch input terminal, be connected with the 7th feedback sample switch between the input of this first feedback sample switch and the 3rd feedback sample output switching terminal, be connected with the 6th feedback sample switch between the input of described the second feedback sample switch and the 4th feedback sample output switching terminal, be connected with the 8th feedback sample switch between the output of this second feedback sample switch and the 4th feedback sample switch input terminal.
In above-mentioned integral analogue-to-digital converter, described the second, the 4th, the 5th, the 7th input sample switch and the first, the 3rd feedback sample switch receive described the first input control signal, described the first, the 3rd, the 6th, the 8th input sample switch and the 5th, the 7th feedback sample switch receive described the second input control signal, described the 6th, the 8th feedback sample switch receives described the first feedback control signal, and described the second, the 4th feedback sample switch receives described the second feedback control signal.
In above-mentioned integral analogue-to-digital converter, series connection the first input capacitance between described the first input sample switch and the second input sample switch, series connection the second input capacitance between described the 3rd input sample switch and the 4th input sample switch, series connection the first feedback capacity between described the first feedback sample switch and the second feedback sample switch, series connection the second feedback capacity between described the 3rd feedback sample switch and the 4th feedback sample switch.
The sampling control method of two described a kind of integral analogue-to-digital converters of the present invention comprises the following steps,
Step 2, within rear half sampling period, control sampling positive-negative feedback reference voltage signal.
In the sampling control method of above-mentioned integral analogue-to-digital converter, described step 1 and step 2 realize by logic control circuit, several input sample switches and several feedback sample switches.
Owing to adopted above-mentioned technical solution, the present invention alternately opens and closes within a sampling period to control each sampling switch by setting up logic control circuit, so that input voltage signal was once sampled within an employing cycle, and the reference voltage signal of feedback is twice of sampling period sampling, thereby reduced the sampling rate ratio of input signal with feedback signal, and final so that the signal to noise ratio that overload causes effectively descends, improved the existing defective of method of dwindling input capacitance and feedback capacity ratio in the prior art.
Description of drawings
Fig. 1 is the structured flowchart of single order ∑ Δ A/D converter in the prior art;
Fig. 2 is the structural representation of integral analogue-to-digital converter of the present invention;
Fig. 3 is the sequential chart of the input control signal in the integral analogue-to-digital converter of the present invention;
Fig. 4 is the sequential chart of the feedback control signal in the integral analogue-to-digital converter of the present invention;
Fig. 5 is the integral analogue-to-digital converter of the present invention equivalent structure schematic diagram of 1 o'clock time period within a sampling period;
Fig. 6 is the integral analogue-to-digital converter of the present invention equivalent structure schematic diagram of 2 o'clock time periods within a sampling period.
Embodiment
Below in conjunction with accompanying drawing, specific embodiments of the invention are elaborated.
As shown in Figure 2, one of the present invention's integral analogue-to-digital converter comprises input sampling circuit 1, feedback sampling circuit 2, integrator 3, comparator 4, desampling fir filter 5 and logic control circuit 6, wherein,
The input of logic control circuit 6 directly is connected with the output of comparator 4 on the one hand, reception of data signal Y1, be connected with the output of comparator 4 by a not gate 7 on the other hand, receive anti-phase data signal Y2, also receive simultaneously the first input control signal T1 and the second input control signal T2 of outside input, output is used for the first feedback control signal T1Y1+T2Y2 and the second feedback control signal T2Y1+T1Y2 of control feedback sampling circuit 2;
Feedback sampling circuit 2 comprises the 3rd feedback sample switch S 23, the second feedback capacity Cref2 and the 4th feedback sample switch S 24 of the first feedback sample switch S 21, the first feedback capacity Cref1 and the second feedback sample switch S 2 of successively series connection and successively series connection; Wherein, the input of the first feedback sample switch S 21 receives positive reference voltage signal Vref+, and the output of the second feedback sample switch S 22 is connected with the in-phase input end of integrator 3; The input of the 3rd feedback sample switch S 23 receives negative reference voltage signal Vref-, and the output of the 4th feedback sample switch S 24 is connected with the inverting input of integrator 3; In addition, be connected with between the output of the first feedback sample switch S 21 and the 3rd feedback sample switch S 23 inputs between the input of the 5th feedback sample switch S 25, the first feedback sample switch S 21 and the 3rd feedback sample switch S 23 outputs and be connected with the 7th feedback sample switch S 27; Be connected with between the input of the second feedback sample switch S 22 and the 4th feedback sample switch S 24 outputs between the output of the 6th feedback sample switch S 26, the second feedback sample switch S 22 and the 4th feedback sample switch S 24 inputs and be connected with the 8th feedback sample switch S 28.
In the present invention, the second, the 4th, the 5th, the 7th input sample switch S 12, S14, S15, S17 and first, the 3rd feedback sample switch S 21, S23 receive the first input control signal T1, namely control its switching by the first input control signal T1; The first, the 3rd, the 6th, the 8th input sample switch S 11, S13, S16, S18 and the 5th, the 7th feedback sample switch S 25, S27 are controlled by the second input control signal T2; Six, the 8th feedback sample switch S 26, S28 are controlled by the first feedback control signal T1Y1+T2Y2, and the second, the 4th feedback sample switch S 22, S24 are controlled by the second feedback control signal T2Y1+T1Y2.
See also Fig. 3 to Fig. 6, in the present embodiment, take above-mentioned integral analogue-to-digital converter as example, the sampling control method of a kind of integral analogue-to-digital converter of two of the present invention is elaborated, this sampling control method comprises the following steps,
Step 2, within rear half sampling period, i.e. in the time period 2, the first input control signal T1 is low level, the second, the 4th, the 5th, the 7th input sample switch S 12, S14, S15, S17 and first, the 3rd feedback sample switch S 21, S23 open; The second input control signal T2 is high level, first, the 3rd, the 6th, the 8th input sample switch S 11, S13, S16, S18 and the 5th, the 7th feedback sample switch S 25, S27 is closed, just, negative input voltage signal Vin+, Vin-ground connection, logic control circuit 6 outputs the first feedback control signal T1Y1+T2Y2 is low level, the 6th, the 8th feedback sample switch S 26, S28 opens, the second feedback control signal T2Y1+T1Y2 is high level, second, the 4th feedback sample switch S 22, S24 is closed, integral analogue-to-digital converter is just only being sampled, negative feedback reference voltage signal Vref+, Vref-this moment, the equivalent structure schematic diagram of integral analogue-to-digital converter as shown in Figure 6.
By above-mentioned sampling control method as can be known, in the present invention, the sampling rate of positive-negative feedback reference voltage signal Vref+, Vref-is the twice of the sampling rate of positive and negative input voltage signal Vin+, Vin-, therefore, the ratio R of aforesaid input signal sample frequency and benchmark sample rate can be changed into 0.5 by the present invention;
Again by formula
As can be known,
The present invention can be under the prerequisite of the dynamic range that does not reduce whole analog to digital converter, and the signal to noise ratio Gain of the analog to digital converter that makes effectively reduces.
Below embodiment has been described in detail the present invention by reference to the accompanying drawings, and those skilled in the art can make the many variations example to the present invention according to the above description.Thereby some details among the embodiment should not consist of limitation of the invention, and the scope that the present invention will define with appended claims is as protection scope of the present invention.
Claims (2)
1. integral analogue-to-digital converter, it comprises integrator, comparator and the desampling fir filter that connects successively, it is characterized in that described transducer also comprises a logic control circuit, an input sampling circuit and a feedback sampling circuit,
The input of described logic control circuit is connected with the output of described comparator on the one hand, be connected with the output of described comparator by a not gate on the other hand, and receiving outside the first input control signal and the second input control signal of inputting, output is used for controlling the first feedback control signal and second feedback control signal of described feedback sampling circuit;
Described input sampling circuit comprises the first input sample switch of successively series connection and the 3rd input sample switch and the 4th input sample switch of the second input sample switch and successively series connection, the output of this second input sample switch is connected to the inverting input of described integrator, the output of the 4th input sample switch is connected to the in-phase input end of described integrator, and be connected with the 5th input sample switch between the input of the output of described the first input sample switch and the 3rd input sample switch, be connected with the 7th input sample switch between the input of this first input sample switch and the output of the 3rd input sample switch, the output of described the first input sample switch and the 3rd input sample switch is also respectively by the 6th input sample switch and the 8th input sample switch ground connection;
Described feedback sampling circuit comprises the first feedback sample switch of successively series connection and the 3rd feedback sample switch and the 4th feedback sample switch of the second feedback sample switch and successively series connection, the output of this second feedback sample switch is connected to the in-phase input end of described integrator, the output of the 4th feedback sample switch is connected to the inverting input of described integrator, and be connected with the 5th feedback sample switch between the output of described the first feedback sample switch and the 3rd feedback sample switch input terminal, be connected with the 7th feedback sample switch between the input of this first feedback sample switch and the 3rd feedback sample output switching terminal, be connected with the 6th feedback sample switch between the input of described the second feedback sample switch and the 4th feedback sample output switching terminal, be connected with the 8th feedback sample switch between the output of this second feedback sample switch and the 4th feedback sample switch input terminal
Described the second, the 4th, the 5th, the 7th input sample switch and the first, the 3rd feedback sample switch receive described the first input control signal, described the first, the 3rd, the 6th, the 8th input sample switch and the 5th, the 7th feedback sample switch receive described the second input control signal, described the 6th, the 8th feedback sample switch receives described the first feedback control signal, described the second, the 4th feedback sample switch receives described the second feedback control signal
Series connection the first input capacitance between described the first input sample switch and the second input sample switch, series connection the second input capacitance between described the 3rd input sample switch and the 4th input sample switch, series connection the first feedback capacity between described the first feedback sample switch and the second feedback sample switch, series connection the second feedback capacity between described the 3rd feedback sample switch and the 4th feedback sample switch.
2. the sampling control method of an integral analogue-to-digital converter as claimed in claim 1 is characterized in that, described sampling control method comprises the following steps,
Step 1, within front half sampling period, the control positive and negative voltage input signal of sampling and positive-negative feedback reference voltage signal;
Step 2, within rear half sampling period, control sampling positive-negative feedback reference voltage signal.
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| CN102868408B (en) * | 2011-07-05 | 2015-05-20 | 北京立博信荣科技有限公司 | Integral analog-to-digital converter |
| CN103825596B (en) * | 2014-03-07 | 2016-09-28 | 中国科学院半导体研究所 | It is applicable to the programmable switch capacitance integrator of temperature sensor |
| US9362914B2 (en) * | 2014-05-13 | 2016-06-07 | Mediatek Inc. | Sampling circuit for sampling signal input and related control method |
| CN104168019B (en) * | 2014-07-22 | 2017-11-24 | 常州同惠电子股份有限公司 | Analog-digital converter and conversion method for digital multimeter |
| CN104184477B (en) * | 2014-09-01 | 2017-10-03 | 长沙景嘉微电子股份有限公司 | A kind of high-performance DAC-circuit for continuous type Sigma_Delta ADC |
| DE102015212848A1 (en) * | 2015-07-09 | 2017-01-12 | Forschungszentrum Jülich GmbH | Filter circuit for filtering an input signal of an analog-to-digital converter |
| US9906232B1 (en) * | 2017-03-10 | 2018-02-27 | Xilinx, Inc. | Resolution programmable SAR ADC |
| CN109253725B (en) * | 2017-07-13 | 2023-07-21 | 深迪半导体(绍兴)有限公司 | Signal processing system of MEMS gyroscope |
| CN111490787B (en) * | 2019-01-29 | 2023-07-21 | 江苏润石科技有限公司 | Sigma-delta modulator and method for reducing nonlinearity and gain error |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5461381A (en) * | 1993-12-13 | 1995-10-24 | Motorola, Inc. | Sigma-delta analog-to-digital converter (ADC) with feedback compensation and method therefor |
| CN1801627A (en) * | 2004-10-11 | 2006-07-12 | 因芬尼昂技术股份公司 | Analog-to-digital converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5461381A (en) * | 1993-12-13 | 1995-10-24 | Motorola, Inc. | Sigma-delta analog-to-digital converter (ADC) with feedback compensation and method therefor |
| CN1801627A (en) * | 2004-10-11 | 2006-07-12 | 因芬尼昂技术股份公司 | Analog-to-digital converter |
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