CN203747802U - Digital-to-analog conversion circuit - Google Patents

Abstract

The utility model discloses a digital-to-analog conversion circuit. The digital-to-analog conversion circuit comprises a first clock generating sub-circuit, a common-mode voltage generating sub-circuit and a conversion main circuit and further comprises a second clock generating sub-circuit and a reversal sub-circuit. The second clock generating sub-circuit is connected with the reversal sub-circuit and provided with a third output end and a fourth output end, and the third output end and the fourth output end output complementary clock pulses. When a sampling sub-circuit is in the sampling state, clock pulses output by the second clock generating sub-circuit are reversed. The reversal sub-circuit is respectively connected with the output end and the input end of an operational amplifier. When clock pulses output by the second clock generating sub-circuit are reversed, the directions of offset voltage and low-frequency noise generated by the operational amplifier are reversed through the reversal sub-circuit. Through the digital-to-analog conversion circuit, the power of the operational amplifier is reduced, direct-current offset and low-frequency 1/f noise of the operational amplifier are eliminated, and the signal-to-noise ratio of the digital-to-analog conversion circuit is improved.

Description

D/A converting circuit

Technical field

The utility model relates to integrated circuit fields, relates more specifically to a kind of D/A converting circuit.

Background technology

Along with the development of multimedia technology, increasing to the demand of audio digital to analog converter (DAC), the key that determines tonequality is D/A converting circuit (DAC) and the power amplifier circuit of master control decoding chip the inside.DAC is mainly responsible for the data flow of being convenient to data storage to convert analog signal to, and power amplifier circuit is mainly that the analog signal after DAC conversion is amplified to the power that can promote earphone or loudspeaker, therefore, DAC circuit is as important component part in audio frequency master control decoding chip, its power consumption, performance is the present stage audio digital to analog converter part of concern emphatically.

In traditional D/A converting circuit, in integral process, the charging and discharging currents that sampling capacitance and integrating capacitor need in charge transfer process is all provided by amplifier, has greatly increased the power consumption of amplifier; Slew Rate, the speed etc. of amplifier are had to higher requirement simultaneously.

Therefore, be necessary to provide a kind of improved D/A converting circuit to overcome above-mentioned defect.

Utility model content

The purpose of this utility model is to provide a kind of D/A converting circuit, and this D/A converting circuit has reduced the power of operational amplifier, has eliminated DC offset voltage and the low frequency 1/f noise of operational amplifier, has improved the signal to noise ratio of D/A converting circuit.

For achieving the above object, the utility model provides a kind of D/A converting circuit, comprise the first clock generating electronic circuit, common-mode voltage produces electronic circuit and conversion main circuit, described the first clock generating electronic circuit is connected with described conversion main circuit, to change the work of main circuit described in the control of generation clock pulse, and described the first clock generating electronic circuit has the first output and the second output, described the first output and the second output are exported complementary clock pulse, described common-mode voltage produces electronic circuit and is connected with described conversion main circuit, to produce the required common-mode voltage of the normal work of described conversion main circuit, described conversion main circuit converts the digital differential signal of outside input to analog difference signal output, described conversion main circuit also comprises sampling electronic circuit and integration electronic circuit, described integration electronic circuit is made up of integrating capacitor and operational amplifier, the input of described sampling electronic circuit is connected with external digital differential signal output, its output is connected with the input of described operational amplifier and one end of integrating capacitor respectively, the other end of described integrating capacitor be connected with described analog signal output and export conversion after analog difference signal, and described conversion main circuit is symmetrical arranged about described operational amplifier, wherein, also comprise that second clock produces electronic circuit and upset electronic circuit, described second clock produces electronic circuit and is connected with described upset electronic circuit, with the work of the electronic circuit that overturns described in the control of generation clock pulse, and described second clock produces electronic circuit and has the 3rd output and the 4th output, described the 3rd output and the 4th output are exported complementary clock pulse, and when described sampling electronic circuit is during in sample states, described second clock produces the 3rd output of electronic circuit and the clock pulse of the 4th output output is overturn, described upset electronic circuit is connected with output and the input of described operational amplifier respectively, in the time that described second clock produces the clock pulse upset of electronic circuit output, the offset voltage that described upset electronic circuit produces described operational amplifier and the upset of the direction of low-frequency noise.

Preferably, described upset electronic circuit comprises the first switch, second switch, the 3rd switch, the 4th switch, the 5th switch, the 6th switch, minion is closed and the 8th switch, one end of described the first switch and the 4th switch is connected with an output of described sampling electronic circuit jointly, one end of described second switch and the 3rd switch is connected with another output of described sampling electronic circuit jointly, the other end of described the first switch and the 3rd switch is connected with the normal phase input end of described operational amplifier jointly, the other end of described second switch and the 4th switch is connected with the inverting input of described operational amplifier jointly, one end that described the 5th switch and described minion are closed is connected with the reversed-phase output of described operational amplifier jointly, one end of described the 6th switch and the 8th switch is connected with the positive output end of described operational amplifier jointly, the other end of described the 5th switch and the 8th switch is connected with an output of described D/A converting circuit jointly, and the other end that described the 6th switch and minion are closed is connected with another output of described D/A converting circuit jointly.

Preferably, the control end of described the first switch, second switch, the 5th switch and the 6th switch is also connected with the 3rd output of described second clock generation electronic circuit respectively; Described the 3rd switch, the 4th switch, minion are closed and the control end of the 8th switch is also connected with the 4th output of described second clock generation electronic circuit respectively; And all closures in the time that the clock pulse of its control end is high level of switch described in each.

Compared with prior art, D/A converting circuit of the present utility model is owing to also comprising that described second clock produces electronic circuit and upset electronic circuit, and described upset electronic circuit is connected with output and the input of described operational amplifier respectively, in the time that described second clock produces the clock pulse upset of electronic circuit output, the offset voltage that described upset electronic circuit produces described operational amplifier and the upset of the direction of low-frequency noise; Thereby make within a clock cycle, the DC maladjustment of described operational amplifier input and low frequency 1/f noise thereof to be offset, also within a clock cycle, eliminate DC maladjustment and the low frequency 1/f noise thereof of operational amplifier input, further improved the signal to noise ratio of D/A converting circuit.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Brief description of the drawings

Fig. 1 is the structured flowchart of the utility model D/A converting circuit.

Fig. 2 is the circuit structure diagram of the utility model D/A converting circuit.

Fig. 3 is the equivalent operating state that second clock produces the front operational amplifier of clock pulse upset of electronic circuit output.

Fig. 4 is the equivalent operating state that second clock produces the rear operational amplifier of clock pulse upset of electronic circuit output.

Embodiment

With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of D/A converting circuit, and this D/A converting circuit has reduced the power of operational amplifier, has eliminated DC maladjustment and the low frequency 1/f noise of operational amplifier, has improved the signal to noise ratio of D/A converting circuit.

Please refer to Fig. 1, Fig. 1 is the structured flowchart of the utility model D/A converting circuit.As shown in the figure, D/A converting circuit of the present utility model comprises that conversion main circuit, the first clock generating electronic circuit, second clock produce electronic circuit, common-mode voltage produces electronic circuit and upset electronic circuit; Described conversion main circuit comprises sampling electronic circuit and integration electronic circuit, described sampling electronic circuit is connected with described integration electronic circuit and external digital differential signal output respectively, digital differential signal to outside digital differential signal output part output is sampled, and exports the signal after sampling to described integration electronic circuit; Described integration electronic circuit is also connected with analog signal output, and described integration electronic circuit carries out integration to the signal after sampling, and by the analog difference signal after described analog signal output output conversion; Described the first clock generating electronic circuit is connected with the sampling electronic circuit of described conversion main circuit, thus the work of the electronic circuit of sampling described in the clock pulse control of described the first clock generating electronic circuit output; Described common-mode voltage produces electronic circuit and is connected with the sampling electronic circuit of described conversion main circuit, normally works to ensure described sampling electronic circuit with output common mode voltage; Described second clock produces electronic circuit and is connected with described upset electronic circuit, to produce the work of the electronic circuit that overturns described in clock pulse control; Described upset electronic circuit is connected with the integration electronic circuit of described conversion main circuit, produce at described second clock under the control of electronic circuit, within a clock cycle, described upset electronic circuit overturns the direction of the offset voltage of described integration electronic circuit and low-frequency noise, make within a clock cycle, the offset voltage of described integration electronic circuit and low-frequency noise can be cancelled.

Particularly, please again in conjunction with reference to figure 2.CLK is the input clock of described the first clock generating electronic circuit, and described the first clock generating electronic circuit has the first output Φ 1 and the second output Φ 2, described the first output Φ 1 and the second output Φ 2 export complementary clock pulse,, in the time that described the first output Φ 1 is output as high level, described the second output Φ 2 is output as low level, and vice versa.CHOP_CLK is the input clock that described second clock produces electronic circuit, and described second clock produces electronic circuit and has the 3rd output Φ 3 and the 4th output Φ 4, described the 3rd output Φ 3 and the 4th output Φ 4 export complementary clock pulse,, in the time that described the 3rd output Φ 3 is output as high level, described the 4th output Φ 4 is output as low level, and vice versa; In the utility model, the upset that described second clock produces the pulse of electronic circuit output clock occurs in described sampling electronic circuit when outside digital differential signal is sampled.Described common-mode voltage produces electronic circuit and is connected with external power source, and output common mode voltage VCM.Described integration electronic circuit comprises integrating capacitor Cintp and operational amplifier OP; In preferred embodiment of the present utility model, described operational amplifier OP is Full differential operational amplifier.Described sampling electronic circuit comprises the 9th switch S 9, the tenth switch S the 10, the 11 switch S 11, twelvemo pass S12 and sampling capacitance Csp; One end (being the input of described sampling electronic circuit) of described the 9th switch S 9 is connected with external digital differential signal output, the other end is connected with one end that sampling capacitance Csp and twelvemo are closed S12, external digital differential signal output output digital differential signal VINP is to described sampling electronic circuit, and in the time of described the first switch S 1 closure, described sampling capacitance Csp samples to digital differential signal VINP, and the signal after sampling is kept; The other end of described sampling capacitance Csp is connected with one end of described the tenth switch S 10 and the 11 switch S 11, the other end of described the tenth switch S 10 is connected with the output that described common-mode voltage produces electronic circuit, and described common-mode voltage produces circuit by extremely described sampling electronic circuit of described the tenth switch S 10 output common mode voltage VCM; The other end (being the output of described sampling electronic circuit) of described the 11 switch S 11 is connected with one end of described integrating capacitor Cintp and the normal phase input end of operational amplifier OP, thereby in the time of described the 11 switch S 11 closure, described integrating capacitor Cintp and operational amplifier OP can carry out Integral Transformation to the digital differential signal after sampling; The other end of described integrating capacitor Cintp is connected with described analog signal output, thereby by this output, the analog difference signal VOUTN after Integral Transformation is exported.In the utility model, described conversion main circuit is symmetrical arranged about described operational amplifier OP, and described conversion main circuit comprises two groups of sampling electronic circuits and integrating capacitor, and is arranged at respectively the both sides of described operational amplifier OP; The sampling electronic circuit of organizing separately comprises the 13 switch S the 13, the 14 switch S the 14, the 15 switch S 15 and sampling capacitance Csn, and the integrating capacitor of organizing separately is Cintn; These two groups of structures are identical, annexation is identical, difference is only, external digital differential signal output output digital differential signal VINN is to described sampling electronic circuit, described the 15 other end of switch S 15 and one end of described integrating capacitor Cintn are connected with the inverting input of described operational amplifier OP, the other end of described integrating capacitor Cintn is connected with another output port of described analog signal output, and exports the analog difference signal VOUTP after conversion.Wherein, the control end of described the 9th switch S 9, the tenth switch S the 10, the 13 switch S 13 and the 14 switch S 14 is all connected with the first output Φ 1 of described the first clock generating electronic circuit, thus closure and the disconnection of the clock pulse control that described the first output Φ 1 exports switch described in each; Described the 11 switch S 11, twelvemo are closed the control end that S12, the 15 switch S 15 and sixteenmo close S16 and are all connected with the second output Φ 2 of described the first clock generating electronic circuit, thus closure and the disconnection of the clock pulse control that described the second output Φ 2 exports switch described in each; And described in each, all closures in the time that the clock pulse of its control end is high level of switch, disconnect when low level.Described upset electronic circuit comprises the first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4, the 5th switch S 5, the 6th switch S 6, minion pass S7 and the 8th switch S8; One end of described the first switch S 1 and the 4th switch S 4 is connected with the other end (output of the electronic circuit of sampling) of described the 11 switch S 11 jointly, one end of described second switch S2 and the 3rd switch S 3 is connected with the other end (another output of the electronic circuit of sampling) of described the 15 switch S 15 jointly, the other end of described the first switch S 1 and the 3rd switch S 3 is connected with the normal phase input end of described operational amplifier OP jointly, and the other end of described second switch S2 and the 4th switch S 4 is connected with the inverting input of described operational amplifier OP jointly; One end that described the 5th switch S 5 and described minion are closed S7 is connected with the reversed-phase output of described operational amplifier OP jointly, one end of described the 6th switch S 6 and the 8th switch S8 is connected with the positive output end of described operational amplifier OP jointly, the other end of described the 5th switch S 5 and the 8th switch S8 is connected with an output of described D/A converting circuit jointly, and the other end that described the 6th switch S 1 and minion are closed S1 is connected with another output port of described analog signal output jointly.In addition, the control end of described the first switch S 1, second switch S2, the 5th switch S 5 and the 6th switch S 6 is also connected with the 3rd output Φ 3 of described second clock generation electronic circuit respectively; The control end that described the 3rd switch S 3, the 4th switch S 4, minion are closed S7 and the 8th switch S8 is also connected with the 4th output Φ 4 of described second clock generation electronic circuit respectively; And described in each, all closures in the time that the clock pulse of its control end is high level of switch, disconnect when low level.

Introduce the course of work of the utility model D/A converting circuit below, in conjunction with Fig. 2-4.Because described conversion main circuit is symmetrical arranged about described operational amplifier OP, the structure of make to sample electronic circuit and integration electronic circuit is upper and lower symmetrical structure, when the course of work is introduced, only the first half is described, and the latter half is identical.Sampling instant, when the clock pulse that the first output Φ 1 exports is high level, the clock pulse that the second output Φ 2 exports is low level, the 9th switch S 9 and the tenth switch S 10 conductings, the 11 switch S 11 and twelvemo are closed S12 and are disconnected, now described sampling capacitance Csp samples to the digital differential signal VINP of input, and becomes electric charge to be kept in sampling capacitance Csp the voltage transitions obtaining after sampling.The integration moment, when the clock pulse that the first output Φ 1 exports is low level, the clock pulse that the second output Φ 2 exports is high level, the 9th switch S 9 and the tenth switch S 10 disconnect, the 11 switch S 11 and twelvemo are closed S12 closure, now sampling capacitance Csp is in parallel with integrating capacitor Cintp, and sampling capacitance Csp transfer part sampled charge is to integrating capacitor Cintp, and operational amplifier OP charges to the right pole plate of integrating capacitor Cintp simultaneously; In the utility model, described sampling capacitance Csp also provides Partial charge to integrating capacitor Cintp, thereby makes the charging of described integrating capacitor Cintp and not only rely on described operational amplifier OP, has therefore saved the driving power consumption of operational amplifier OP.

In the time that described second clock produces clock pulse that the 3rd output Φ 3 of electronic circuit exports and is high level, the clock pulse that the 4th output Φ 4 exports is low level, described the first switch S 1, second switch S2, the 5th switch S 5 and the 6th switch S 6 closures, described the 3rd switch S 3, the 4th switch S 4, minion close S7 and the 8th switch S8 disconnects; Now the operating state of described operational amplifier OP as shown in Figure 3, wherein Veq1 is that the clock pulse that the 3rd output Φ 3 exports is high level, the operational amplifier OP equivalent input noise of the clock pulse that the 4th output Φ 4 exports during for low level, vn1 is offset voltage and the low frequency 1/f noise of operational amplifier OP, vn2 is the equivalent input noise of the power amplifier that connects below of the utility model D/A converting circuit, if the gain of described operational amplifier OP is A, equivalent input noise so is now

$v_{\mathrm{qe}1}=v_{n1}+\frac{v_{n2}}{A}---\left(1\right)$

When described sampling electronic circuit is during in sample states, be that the clock pulse that the first output Φ 1 of described the first clock generating electronic circuit exports is high level, the clock pulse that the second output Φ 2 exports is low level, described second clock produces the clock pulse of electronic circuit output and overturns, also the clock pulse that the 3rd output Φ 3 that makes described second clock produce electronic circuit exports is low level, and the clock pulse that the 4th output Φ 4 exports is high level; And, described the first switch S 1, second switch S2, the 5th switch S 5 and the 6th switch S 6 disconnect, described the 3rd switch S 3, the 4th switch S 4, minion are closed S7 and the 8th switch S8 closure, now, the operating state of described operational amplifier OP as shown in Figure 4, wherein Veq2 is the equivalent input noise of described operational amplifier OP now, and now the equivalent input noise of operational amplifier OP is

$v_{\mathrm{qe}1}=-v_{n1}+\frac{v_{n2}}{A}---\left(2\right)$

, within a clock cycle, the average equivalent input noise Veq of the operational amplifier OP of D/A converting circuit of the present utility model is the mean value of formula (1) and formula (2) summation,

$v_{\mathrm{qe}}=\frac{v_{\mathrm{qe}1}+v_{\mathrm{eq}2}}{2}=\frac{v_{n2}}{A}---\left(3\right)$

Can be found out by (3) formula, described upset electronic circuit overturns to the input noise of described operational amplifier within every half clock cycle, thereby the offset voltage of described operational amplifier and low frequency 1/f noise sum are 0 within a clock cycle, make D/A converting circuit of the present utility model within a clock cycle, eliminate DC maladjustment and the low frequency 1/f noise thereof of operational amplifier OP, further improved the signal to noise ratio of D/A converting circuit.

In conjunction with most preferred embodiment, the utility model is described above, but the utility model is not limited to the embodiment of above announcement, and should contains the various amendments of carrying out according to essence of the present utility model, equivalent combinations.

Claims (3)

1. a D/A converting circuit, comprise the first clock generating electronic circuit, common-mode voltage produces electronic circuit and conversion main circuit, described the first clock generating electronic circuit is connected with described conversion main circuit, to change the work of main circuit described in the control of generation clock pulse, and described the first clock generating electronic circuit has the first output and the second output, described the first output and the second output are exported complementary clock pulse, described common-mode voltage produces electronic circuit and is connected with described conversion main circuit, to produce the required common-mode voltage of the normal work of described conversion main circuit, described conversion main circuit converts the digital differential signal of outside input to analog difference signal output, and comprise sampling electronic circuit and integration electronic circuit, described integration electronic circuit is made up of integrating capacitor and operational amplifier, the input of described sampling electronic circuit is connected with external digital differential signal output, its output is connected with the input of described operational amplifier and one end of integrating capacitor respectively, the other end of described integrating capacitor be connected with described analog signal output and export conversion after analog difference signal, and described conversion main circuit is symmetrical arranged about described operational amplifier, it is characterized in that, also comprise that second clock produces electronic circuit and upset electronic circuit, described second clock produces electronic circuit and is connected with described upset electronic circuit, with the work of the electronic circuit that overturns described in the control of generation clock pulse, and described second clock produces electronic circuit and has the 3rd output and the 4th output, described the 3rd output and the 4th output are exported complementary clock pulse, and when described sampling electronic circuit is during in sample states, described second clock produces the 3rd output of electronic circuit and the clock pulse of the 4th output output is overturn, described upset electronic circuit is connected with output and the input of described operational amplifier respectively, in the time that described second clock produces the clock pulse upset of electronic circuit output, the offset voltage that described upset electronic circuit produces described operational amplifier and the upset of the direction of low-frequency noise.

2. D/A converting circuit as claimed in claim 1, it is characterized in that, described upset electronic circuit comprises the first switch, second switch, the 3rd switch, the 4th switch, the 5th switch, the 6th switch, minion is closed and the 8th switch, one end of described the first switch and the 4th switch is connected with an output of described sampling electronic circuit jointly, one end of described second switch and the 3rd switch is connected with another output of described sampling electronic circuit jointly, the other end of described the first switch and the 3rd switch is connected with the normal phase input end of described operational amplifier jointly, the other end of described second switch and the 4th switch is connected with the inverting input of described operational amplifier jointly, one end that described the 5th switch and described minion are closed is connected with the reversed-phase output of described operational amplifier jointly, one end of described the 6th switch and the 8th switch is connected with the positive output end of described operational amplifier jointly, the other end of described the 5th switch and the 8th switch is connected with an output of described D/A converting circuit jointly, and the other end that described the 6th switch and minion are closed is connected with another output of described D/A converting circuit jointly.

3. D/A converting circuit as claimed in claim 2, is characterized in that, the control end of described the first switch, second switch, the 5th switch and the 6th switch is also connected with the 3rd output of described second clock generation electronic circuit respectively; Described the 3rd switch, the 4th switch, minion are closed and the control end of the 8th switch is also connected with the 4th output of described second clock generation electronic circuit respectively; And all closures in the time that the clock pulse of its control end is high level of switch described in each.