CN202957808U - Amplifier with ultralow dc offset in input end and A/D converter thereof - Google Patents
Amplifier with ultralow dc offset in input end and A/D converter thereof Download PDFInfo
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- CN202957808U CN202957808U CN201220578684.XU CN201220578684U CN202957808U CN 202957808 U CN202957808 U CN 202957808U CN 201220578684 U CN201220578684 U CN 201220578684U CN 202957808 U CN202957808 U CN 202957808U
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Abstract
The utility model relates to an amplifier with ultralow dc offset in the input end and an A/D converter thereof. The amplifier comprises a chopper modulator, a sampler, a CDS sampler and an amplifier/integrator, wherein a chopper demodulator is arranged behind the sampler in a circuit. The chopper modulator and the chopper demodulator can eliminate residual dc offset generated by electronic components as the CDS sampler because of nonideality of the electronic components; and reversely, the CDS sampler can eliminate residual dc offset of the chopper modulator and the chopper demodulator. Since the chopper modulator and demodulator modulates the residual dc offset of the electronic components as the CDS sampler to a clock frequency of 2*ck_chop to generate high-frequency modulation signals, input signals and the modulation signals are not overlapped in frequency domain, the demodulation signals can be eliminated by a low-pass filter connected in the output end of the amplifier with the ultralow dc offset in the input end, and thus the goal of removing residual dc offset of the sampling signals is achieved.
Description
Technical field
The utility model relates to the high-precision amplifying field, is specifically related to a kind of amplifier and A/D converter of ultralow input DC maladjustment.
Background technology
High-precision amplifying has low-down DC maladjustment (DC offset) as instrument amplifier (Instrument Amplifier) requires input, along with the difference of application, for the input direct-current of amplifier element, imbalance is limited in tens and does not wait to hundreds of microvolt (μ V).If the input at amplifier element is left intact, use the input DC maladjustment of the amplifier element that bipolar transistor is input stage between 1-3 millivolt (mV), use the amplifier element input DC maladjustment that the insulated gate metal-oxide-semiconductor is input stage up to 10 millivolts, therefore far can not satisfy the demand.
The method of the input DC maladjustment of reduction amplifier element commonly used has several as follows:
Method 1, measure in test process and the input DC maladjustment of amplifier element is finely tuned to (trim), and offset parameter is recorded on chip by the memory cell (OTP) of one-time programming.This way production cost is very high, and precision is limited, and can't eliminate the drift of DC maladjustment with temperature.
As shown in Figure 1, the method is modulated to the input DC maladjustment of amplifier element on a higher carrier frequency, thereby separates with low-frequency input signal for method 2, chopper amplification method (chopping).Although the method can be eliminated the temperature drift of DC maladjustment, in the output signal of amplifier element, with the carrier signal of two frequencys multiplication, also need by extra circuit for eliminating.
Method 3, correlation secondary sampling method (correlated double sampling, CDS), as shown in Figure 2,1 pair of input signal of capacitor C is sampled, when sampled clock signal ck1 is high, ck2 when low, capacitor C 2 is by the maintenance of sampling of the input DC offset voltage of 3 pairs of amplifier elements of capacitor C, and keeps a record on the trailing edge of sampled clock signal ck1.The method also can be eliminated the temperature drift of DC maladjustment, when clock signal ck2 be high, ck1 when low, capacitor C 2 is connected with amplifier element, the input DC offset voltage of its record has been offset the input DC maladjustment of amplifier element, thereby the input signal of amplifier element can be exaggerated to zero deflection.
The input DC maladjustment index that above method 2 and 3 can reach is tens to the hundreds of microvolt, remaining DC maladjustment is mainly from the imperfection of circuit, charge injection (charge injection) as sampling switch, the matching error of difference channel (mismatch), and amplifier working point again stable etc. after the each switch motion of circuit.In the new application of a lot of instrument amplifiers, require the input DC maladjustment of amplifier element lower than 10 microvolts, and require that very low temperature drift is arranged, and said method all can not reach such index.
The utility model content
The utility model is for the deficiencies in the prior art, proposed the amplifier of the ultralow input DC maladjustment of the residue DC maladjustment that a kind of imperfection of eliminating due to circuit element causes; And use the A/D converter of this amplifier as the front-end sampling circuit.
The technical solution of the utility model is as follows:
A kind of amplifier of ultralow input DC maladjustment is characterized in that: it comprises chopping modulation device, sampler, CDS sampler and the amplification/integrator connected successively, and a copped wave demodulator is arranged in the circuit after described sampler; Described chopping modulation device and copped wave demodulator use copped wave clock signal ck_chop, and described sampler and CDS sampler use sampled clock signal ck.
Described copped wave demodulator is arranged between described sampler and CDS sampler.
Described copped wave demodulator is arranged between described CDS sampler and described amplification/integrator.
Described copped wave demodulator is arranged on the output of described amplification/integrator.
The output of described amplification/integrator connects low pass filter.
The output of described copped wave demodulator connects low pass filter.
A kind of A/D converter that uses the amplifier of above-mentioned ultralow input DC maladjustment, it is characterized in that: it comprises analog to digital converter, and the signal input part of described analog to digital converter and reference voltage input are connected respectively the amplifier of a described ultralow input DC maladjustment.
The amplifier of described ultralow input DC maladjustment comprises chopping modulation device, sampler, CDS sampler and the amplification/integrator connected successively, and a copped wave demodulator is arranged in the circuit after described sampler.
Technique effect of the present utility model is as follows:
The amplifier of a kind of ultralow input DC maladjustment of the present utility model, comprise the chopping modulation device, sampler, CDS sampler and the amplification/integrator that connect successively, and a copped wave demodulator is arranged in the circuit after sampler.Wherein chopping modulation device and copped wave demodulator are eliminated the residue DC maladjustment that the circuit element such as CDS sampler produces due to the imperfection of circuit element; Conversely, the CDS sampler also can be eliminated the residue DC maladjustment of chopping modulation device and copped wave demodulator.By above-mentioned setting, can reach the target that long-time average amplifier element equivalence input DC maladjustment is less than 10 μ V.
Because chopping modulation device and copped wave demodulator are modulated to the residue DC maladjustment of the circuit elements such as CDS sampler on the clock frequency of 2 * ck_chop, generate the modulation signal of high frequency, so input signal and modulation signal not overlapping on frequency domain.The low pass filter that modulation signal just can connect by the output of the amplifier in whole ultralow input DC maladjustment is like this eliminated, thereby has reached the purpose of removing sampled signal residue DC maladjustment.
Due to the rising edge of the rising of copped wave clock signal ck_chop or trailing edge and sampled clock signal ck or descend and overlap, can guarantee that like this, when the sampled point of sampler, copped wave clock signal ck_chop is complete stability.And in the time period before the arrival sampled point, after chopping modulation device and copped wave demodulator switch, the working point of amplifier element re-establish the quality that can not affect output signal, such arrangement has been eliminated traditional chopper circuit because the signal residue DC maladjustment of bringing is set up in the amplifier element working point.
The accompanying drawing explanation
Fig. 1 is the basic circuit diagram of chopper-type amplifier
Fig. 2 is the structural representation that uses the correlation secondary sampling amplifier
Fig. 3 is the structural representation of embodiment 1 of the present utility model
Fig. 4 is the time diagram of embodiment 1 of the present utility model
Fig. 5 is the structural representation of embodiment 2 of the present utility model
Fig. 6 is the structural representation of embodiment 3 of the present utility model
Fig. 7 is the specific implementation circuit diagram of the utility model embodiment 1
Fig. 8 is the time diagram of the specific implementation circuit of the utility model embodiment 1
Fig. 9 is Application Example 1 of the present utility model, embodiment 2 or the embodiment 3 high precision analogue change-over circuit schematic diagram as the front-end sampling circuit
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Specific embodiment described herein is only in order to explain the utility model, and is not used in restriction the utility model.
The amplifier basic principle of ultralow input DC maladjustment of the present utility model is to use chopping modulation demodulator circuit and CDS(correlation secondary sampling in circuit simultaneously) circuit, allow their eliminate each other the residue DC maladjustment that the imperfection due to circuit element produces, thereby make whole amplifying circuit reach higher precision.Eliminate sample rate current and CDS circuit residue DC maladjustment by the chopping modulation demodulator circuit, by the residue DC maladjustment of CDS circuit for eliminating chopping modulation circuit, the chopping modulation signal of two frequencys multiplication of carrying in the output signal of last amplifier is eliminated by a low pass filter.
Embodiment 1:
As shown in Figure 3, Figure 4, the amplifier of ultralow input DC maladjustment comprises chopping modulation device 1, sampler 2, copped wave demodulator 3, CDS sampler 4 and the amplification/integrator 5 connected successively, wherein chopping modulation device 1 and copped wave demodulator 3 use copped wave clock signal ck_chop, and sampler 2 and CDS sampler 4 use sampled clock signal ck.Input signal is successively through input chopping modulation device 1, sampler 2, copped wave demodulator 3 and CDS sampler 4, finally enters and amplification and the output of amplify/integrator 5 settling signals.In the present embodiment, chopping modulation device 1 and copped wave demodulator 3 are separately positioned on input and the output of sampler 2.Amplification/integrator 5 larger input DC maladjustment own are sampled and removed by CDS sampler 4, and the residue DC maladjustment that in sampler 2, the imperfection of circuit element produces, as switch-charge is injected and difference channel mismatch and the residue DC maladjustment that produces, by chopping modulation device 1 and copped wave demodulator 3, be modulated on the clock frequency of 2 * ck_chop, generate the modulation signal of high frequency.
The input of CDS sampler 4 subsequently will comprise input signal and above-mentioned modulation signal simultaneously, due to input signal and modulation signal not overlapping on frequency domain, therefore modulation signal is easy to low pass filter 6 removals that be exaggerated/integrator 5 outputs arrange, no longer affect the input signal of low frequency, thereby reached the purpose of removing sampled signal residue DC maladjustment.Because residue DC maladjustment itself is less, tens to hundreds of μ V, can make to remain DC maladjustment by chopping modulation and cut down again 1-2 the order of magnitude, reach the target that system equivalence input DC maladjustment is less than 10 μ V.
Embodiment 2:
As shown in Figure 4, Figure 5, the amplifier of ultralow input DC maladjustment comprises chopping modulation device 1, sampler 2, CDS sampler 4, copped wave demodulator 3 and the amplification/integrator 5 connected successively, wherein chopping modulation device 1 and copped wave demodulator 3 use copped wave clock signal ck_chop, and sampler 2 and CDS sampler 4 use sampled clock signal ck.Input signal is successively through input chopping modulation device 1, sampler 2, CDS sampler 4 and copped wave demodulator 3, finally enters and amplification and the output of amplify/integrator 5 settling signals.In the present embodiment, sampler 2 and CDS sampler 4 are arranged between chopping modulation device 1 and copped wave demodulator 3, principle based on similarly to Example 1, in sampler 2 and CDS sampler 4 circuit element the residue DC maladjustment will be modulated onto on the frequency of 2 * ck_chop, generate the modulation signal of high frequency.
The input of amplification/integrator 5 subsequently will comprise input signal and above-mentioned modulation signal simultaneously, due to input signal and modulation signal not overlapping on frequency domain, therefore modulation signal is easy to low pass filter 6 removals that be exaggerated/integrator 5 outputs arrange, no longer affect the input signal of low frequency, thereby reached the purpose of removing residue DC maladjustment in sampled signal.
Embodiment 3:
As shown in Fig. 4, Fig. 6, the amplifier of ultralow input DC maladjustment comprises chopping modulation device 1, sampler 2, CDS sampler 4, amplification/integrator 5 and the copped wave demodulator 3 connected successively, wherein chopping modulation device 1 and copped wave demodulator 3 use copped wave clock signal ck_chop, and sampler 2 and CDS sampler 4 use sampled clock signal ck.Input signal through sampling and the amplification of input chopping modulation device 1, sampler 2, CDS sampler 4, amplification/integrator 5 settling signals, is finally exported by copped wave demodulator 3 successively.In the present embodiment, sampler 2, CDS sampler 4, amplification/integrator 5 all are arranged between chopping modulation device 1 and copped wave demodulator 3, principle based on similarly to Example 1, the all residue DC maladjustment of sampler 2, CDS sampler 4 and amplification/integrator 5 all can be modulated onto on the frequency of 2 * ck_chop, generate the modulation signal of high frequency.
The output signal of the amplifier of whole ultralow input DC maladjustment will comprise amplifying signal and the above-mentioned modulation signal of input signal subsequently, because amplifying signal and the modulation signal of input signal are not overlapping on frequency domain, therefore modulation signal is easy to be removed with low pass filter 6 by the circuit of back, no longer affect the amplifying signal of the input signal of low frequency, thereby reached the purpose of removing the residue DC maladjustment.
Above-mentioned three embodiment have all illustrated how to use chopping modulation device 1, copped wave demodulator 3 is eliminated the circuit element residue DC maladjustment such as CDS sampler 4, and conversely, CDS sampler 4 also can be eliminated the residue DC maladjustment of chopping modulation device 1, copped wave demodulator 3.As shown in Figure 4, by the choosing of copped wave clock signal ck_chop frequency, sampled clock signal ck frequency, phase place, can make the imperfection of chopping modulation device 1, copped wave demodulator 3 not affect the quality of output signal, its choosing method comprises:
1) in above-mentioned three embodiment, mention, if selecting sampling clock signal ck frequency is higher than the copped wave clock signal ck_chop frequency of 2 times, the modulation signal of 2 frequencys multiplication (2 * ck_chop) that chopping modulation device 1, copped wave demodulator 3 produce is not overlapping with input signal on frequency domain, thereby the low pass filter 6 that can connect by the output of the amplifier in ultralow input DC maladjustment is eliminated modulation signal;
2) sequential of sampled clock signal ck is associated with the sequential of described copped wave clock signal ck_chop;
3) rising of copped wave clock signal ck_chop or trailing edge are overlapped with rising edge or the decline (i.e. sampling edge) of sampled clock signal ck, while with this, guaranteeing the sampled point (trailing edge of sampled clock signal ck) at sampler 2, copped wave clock signal ck_chop is complete stability; Like this in the time period before arriving sampled point, after chopping modulation device 1 and copped wave demodulator 3 switches, the working point of amplifier element 6 re-establish the quality that can not affect output signal.
As shown in Figure 7, Figure 8, the specific implementation circuit of embodiment 1 has been used a slower copped wave clock signal ck_chop, and a sampled clock signal ck faster, and wherein the frequency of sampled clock signal ck is the integral multiple of copped wave clock signal ck_chop.Because input signal is differential signal, therefore whole circuit realizes it being also differential mode.Input signal is by input inp, the inn input of chopping modulation device 1, according to the frequency of copped wave clock signal ck_chop by input signal positive and anti-phase between switching, the voltage signal after switching is by two output vinp and the vinn output of chopping modulation device 1.
Two inputs of sampler 2 connect respectively output vinp and vinn, according to the frequency of sampled clock signal ck, the two-way input signal sampled respectively, and two output v1p and the v1n output by sampler 2 by the input sample signal.Due to chopping modulation device 1 output be differential signal, so sampler 2 comprises a difference sample circuit.Wherein the sample circuit of positive phase input signal one side comprises the input sample capacitor C 1 of K switch 1～K4 and a sampling maintenance input signal, and K switch 1～K4 is associated with clock signal ck.。The input of K switch 5 connects output vinp, K switch 1, input sample capacitor C 1, K switch 4 series connection, the output v1p that the output of K switch 4 is sampler 2; By K switch 2 ground connection, pass through K switch 3 ground connection between input sample capacitor C 1 and K switch 4 between K switch 1 and input sample capacitor C 1.
According to choosing of ck clock polarity, the input vinp of sampler 2 to the polarity of output v1p can be forward or oppositely.But no matter input vinp is positive or upset to output v1p, these two kinds of working methods all have the characteristic of the ultralow input DC maladjustment that the utility model has equally.
Two inputs of copped wave demodulator 3 connect respectively output v1p and v1n, the frequency of copped wave clock signal ck_chop will lack of proper care sampled signal positive and anti-phase between switching, the imbalance sampled signal after switching is by two output v2p and the v2n output of copped wave demodulator 3.
Two inputs of CDS sampler 4 connect respectively output v2p and v2n, according to the frequency of sampled clock signal ck, the input DC maladjustment of amplifier element 6 is sampled, the sampled signal of lacking of proper care afterwards is by input opinp and the opinn output of amplifier element 6.CDS sampler 4 comprises the identical CDS circuit of two-strip structure, is divided into the CDS circuit of positive phase input signal one side and the CDS circuit of negative input signal one side.Wherein the CDS circuit of positive phase input signal one side comprises the imbalance sampling capacitance Ccds of K switch 5～K7 and an input DC maladjustment that keeps amplifier element 6 for sampling, K switch 5, and K6 is associated with clock signal ck with K7.K switch 5 one ends connect output v2p, and the other end connects the integrating capacitor C2 in amplification/integrator 5; Imbalance sampling capacitance Ccds mono-end connects output v2p, and the other end connects the input opinp of amplifier element 6; K switch 5 is by K switch 6 ground connection, and input opinp is connected between K switch 5 and integrating capacitor C2 by K switch 7.According to the operation principle of foregoing CDS correlation secondary sampling method, the input signal of amplifier element 6 can be exaggerated to zero deflection in amplifier element 6.
Amplification/integrator 5 comprises amplifier element 6 and integrating capacitor C2, and two inputs of amplifier element 6 connect respectively input opinp and opinn, and 6 pairs of inputs of amplifier element signal is wherein amplified, and by output opoutp and opoutn output.When controlling the copped wave clock signal ck_chop signal timing upset of chopping modulation device 1 and copped wave demodulator 3, input signal passes through positive and anti-phase sampler 2 and CDS sampler 4 in turn, the imperfection of their inside and matching error will be cancelled out each other, long-time average out to zero.
The basic principle of the described example 1,2,3 of Fig. 3-Fig. 6, and the physical circuit realization of Fig. 7-8 statement, can directly be used as the front-end sampling circuit of standard module transducer (ADC).In addition, they also can be used in the over-sampling analog-to-digital conversion, comprise SIGMA-Delta (Sigma-Delta) analog to digital converter.As shown in Figure 9, when embodiment 1 of the present utility model, embodiment 2 or embodiment 3 are applied in the analog circuit of high accuracy SIGMA-Delta (Sigma-Delta) analog to digital converter (ADC) front end, signal input part is used the amplifier sampling of the ultralow input DC maladjustment of embodiment 1, embodiment 2 or embodiment 3, and reference voltage input is also used the amplifier sampling of the ultralow input DC maladjustment of embodiment 1, embodiment 2 or embodiment 3.Input (virtually) v2p(v2n of sampled signal and reference voltage signal CDS sampler in the amplifier of ultralow input DC maladjustment) realize current subtraction can completing needed negative feedback loop.Because the sample circuit of sampled signal and reference voltage signal has all used the way of reduction offset voltage shown in this article, therefore whole analog to digital converter has also had same ultralow input direct-current Misalignment Characteristics.
It should be pointed out that the above embodiment can make those skilled in the art's comprehend the utility model create, and creates but limit never in any form the utility model.Therefore; although this specification is created and is had been described in detail the utility model with reference to drawings and Examples; but; those skilled in the art are to be understood that; still can create and modify or be equal to replacement the utility model; in a word, all do not break away from technical scheme and the improvement thereof of the spirit and scope of the utility model creation, and it all should be encompassed in the utility model and create in the middle of the protection range of patent.
Claims (8)
1. the amplifier of a ultralow input DC maladjustment is characterized in that: it comprises chopping modulation device, sampler, CDS sampler and the amplification/integrator connected successively, and a copped wave demodulator is arranged in the circuit after described sampler; Described chopping modulation device and copped wave demodulator use copped wave clock signal ck_chop, and described sampler and CDS sampler use sampled clock signal ck.
2. the amplifier of a kind of ultralow input DC maladjustment as claimed in claim 1, it is characterized in that: described copped wave demodulator is arranged between described sampler and CDS sampler.
3. the amplifier of a kind of ultralow input DC maladjustment as claimed in claim 1, it is characterized in that: described copped wave demodulator is arranged between described CDS sampler and described amplification/integrator.
4. the amplifier of a kind of ultralow input DC maladjustment as claimed in claim 1, it is characterized in that: described copped wave demodulator is arranged on the output of described amplification/integrator.
5. the amplifier of a kind of ultralow input DC maladjustment as described as one of claim 1-3, is characterized in that: the output connection low pass filter of described amplification/integrator.
6. the amplifier of a kind of ultralow input DC maladjustment as claimed in claim 4, is characterized in that: the output connection low pass filter of described copped wave demodulator.
7. the A/D converter of the amplifier of a use ultralow input DC maladjustment as described as claim 1-6, it is characterized in that: it comprises analog to digital converter, and the signal input part of described analog to digital converter and reference voltage input are connected respectively the amplifier of a described ultralow input DC maladjustment.
8. a kind of A/D converter as claimed in claim 7, it is characterized in that: the amplifier of described ultralow input DC maladjustment comprises chopping modulation device, sampler, CDS sampler and the amplification/integrator connected successively, and a copped wave demodulator is arranged in the circuit after described sampler.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201220578684.XU CN202957808U (en) | 2012-11-05 | 2012-11-05 | Amplifier with ultralow dc offset in input end and A/D converter thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201220578684.XU CN202957808U (en) | 2012-11-05 | 2012-11-05 | Amplifier with ultralow dc offset in input end and A/D converter thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138760A (en) * | 2012-11-05 | 2013-06-05 | 戴祖渝 | Amplifier with ultralow direct current (DC) offset at input end and analog/digital (A/D) converter |
| CN104682957A (en) * | 2013-11-29 | 2015-06-03 | 展讯通信（上海）有限公司 | Sigma-delta analog-to-digital converter |
| CN105158672A (en) * | 2015-08-24 | 2015-12-16 | 北京中科汉天下电子技术有限公司 | Test circuit |
| CN105306845A (en) * | 2015-11-19 | 2016-02-03 | 电子科技大学 | Correlated double-sampling circuit capable of cancelling offset |
| CN105651452A (en) * | 2016-02-22 | 2016-06-08 | 武汉市聚芯微电子有限责任公司 | Pressure sensor signal readout circuit capable of adjusting zero offset |
| CN109450384A (en) * | 2018-09-20 | 2019-03-08 | 天津大学 | A kind of reading circuit based on chopping modulation and correlated-double-sampling |
-
2012
- 2012-11-05 CN CN201220578684.XU patent/CN202957808U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138760A (en) * | 2012-11-05 | 2013-06-05 | 戴祖渝 | Amplifier with ultralow direct current (DC) offset at input end and analog/digital (A/D) converter |
| CN104682957A (en) * | 2013-11-29 | 2015-06-03 | 展讯通信（上海）有限公司 | Sigma-delta analog-to-digital converter |
| CN104682957B (en) * | 2013-11-29 | 2018-10-16 | 展讯通信（上海）有限公司 | Quadrature Sigma-Delta analog-digital converter |
| CN105158672A (en) * | 2015-08-24 | 2015-12-16 | 北京中科汉天下电子技术有限公司 | Test circuit |
| CN105306845A (en) * | 2015-11-19 | 2016-02-03 | 电子科技大学 | Correlated double-sampling circuit capable of cancelling offset |
| CN105306845B (en) * | 2015-11-19 | 2018-04-06 | 电子科技大学 | A kind of correlated double sampling circuit for eliminating imbalance |
| CN105651452A (en) * | 2016-02-22 | 2016-06-08 | 武汉市聚芯微电子有限责任公司 | Pressure sensor signal readout circuit capable of adjusting zero offset |
| CN109450384A (en) * | 2018-09-20 | 2019-03-08 | 天津大学 | A kind of reading circuit based on chopping modulation and correlated-double-sampling |
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Owner name: GUANGDONG XIDIWEI ELECTRONIC CO., LTD. Free format text: FORMER OWNER: DAI ZUYU Effective date: 20140523 |
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Effective date of registration: 20140523 Address after: 528200, B, building 1, building 1, Tian An Digital Town, No. 509, Ping Lu, Nanhai, Foshan, Guangdong, Guicheng Patentee after: GUANGDONG HALO MICROELECTRONICS Co.,Ltd. Address before: 528200, B, building 1, building 1, Tian An Digital Town, No. 509, Ping Lu, Nanhai, Foshan, Guangdong, Guicheng Patentee before: Dai Zuyu |
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