CN201576679U - 闪存芯片堆栈结构 - Google Patents

闪存芯片堆栈结构 Download PDF

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CN201576679U
CN201576679U CN2009203067760U CN200920306776U CN201576679U CN 201576679 U CN201576679 U CN 201576679U CN 2009203067760 U CN2009203067760 U CN 2009203067760U CN 200920306776 U CN200920306776 U CN 200920306776U CN 201576679 U CN201576679 U CN 201576679U
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crystal grain
control unit
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chip stack
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梁裕民
朱贵武
卢旋瑜
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Aflash Tech Co Ltd
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Mao Bang Electronic Co Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2225/06503—Stacked arrangements of devices
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Abstract

一种闪存芯片堆栈结构，其包含一控制单元以及多数相互堆栈的晶粒，各晶粒两面上分别设有相互导通的电源接脚、接地接脚、输入/出接脚、选择接脚及待命/忙碌接脚，各电源、接地及输入/出接脚并联后与控制单元连接，而各选择接脚及待命/忙碌接脚分别直接与控制单元连接，且选择接脚及待命/忙碌接脚间分别连接有导线部，可于各晶粒布局时依不同层叠将所需的导线部加以断开；另亦可于各选择接脚及待命/忙碌接脚间分别连接有断线部，可于布局将所需的断线部加以连接。藉此，可使各晶粒达到易于进行线路布局、易于生产管理、降低制作成本及符合订制化需求的功效。

Description

闪存芯片堆栈结构
技术领域
本实用新型涉及一种闪存芯片堆栈结构，尤指一种可使各晶粒达到易于进行线路布局、易于生产管理、降低制作成本及符合订制化需求的功效者。
背景技术
按，一般已用闪存晶粒是于一面上设有电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚，而当进行各记忆晶粒堆栈封装时，依所需以打线的方式将各接脚的脚位相互连接，藉以达到记忆晶粒的封装。
但是由于已用的记忆晶粒堆栈封装以打线的方式将各接脚的脚位相互连接，虽然接线方式较具有弹性，但对于记忆芯片颗粒的堆栈封装而言，则需在该记忆晶粒的整个晶圆上依不同的层叠制作出不同的线路，使得制作生产晶圆时所用的光罩设计较为复杂，而增加生产管理的难度，并使得制作成本增加，更无法依据客户的特殊需求进行制作。
实用新型内容
本实用新型的主要目的在于，提供一种闪存芯片堆栈结构，其可使各晶粒达到易于进行线路布局、易于生产管理、降低制作成本及符合客制化需求的功效。
为达上述目的，本实用新型所采用的第一种技术方案为：一种闪存芯片堆栈结构，其包括：一控制单元；以及多数相互堆栈的晶粒，且各晶粒两面上分别设有多数相互导通的电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚，各电源接脚、接地接脚及输入/出接脚相互并联后与控制单元连接，而各选择接脚及待命/忙碌接脚分别直接与控制单元连接，且选择接脚及待命/忙碌接脚之间分别连接有导线部，可于各晶粒布局时依不同层叠将所需的导线部加以断开。
为达上述目的，本实用新型所采用的第二种技术方案为：一种闪存芯片堆栈结构，其包括：一控制单元；以及多数相互堆栈的晶粒，且各晶粒两面上分别设有多数相互导通的电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚，各电源接脚、接地接脚及输入/输出接脚相互并联后与控制单元连接，而各选择接脚及待命/忙碌接脚分别直接与控制单元连接，且选择接脚及待命/忙碌接脚之间分别连接有断线部，可于各晶粒布局时依不同层叠将所需的断线部加以连接。
本实用新型的进一步改进为：上述两种方案中的控制单元为控制芯片。
本实用新型的进一步改进为：各晶粒为闪存晶粒。
本实用新型的进一步改进为：各晶粒两面上的各电源接脚、接地接脚、输入/出接脚、选择接脚及待命/忙碌接脚连接分别以设于侧缘导通部相互导通。
本实用新型的进一步改进为：各导线部以激光切断方式加以断开。
与现有技术相比，本实用新型所具有的有益效果为：本实用新型各晶粒两面上分别设有多数相互导通的电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚，各电源接脚、接地接脚及输入/输出接脚相互并联后与控制单元连接，而各选择接脚及待命/忙碌接脚分别直接与控制单元连接，且选择接脚及待命/忙碌接脚之间分别连接有导线部，可于各晶粒布局时依不同层叠将所需的导线部加以断开；另亦可于各选择接脚及待命/忙碌接脚之间分别连接有断线部，可于布局将所需的断线部加以连接，使各晶粒达到易于进行线路布局、易于生产管理、降低制作成本及符合客制化需求的功效。
附图说明
图1为本实用新型第一实施例的立体分解示意图。
图2为本实用新型第一实施例的方块示意图。
图3为本实用新型第一实施例的选择接脚及待命/忙碌接脚连接状态示意图。
图4为本实用新型第一实施例的选择接脚及待命/忙碌接脚断开状态示意图。
图5为本实用新型第二实施例的选择接脚及待命/忙碌接脚断开状态示意图。
图6为本实用新型第二实施例的选择接脚及待命/忙碌接脚连接状态示意图。
标号说明
控制单元1
晶粒2
电源接脚21
接地接脚22
输入/输出接脚23
选择接脚24
待命/忙碌接脚25
导线部26
导通部27
断线部28
导体29
具体实施方式
请参阅图1、图2、图3及图4所示，分别为本实用新型第一实施例的立体分解示意图、本实用新型第一实施例的方块示意图、本实用新型第一实施例的选择接脚及待命/忙碌接脚连接状态示意图及本实用新型第一实施例的选择接脚及待命/忙碌接脚断开状态示意图。如图所示：本实用新型为一种闪存芯片堆栈结构，其至少由一控制单元1以及多数晶粒2所构成。
上述所提的控制单元1可为控制芯片。
各晶粒2可为相互堆栈的闪存晶粒，且各晶粒2两面上分别具有多数电源接脚21、接地接脚22、输入/输出接脚23、选择接脚24及待命/忙碌接脚25，各电源接脚21、接地接脚22及输入/输出接脚23相互并联后与控制单元1连接，而各选择接脚24及待命/忙碌接脚25分别直接与控制单元1连接，且选择接脚24及待命/忙碌接脚25之间分别连接有导线部26，并于各晶粒2的侧缘分别具有多数与各电源接脚21、接地接脚22、输入/出接脚23、选择接脚24及待命/忙碌接脚25连接的导通部27。如是，藉由上述结构构成一全新的闪存芯片堆栈结构。
当本实用新型于布局设计时，可先将多数晶粒2相互堆栈，并依不同层叠进布局时的所需将各导通部27进行相互导通，而让各相对应或不相对应晶粒2两面上的电源接脚21、接地接脚22、输入/出接脚23、选择接脚24及待命/忙碌接脚25依需求加以导通或不导通，之后再于各晶粒2上依布局时的不同层叠所需将导线部26以激光切断方式加以断开；如此，即可使各晶粒2达到易于进行线路布局、易于生产管理、降低制作成本及符合订制化需求的功效。
请参阅图5及图6所示，分别为本实用新型第二实施例的选择接脚及待命/忙碌接脚断开状态示意图及本实用新型第二实施例的选择接脚及待命/忙碌接脚连接状态示意图。如图所示：本实用新型除上述第一实施例所提结构型态之外，更可以本第二实施例的结构作为线路布局的型态，而其所不同之处在于，各选择接脚24及待命/忙碌接脚25之间分别连接有断线部28，可于各晶粒2布局时依不同层叠将所需的断线部28以导体29焊接方式或导体29印刷方式加以连接；如此，同样可达到上述所提第一实施例中所提的功效。
综上所述，本实用新型闪存芯片堆栈结构可有效改善已用的种种缺点，可使各晶粒达到易于进行线路布局、易于生产管理、降低制作成本及符合订制化需求的功效，进而使本实用新型的产生能更进步、更实用、更符合使用者所须，确已符合实用新型专利申请要件，爰依法提出专利申请。
惟以上所述，仅为本实用新型的较佳实施例而已，当不能以此限定本实用新型实施范围；故，凡依本实用新型权利要求书及实用新型说明书内容所作的简单的等效变化与修饰，皆应仍属本实用新型专利涵盖的范围内。

Claims (11)

1.一种闪存芯片堆栈结构，其特征在于包括：一控制单元；以及多数相互堆栈的晶粒，且各晶粒两面上分别设有多数相互导通的电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚，各电源接脚、接地接脚及输入/出接脚相互并联后与控制单元连接，而各选择接脚及待命/忙碌接脚分别直接与控制单元连接，且选择接脚及待命/忙碌接脚之间分别连接有导线部，可于各晶粒布局时依不同层叠将所需的导线部加以断开。
2.根据权利要求1所述的闪存芯片堆栈结构，其特征在于，该控制单元为控制芯片。
3.根据权利要求1所述的闪存芯片堆栈结构，其特征在于，各晶粒为闪存晶粒。
4.根据权利要求1所述的闪存芯片堆栈结构，其特征在于，各晶粒两面上的各电源接脚、接地接脚、输入/出接脚、选择接脚及待命/忙碌接脚连接分别以设于侧缘导通部相互导通。
5.根据权利要求1所述的闪存芯片堆栈结构，其特征在于，各导线部以激光切断方式加以断开。
6.一种闪存芯片堆栈结构，其特征在于包括：一控制单元；以及多数相互堆栈的晶粒，且各晶粒两面上分别设有多数相互导通的电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚，各电源接脚、接地接脚及输入/输出接脚相互并联后与控制单元连接，而各选择接脚及待命/忙碌接脚分别直接与控制单元连接，且选择接脚及待命/忙碌接脚之间分别连接有断线部，可于各晶粒布局时依不同层叠将所需的断线部加以连接。
7.根据权利要求6所述的闪存芯片堆栈结构，其特征在于，该控制单元为控制芯片。
8.根据权利要求6所述的闪存芯片堆栈结构，其特征在于，各晶粒为闪存晶粒。
9.根据权利要求6所述的闪存芯片堆栈结构，其特征在于，各晶粒两面上的各电源接脚、接地接脚、输入/输出接脚、选择接脚及待命/忙碌接脚连接分别以设于侧缘导通部相互导通。
10.根据权利要求6所述的闪存芯片堆栈结构，其特征在于，各断线部以导体焊接方式加以连接。
11.根据权利要求6所述的闪存芯片堆栈结构，其特征在于，各断线部以导体印刷方式加以连接。
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CN104425012A (zh) * 2013-08-30 2015-03-18 北京兆易创新科技股份有限公司 一种nand闪存单元

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