CN201435021Y - Reference voltage element - Google Patents

Abstract

The utility model provides a reference voltage element, comprising a depletion-mode PMOS transistor and an enhancement-mode PMOS transistor, wherein the depletion-mode PMOS transistor and the enhancement-mode PMOS transistor are both superficial conducting channel transistors, and have the same ion distribution in the conducting channels, the grid electrode of the depletion-mode PMOS transistor isP-type doping, and the grid electrode of the enhancement-mode PMOS transistor is N-type doping. The threshold voltage of the reference voltage element is not easy to change with temperature, and hasgood stability.

Description

The reference voltage device

Technical field

The utility model relates to technical field of semiconductors, particularly a kind of reference voltage device.

Background technology

At present, the reference voltage device is widely used in the integrated circuit (IC) products, is used for providing reference voltage for integrated circuit (IC) products.The stability of integrated circuit (IC) products directly depends on the stability of described reference voltage device, and for example the reference voltage level that is subjected to influences such as temperature, environment and provides when the reference voltage device changes, and will inevitably make the performance of integrated circuit (IC) products change.

Fig. 1 is a kind of circuit diagram of reference voltage device, and Fig. 2 is a kind of cross-sectional view of existing reference voltage device shown in Figure 1.With reference to illustrated in figures 1 and 2, grid and the source electrode of depletion type PMOS transistor P1 couple, grid and the drain electrode of enhancement mode PMOS transistor P2 couple, and the source electrode of depletion type PMOS transistor P1 drain electrode and enhancement mode PMOS transistor P2 couples the output terminal of reference voltage device.Wherein, depletion type PMOS transistor P1 is a depletion type PMOS transistor, and is buried channel technology, and adopts N type polysilicon as grid; Enhancement mode PMOS transistor P2 is an enhancement mode, and is surface channel technology, and adopts N type polysilicon as grid.Because it is different to distribute in the channel dopant of depletion type PMOS transistor P1 and enhancement mode PMOS transistor P2, so threshold voltage and mutual conductance differ greatly with variation of temperature.

Therefore above-mentioned existing reference voltage device changes easily with the variation of temperature threshold voltage, so less stable.

The utility model content

The purpose of this utility model provides a kind of reference voltage device, has improved the stability of reference voltage device.

In order to achieve the above object, the utility model provides a kind of reference voltage device, comprise depletion type PMOS transistor and enhancement mode PMOS transistor, depletion type PMOS transistor and enhancement mode PMOS transistor are all the surface conduction channel transistor npn npn, and the ion distribution in depletion type PMOS transistor and the transistorized conducting channel of enhancement mode PMOS is identical, wherein the transistorized grid of depletion type PMOS mixes for the P type, and the transistorized grid of enhancement mode PMOS mixes for the N type.

Preferably, the transistorized grid side of depletion type PMOS resistance is at 2000ohm ± 200ohm, and the transistorized threshold voltage of depletion type PMOS is at 0.4V ± 0.1V; The transistorized grid side of enhancement mode PMOS resistance is at 20ohm ± 2ohm, and the transistorized threshold voltage of enhancement mode PMOS is at-0.8V ± 0.2V.

Preferably, enhancement mode PMOS transistor and the transistorized breadth length ratio of depletion type PMOS are

Wherein Ue is the transistorized channel mobility of depletion type PMOS, and Ud is the transistorized channel mobility of enhancement mode PMOS, and wherein α E is the temperature coefficient of the transistorized threshold voltage of depletion type PMOS, and α D is the temperature coefficient of the transistorized threshold voltage of enhancement mode PMOS.

Preferably, enhancement mode PMOS transistor and the transistorized breadth length ratio of depletion type PMOS are Wherein Ue is the transistorized channel mobility of depletion type PMOS, and Ud is the transistorized channel mobility of enhancement mode PMOS.

Preferably, depletion type PMOS transistor and enhancement mode PMOS transistor are arranged in same type N trap, and the ion concentration distribution of N trap is identical.

Preferably, comprising: transistorized grid of depletion type PMOS and source electrode couple high level, and transistorized substrate of depletion type PMOS and source electrode couple; Transistorized grid of enhancement mode PMOS and drain electrode couple; Transistorized substrate of enhancement mode PMOS and source electrode couple, and enhancement mode PMOS transistor drain couples low level; Depletion type PMOS transistor drain and the transistorized source electrode of enhancement mode PMOS couple the output terminal of reference voltage device.

Preferably, comprising: transistorized grid of depletion type PMOS and source electrode couple, and transistorized substrate of depletion type PMOS and source electrode couple, and depletion type PMOS transistor drain couples low level; Transistorized grid of enhancement mode PMOS and drain electrode couple, and transistorized substrate of enhancement mode PMOS and source electrode couple, and the transistorized source electrode of enhancement mode PMOS couples high level; Depletion type PMOS transistor source and enhancement mode PMOS transistor drain couple the output terminal of reference voltage device.

Preferably, comprising: the transistorized grid of depletion type PMOS couples high level, and transistorized substrate of depletion type PMOS and source electrode couple, and depletion type PMOS transistor drain couples low level; Transistorized grid of enhancement mode PMOS and drain electrode couple, and transistorized substrate of enhancement mode PMOS and source electrode couple, and the transistorized source electrode of enhancement mode PMOS couples high level; Depletion type PMOS transistor source and enhancement mode PMOS transistor drain couple the output terminal of reference voltage device.

Preferably, comprising: the transistorized grid of a PMOS couples drain electrode, and the transistorized source electrode of a PMOS couples high level, and the transistorized substrate of a PMOS couples high level; Transistorized grid of depletion type PMOS and source electrode couple a PMOS transistor drain, and the transistorized substrate of depletion type PMOS couples high level; Transistorized grid of enhancement mode PMOS and drain electrode couple; Transistorized substrate of enhancement mode PMOS and source electrode couple, and enhancement mode PMOS transistor drain couples low level; Depletion type PMOS transistor drain and the transistorized source electrode of enhancement mode PMOS couple the output terminal of reference voltage device.

Preferably, comprising: first order reference voltage devices comprises: transistorized grid of the first depletion type PMOS and source electrode couple, and transistorized substrate of the first depletion type PMOS and source electrode couple, and the first depletion type PMOS transistor drain couples low level; Transistorized grid of the first enhancement mode PMOS and drain electrode couple, and transistorized substrate of the first enhancement mode PMOS and source electrode couple, and the transistorized source electrode of the first enhancement mode PMOS couples high level; The first depletion type PMOS transistor source and the first enhancement mode PMOS transistor drain couple the output terminal of first order reference voltage device;

The grid of nmos pass transistor couples the output terminal of first order reference voltage device, and the drain electrode of nmos pass transistor couples high level, and the substrate of nmos pass transistor and source electrode couple second and strengthen the transistorized source electrode of PMOS; The transistorized substrate of enhancement mode PMOS couples high level, and the second enhancement mode PMOS transistor drain and the transistorized source electrode of the second depletion type PMOS couple the output terminal of reference voltage device; Transistorized grid of the second depletion type PMOS and drain electrode couple low level.

The advantage that technique scheme is compared with prior art is: depletion type PMOS transistor and enhancement mode PMOS transistor all are the surface channel device, but depletion type PMOS transistor adopts the P type polysilicon bar utmost point, enhancement mode PMOS transistor adopts the N type polysilicon bar utmost point, so depletion type PMOS transistor need not carry out ion and injects and regulate threshold voltage in conducting channel.For depletion type PMOS transistor and enhancement mode PMOS transistor, the ion branch of conducting channel is identical, and depletion type PMOS transistor is identical with the temperature variant degree of the transistorized threshold voltage of enhancement mode PMOS like this, so good stability.

Description of drawings

By the more specifically explanation of the preferred embodiment of the present utility model shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present utility model will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present utility model by physical size equal proportion convergent-divergent.

Fig. 1 is a kind of circuit diagram of reference voltage device;

Fig. 2 is the cross-sectional view of reference voltage device shown in Figure 1;

Fig. 3 is the circuit diagram of the reference voltage device of first embodiment of the present utility model;

Fig. 4 is the cross-sectional view of reference voltage device of the present utility model shown in Figure 3;

Fig. 5 is the circuit diagram of the reference voltage device of second embodiment of the present utility model;

Fig. 6 is the circuit diagram of the reference voltage device of the 3rd embodiment of the present utility model;

Fig. 7 is the circuit diagram of the reference voltage device of the 4th embodiment of the present utility model;

Fig. 8 is the circuit diagram of the reference voltage device of the 5th embodiment of the present utility model.

Embodiment

For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, embodiment of the present utility model is described in detail below in conjunction with accompanying drawing.

A lot of details have been set forth in the following description so that fully understand the utility model.But the utility model can be implemented much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of the utility model intension, so the utility model is not subjected to the restriction of following public concrete enforcement.

Secondly, the utility model utilizes synoptic diagram to be described in detail, when the utility model embodiment is described in detail in detail; for ease of explanation; the sectional view of expression device architecture can be disobeyed general ratio and be done local the amplification, and described synoptic diagram is example, and it should not limit the scope of the utility model protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.

Embodiment one

With reference to figure 3 and Fig. 4, the reference voltage device comprises: grid 311 and the source electrode 312 of depletion type PMOS transistor P310 couple high level, and substrate and the source electrode 312 of depletion type PMOS transistor P310 couple; Grid 321 and the drain electrode 323 of enhancement mode PMOS transistor P320 couple, and substrate and the source electrode 322 of enhancement mode PMOS transistor P320 couple, and the drain electrode 323 of enhancement mode PMOS transistor P320 couples low level; The source electrode 322 of depletion type PMOS transistor P310 drain electrode 313 and enhancement mode PMOS transistor P320 couples the output terminal OUT of reference voltage device.Wherein, depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are the surface channel device, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, and be identical thereby the concentration impurity ion of the doping of two transistorized conducting channels of PMOS distributes.Wherein, the grid of depletion type PMOS transistor P310 is that the P type mixes, square resistance near 2000ohm, 2000ohm ± 200ohm for example, the threshold voltage of depletion type PMOS transistor P310 near 0.4V, 0.4V ± 0.1V for example.The grid of enhancement mode PMOS transistor P320 is that the N type mixes, and square resistance is near 20ohm, and 20ohm ± 2ohm for example, the threshold voltage of enhancement mode PMOS transistor P320 are near-0.8V, for example-0.8V ± 0.2V.

Preferably, depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are made in same type the N trap (Nwell), adopt identical threshold value adjustment to inject, in other words, depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are arranged in same type N trap, and the ion concentration distribution of N trap is identical, therefore, for depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320, the Impurity Distribution of its conducting channel is identical.

Though depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are the surface channel device, depletion type PMOS transistor P310 adopts the P type polysilicon bar utmost point, and enhancement mode PMOS transistor P320 adopts the N type polysilicon bar utmost point.For depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320, the Impurity Distribution of raceway groove is identical.To lead temperature variant degree identical for the threshold voltage of depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 and electricity like this.Therefore, can provide a reference voltage circuit that is made of depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320, its output voltage is very little with variation of temperature, approaches zero.

Specifically in the present embodiment, it is as follows to express formula with reference to the output voltage of reference voltage circuit shown in Figure 1:

$\mathrm{Vref}=\left|\mathrm{VthE}\right|+\sqrt{\frac{\mathrm{Ud}(W/L)d}{\mathrm{Ue}(W/L)e}}\mathrm{VthD}---\left(1\right)$

Wherein, Vref is an output voltage, VthE is the threshold voltage of depletion type PMOS transistor P310, VthD is the threshold voltage of depletion type PMOS transistor P310, Ue is the channel mobility of depletion type PMOS transistor P310, Ud is the channel mobility of enhancement mode PMOS transistor P320, and (W/L) e is the device breadth length ratio of depletion type PMOS transistor P310, and (W/L) d is the device breadth length ratio of enhancement mode PMOS transistor P320.

Reference voltage device output voltage V ref is with variation of temperature:

$\frac{\∂\mathrm{Vref}}{\∂T}=\mathrm{\αE}+\mathrm{\αD}\sqrt{\frac{\mathrm{Ud}*(W/L)d}{\mathrm{Ue}*(W/L)e}}+\frac{1}{2}\mathrm{Vthd}\sqrt{\frac{(W/L)d}{(W/L)e}}*\frac{1}{\sqrt{\frac{\mathrm{Ud}}{\mathrm{Ue}}}}\frac{\∂\left(\frac{\mathrm{Ud}}{\mathrm{Ue}}\right)}{\∂T}$

Wherein α E is the temperature coefficient of VthE, and α D is the temperature coefficient of VthD.

In this programme, because the Impurity Distribution of enhancement mode PMOS transistor P320 and depletion type PMOS transistor P310 raceway groove is identical, so

$\frac{\∂\left(\frac{\mathrm{Ud}}{\mathrm{Ue}}\right)}{\∂T}=0$

So output voltage is with variation of temperature:

$\frac{\∂\mathrm{Vref}}{\∂T}=\mathrm{\αE}+\mathrm{\αD}\sqrt{\frac{\mathrm{Ud}*(W/L)d}{\mathrm{Ue}*(W/L)e}}---\left(2\right)$

Because under the technology fixation case, α E, α D and Ue/Ud are three fixing constants, and α E is a negative value, α E be one on the occasion of, so, as long as two kinds of device breadth length ratios are chosen suitable value, formula (2) is equalled zero, just:

$\frac{(W/L)d}{(W/L)e}={(-\frac{\mathrm{\αE}}{\mathrm{\αD}})}^2*\frac{\mathrm{Ue}}{\mathrm{Ud}}$

Then output voltage is made as zero with variation of temperature with regard to controlled, and promptly output voltage does not change with variation of temperature.It is therefore preferred in the present embodiment, $\frac{(W/L)d}{(W/L)e}={(-\frac{\mathrm{\αE}}{\mathrm{\αD}})}^2*\frac{\mathrm{Ue}}{\mathrm{Ud}},$ Then output voltage is made as zero with variation of temperature with regard to controlled.

In addition, the utility model also provides another embodiment, in this embodiment can be by for depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 choose suitable breadth length ratio, thus make that output voltage is the energy gap of silicon.

Below this embodiment is elaborated:

For the MOS device, those skilled in the art know:

Wherein, VSB be source electrode to underlayer voltage, φ _F(substrate) is the Fermi potential of substrate, φ _F(grid) are the Fermi potential of grid, and Qss is the oxide layer electric charge, and Cox is a grid specific capacitance value, and Nsub is a N type substrate doping, ε _SiIt is the specific inductive capacity of silicon.

If choose suitable (W/L) d, (W/L) e,

Make $\mathrm{Vref}=\left|\mathrm{VthE}\right|+\sqrt{\frac{\mathrm{Ud}(W/L)d}{\mathrm{Ue}(W/L)e}}\mathrm{VthD}$ (1) in the formula $\sqrt{\frac{\mathrm{Ud}(W/L)d}{\mathrm{Ue}(W/L)e}}=1,$

Then

Just preferred $\frac{(W/L)d}{(W/L)e}=\frac{\mathrm{Ue}}{\mathrm{Ud}},$ Then the reference voltage device of present embodiment can produce constant output voltage values, and output voltage is the energy gap of silicon, about about 1.12V.The temperature coefficient of output voltage is also consistent with the temperature coefficient of energy gap, is a negative value.Because output voltage is constant is the energy gap of silicon, so the stable performance of this reference voltage device, the reliability height.

Embodiment two

With reference to figure 5, the reference voltage device comprises:

Grid 311 and the source electrode 312 of depletion type PMOS transistor P310 couple, and substrate and the source electrode 312 of depletion type PMOS transistor P310 couple, and the drain electrode 313 of depletion type PMOS transistor P310 couples low level; Grid 321 and the drain electrode 323 of enhancement mode PMOS transistor P320 couple, and substrate and the source electrode 322 of enhancement mode PMOS transistor P320 couple, and the source electrode 322 of enhancement mode PMOS transistor P320 couples high level; The drain electrode 323 of depletion type PMOS transistor P310 source electrode 312 and enhancement mode PMOS transistor P320 couples the output terminal OUT of reference voltage device.Wherein, depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are the surface channel device, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, thereby the foreign ion of two transistorized conducting channel doping of PMOS distributes all identical.Wherein, the grid of depletion type PMOS transistor P310 is that the P type mixes, square resistance near 2000ohm, 2000ohm ± 200ohm for example, the threshold voltage of depletion type PMOS transistor P310 near 0.4V, 0.4V ± 0.1V for example.The grid of enhancement mode PMOS transistor P320 is that the N type mixes, and square resistance is near 20ohm, and 20ohm ± 2ohm for example, the threshold voltage of enhancement mode PMOS transistor P320 are near-0.8V, for example-0.8V ± 0.2V.

Embodiment three

With reference to figure 6, the reference voltage device comprises:

The grid 311 of depletion type PMOS transistor P310 couples high level, and substrate and the source electrode 312 of depletion type PMOS transistor P310 couple, and the drain electrode 313 of depletion type PMOS transistor P310 couples low level; Grid 321 and the drain electrode 323 of enhancement mode PMOS transistor P320 couple, and substrate and the source electrode 322 of enhancement mode PMOS transistor P320 couple, and the source electrode 322 of enhancement mode PMOS transistor P320 couples high level; The drain electrode 323 of depletion type PMOS transistor P310 source electrode 312 and enhancement mode PMOS transistor P320 couples the output terminal OUT of reference voltage device.Wherein, depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are the surface channel device, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, thereby the foreign ion of two transistorized conducting channel doping of PMOS distributes all identical.Wherein, the grid of depletion type PMOS transistor P310 is that the P type mixes, square resistance near 2000ohm, 2000ohm ± 200ohm for example, the threshold voltage of depletion type PMOS transistor P310 near 0.4V, 0.4V ± 0.1V for example.The grid of enhancement mode PMOS transistor P320 is that the N type mixes, and square resistance is near 20ohm, and 20ohm ± 2ohm for example, the threshold voltage of enhancement mode PMOS transistor P320 are near-0.8V, for example-0.8V ± 0.2V.

Embodiment four

With reference to figure 7, the reference voltage device comprises:

The source electrode 332 that the grid 331 of the one PMOS transistor 330 couples drain electrode 333, the one PMOS transistors 330 couples high level, and the substrate of a PMOS transistor 330 couples high level; The grid 311 of depletion type PMOS transistor P310 and source electrode 312 couple a PMOS transistor drain 333, and the substrate 312 of depletion type PMOS transistor P310 couples high level; Grid 321 and the drain electrode 323 of enhancement mode PMOS transistor P320 couple; Substrate and the source electrode 322 of enhancement mode PMOS transistor P320 couple, and the drain electrode 323 of enhancement mode PMOS transistor P320 couples low level; The source electrode 322 of depletion type PMOS transistor P310 drain electrode 313 and enhancement mode PMOS transistor P320 couples the output terminal OUT of reference voltage device.Wherein, depletion type PMOS transistor P310 and enhancement mode PMOS transistor P320 are the surface channel device, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, thereby the foreign ion of two transistorized conducting channel doping of PMOS distributes all identical.Wherein, the grid of depletion type PMOS transistor P310 is that the P type mixes, square resistance near 2000ohm, 2000ohm ± 200ohm for example, the threshold voltage of depletion type PMOS transistor P310 near 0.4V, 0.4V ± 0.1V for example.The grid of enhancement mode PMOS transistor P320 is that the N type mixes, and square resistance is near 20ohm, and 20ohm ± 2ohm for example, the threshold voltage of enhancement mode PMOS transistor P320 are near-0.8V, for example-0.8V ± 0.2V.

Embodiment five

With reference to figure 8, the reference voltage device comprises:

The first order is examined the voltage source device and comprised: grid 3111 and the source electrode 3121 of the first depletion type PMOS transistor P3101 of reference voltage device couple, substrate and the source electrode 3121 of the first depletion type PMOS transistor P3101 couple, and the drain electrode 3131 of the first depletion type PMOS transistor P3101 couples low level; Grid 3211 and the drain electrode 3231 of the first enhancement mode PMOS transistor P3201 couple, and substrate and the source electrode 3221 of the first enhancement mode PMOS transistor P3201 couple, and the source electrode 3221 of the first enhancement mode PMOS transistor P3201 couples high level; The drain electrode 3231 of the first depletion type PMOS transistor P3101 source electrode 3121 and the first enhancement mode PMOS transistor P3201 couples the output terminal OUT of reference voltage device.Wherein, the first depletion type PMOS transistor P3101 and the first enhancement mode PMOS transistor P3201 are the surface channel device, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, thereby the foreign ion of two transistorized conducting channel doping of PMOS distributes all identical.Wherein, the grid of depletion type PMOS transistor P310 is that the P type mixes, square resistance near 2000ohm, 2000ohm ± 200ohm for example, the threshold voltage of depletion type PMOS transistor P310 near 0.4V, 0.4V ± 0.1V for example.The grid of enhancement mode PMOS transistor P320 is that the N type mixes, and square resistance is near 20ohm, and 20ohm ± 2ohm for example, the threshold voltage of enhancement mode PMOS transistor P320 are near-0.8V, for example-0.8V ± 0.2V.

The grid 431 of the nmos pass transistor 430 of reference voltage device couples the output of first order reference voltage device, the drain electrode 432 of nmos pass transistor 430 couples high level, and the substrate of nmos pass transistor 430 and source electrode couple the source electrode 3222 of the second enhancing PMOS transistor 3202; The substrate of enhancement mode PMOS transistor 3202 couples high level, and the source electrode 3122 of the drain electrode of the second enhancement mode PMOS transistor 3202 and the second depletion type PMOS transistor P3102 couples the output terminal of reference voltage device; Grid 3112 and the drain electrode 3132 of the second depletion type PMOS transistor P3102 couple low level.Wherein, the second depletion type PMOS transistor P3102 and the second enhancement mode PMOS transistor P3202 are the surface channel device, the dosage and the energy of two transistorized conducting channel doping of PMOS are identical, thereby the foreign ion of two transistorized conducting channel doping of PMOS distributes all identical.Wherein, the grid of depletion type PMOS transistor P310 is that the P type mixes, square resistance near 2000ohm, 2000ohm ± 200ohm for example, the threshold voltage of depletion type PMOS transistor P310 near 0.4V, 0.4V ± 0.1V for example.The grid of enhancement mode PMOS transistor P320 is that the N type mixes, and square resistance is near 20ohm, and 20ohm ± 2ohm for example, the threshold voltage of enhancement mode PMOS transistor P320 are near-0.8V, for example-0.8V ± 0.2V.

The foregoing description two, embodiment four, and embodiment five in, preferred, enhancement mode PMOS transistor and the transistorized breadth length ratio of depletion type PMOS are:

$\frac{(W/L)d}{(W/L)e}={(-\frac{\mathrm{\αE}}{\mathrm{\αD}})}^2*\frac{\mathrm{Ue}}{\mathrm{Ud}}$

Thereby make this reference voltage device output voltage be made as zero with variation of temperature with regard to controlled, promptly output voltage does not change with variation of temperature.

Or preferred, enhancement mode PMOS transistor and the transistorized breadth length ratio of depletion type PMOS are:

$\frac{(W/L)d}{(W/L)e}=\frac{\mathrm{Ue}}{\mathrm{Ud}}$

Then the reference voltage device can produce constant output voltage values, and output voltage is the energy gap of silicon, about about 1.12V.The temperature coefficient of output voltage is also consistent with the temperature coefficient of energy gap, is a negative value.Because output voltage is constant is the energy gap of silicon, so the stable performance of this reference voltage device, the reliability height.

Though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model.Any those of ordinary skill in the art, do not breaking away under the technical solutions of the utility model scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solutions of the utility model are made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solutions of the utility model, all still belongs in the scope of technical solutions of the utility model protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present utility model.

Claims (10)

1, a kind of reference voltage device, comprise depletion type PMOS transistor and enhancement mode PMOS transistor, it is characterized in that, depletion type PMOS transistor and enhancement mode PMOS transistor are all the surface conduction channel transistor npn npn, and the ion distribution in depletion type PMOS transistor and the transistorized conducting channel of enhancement mode PMOS is identical, wherein the transistorized grid of depletion type PMOS mixes for the P type, and the transistorized grid of enhancement mode PMOS mixes for the N type.

2, reference voltage device according to claim 1 is characterized in that, the transistorized grid side of depletion type PMOS resistance is at 2000ohm ± 200ohm, and the transistorized threshold voltage of depletion type PMOS is at 0.4V ± 0.1V; The transistorized grid side of enhancement mode PMOS resistance is at 20ohm ± 2ohm, and the transistorized threshold voltage of enhancement mode PMOS is at-0.8V ± 0.2V.

3, reference voltage device according to claim 2 is characterized in that, enhancement mode PMOS transistor and the transistorized breadth length ratio of depletion type PMOS are

Wherein Ue is the transistorized channel mobility of depletion type PMOS, and Ud is the transistorized channel mobility of enhancement mode PMOS, and wherein α E is the temperature coefficient of the transistorized threshold voltage of depletion type PMOS, and α D is the temperature coefficient of the transistorized threshold voltage of enhancement mode PMOS.

4, reference voltage device according to claim 2 is characterized in that, enhancement mode PMOS transistor and the transistorized breadth length ratio of depletion type PMOS are

Wherein Ue is the transistorized channel mobility of depletion type PMOS, and Ud is the transistorized channel mobility of enhancement mode PMOS.

According to claim 2 or 3 described reference voltage devices, it is characterized in that 5, depletion type PMOS transistor and enhancement mode PMOS transistor are arranged in same type N trap, and the ion concentration distribution of N trap is identical.

6, according to any described reference voltage device of claim 1 to 4, it is characterized in that, comprising:

Transistorized grid of depletion type PMOS and source electrode couple high level, and transistorized substrate of depletion type PMOS and source electrode couple; Transistorized grid of enhancement mode PMOS and drain electrode couple; Transistorized substrate of enhancement mode PMOS and source electrode couple, and enhancement mode PMOS transistor drain couples low level; Depletion type PMOS transistor drain and the transistorized source electrode of enhancement mode PMOS couple the output terminal of reference voltage device.

7, according to any described reference voltage device of claim 1 to 4, it is characterized in that, comprising:

Transistorized grid of depletion type PMOS and source electrode couple, and transistorized substrate of depletion type PMOS and source electrode couple, and depletion type PMOS transistor drain couples low level; Transistorized grid of enhancement mode PMOS and drain electrode couple, and transistorized substrate of enhancement mode PMOS and source electrode couple, and the transistorized source electrode of enhancement mode PMOS couples high level; Depletion type PMOS transistor source and enhancement mode PMOS transistor drain couple the output terminal of reference voltage device.

8, reference voltage device according to claim 1 and 2 is characterized in that, comprising:

The transistorized grid of depletion type PMOS couples high level, and transistorized substrate of depletion type PMOS and source electrode couple, and depletion type PMOS transistor drain couples low level; Transistorized grid of enhancement mode PMOS and drain electrode couple, and transistorized substrate of enhancement mode PMOS and source electrode couple, and the transistorized source electrode of enhancement mode PMOS couples high level; Depletion type PMOS transistor source and enhancement mode PMOS transistor drain couple the output terminal of reference voltage device.

9, according to any described reference voltage device of claim 1 to 4, it is characterized in that, comprising:

The transistorized grid of the one PMOS couples drain electrode, and the transistorized source electrode of a PMOS couples high level, and the transistorized substrate of a PMOS couples high level; Transistorized grid of depletion type PMOS and source electrode couple a PMOS transistor drain, and the transistorized substrate of depletion type PMOS couples high level; Transistorized grid of enhancement mode PMOS and drain electrode couple; Transistorized substrate of enhancement mode PMOS and source electrode couple, and enhancement mode PMOS transistor drain couples low level; Depletion type PMOS transistor drain and the transistorized source electrode of enhancement mode PMOS couple the output terminal of reference voltage device.

10, according to any described reference voltage device of claim 1 to 4, it is characterized in that, comprising:

First order reference voltage devices comprises: transistorized grid of the first depletion type PMOS and source electrode couple, and transistorized substrate of the first depletion type PMOS and source electrode couple, and the first depletion type PMOS transistor drain couples low level; Transistorized grid of the first enhancement mode PMOS and drain electrode couple, and transistorized substrate of the first enhancement mode PMOS and source electrode couple, and the transistorized source electrode of the first enhancement mode PMOS couples high level; The first depletion type PMOS transistor source and the first enhancement mode PMOS transistor drain couple the output terminal of first order reference voltage device;

The grid of nmos pass transistor couples the output terminal of first order reference voltage device, and the drain electrode of nmos pass transistor couples high level, and the substrate of nmos pass transistor and source electrode couple second and strengthen the transistorized source electrode of PMOS; The transistorized substrate of enhancement mode PMOS couples high level, and the second enhancement mode PMOS transistor drain and the transistorized source electrode of the second depletion type PMOS couple the output terminal of reference voltage device; Transistorized grid of the second depletion type PMOS and drain electrode couple low level.

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