CN100416845C - Low-substrate leakage current hole accumulating active picture element and producing method thereof - Google Patents

Low-substrate leakage current hole accumulating active picture element and producing method thereof Download PDF

Info

Publication number
CN100416845C
CN100416845C CN 200510083007 CN200510083007A CN100416845C CN 100416845 C CN100416845 C CN 100416845C CN 200510083007 CN200510083007 CN 200510083007 CN 200510083007 A CN200510083007 A CN 200510083007A CN 100416845 C CN100416845 C CN 100416845C
Authority
CN
Grant status
Grant
Patent type
Prior art keywords
region
epitaxial layer
layer
type
substrate
Prior art date
Application number
CN 200510083007
Other languages
Chinese (zh)
Other versions
CN1889268A (en )
Inventor
金湘亮
Original Assignee
北京思比科微电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Abstract

本发明的低衬底漏电流的空穴积累型有源像素的在N衬底上生长一层P+型外延层,在P+型外延层上生长一层P型外延层,在P外延层区内注入一层N+区,并在N+区浅注入一层P区,从而形成两个PN结,可以吸收不同波长的注入光。 Low substrate of the present invention, a leakage current active hole accumulation type pixel of growing a layer of P + type epitaxial layer on an N substrate, growing a P type epitaxial layer on a P + type epitaxial layer, the region in the P epitaxial layer implanted layer N + region, and a shallow implanted layer P region of the N + region, thereby forming two PN junction, can absorb the injected light at different wavelengths. 本发明提出的是一种基于N衬底和光电二极管的有源像素结构,这种低衬底漏电流的空穴积累型有源像素结构有效的降低了暗电流、提高了量子效率。 Proposed by the present invention is an active pixel architecture N substrate, and a photodiode-based hole accumulation type such low substrate leakage current active pixel architecture effectively reduces the dark current and improve quantum efficiency. 利用N衬底可以有效的防止像素之间的光电荷的扩散,防止弥散现象。 Using N substrate diffused light charge between the pixels can be effectively prevented, to prevent diffusion phenomenon.

Description

低衬底漏电流的空穴积累型有源像素及其制造方法技术领域本发明涉及微电子学的集成电路设计技术领域,尤其涉及一种低衬底漏电流的空穴积累型有源^象素及其制造方法。 Hole accumulation type active pixel TECHNICAL FIELD The lower substrate leakage current invention relates to the design technical field of integrated circuits in microelectronics, in particular, to hole accumulation type a low-substrate leakage current active ^ as hormone and its manufacturing method. 背景技术经过十几年的研究,CMOS ( Complementary Metal-Oxide-Semiconductor Transistor ,中文:互补从属氧化物半导体)图像传感器在某些性能方面取得了明显改善,但在噪声和成像质量等方面都比不上CCD (Charge Coupled Device,中文:电荷耦合器件)图Y象传感器。 BACKGROUND after ten years of research, CMOS (Complementary Metal-Oxide-Semiconductor Transistor, Chinese: complement dependent Oxide Semiconductor) image sensor has made significant improvements in certain properties, but better than not in terms of noise and image quality a CCD (Charge Coupled device, Chinese: Charge Coupled device) FIG Y image sensor. 相对于CCD图像传感器技术而言,基于CMOS工艺的图像传感器具有成本低、功耗低、便于大规^t集成等优点。 With respect to the CCD image sensor technology, CMOS-based image sensor having a low cost, low power consumption, to facilitate large scale ^ t integration advantages. 尤其是随着CMOS工艺的特征尺寸按等比例原则进一步缩小,对某些应用来说,CMOS图像传感器技术某些性能的优势更加突出。 Especially as the feature size CMOS process principles are further reduced in equal proportions, for some applications, certain performance advantages of the CMOS image sensor technology is more prominent. CMOS图像传感器技术能够单芯片集成许多附加电路,如电源管理电路、图像处理电路、图像压缩电路等;同时CMOS器件中的像素单元可以作得比较小,能够提供比CCD图像传感器更高分辨率的图像器件。 CMOS image sensor technology can be a single-chip integration of many additional circuits, such as power management circuit, image processing circuit, an image compression circuit or the like; the same CMOS devices pixel unit can be made relatively small, it can be provided over the CCD image sensor with higher resolution image device. 目前,用于CMOS图像传感器结构的像素单元主要有无源像素结构和有源像素结构。 Currently, the pixel cell for a CMOS image sensor structures are mainly passive pixel structure and the active pixel architecture. 无源像素结构的最大优点是像素内只集成一个晶体管,能获得大的填充系数;电路结构不复杂、寻址简单、获得的成品率高,因而价格低。 The biggest advantage of the passive pixel structure is integrated only one transistor within the pixel can obtain a large fill factor; circuit configuration is not complicated, addressing simple, high yield is obtained, so that a low price. 但无源像素的列总线等效的电阻和电容比较大,使得像素读出的速度慢,特别是当像素阵列比较大时,由列总线带来的信号延迟和信号损失非常大;其次无源像素读出的噪声较大,信号电荷的损失随着列总线的增长而变大,降低了信噪比。 However, passive pixel column bus equivalent resistance and capacitance is relatively large, so that the pixel speed readout slow, particularly when the pixel array is relatively large, signal delay and signal loss caused by the column bus is very large; second passive pixel readout noise of large, loss of signal charge grows column bus becomes large, reducing the signal to noise ratio. 因为上述缺点限制了应用,很快被后来发展的有源像素结构代替。 Because of these shortcomings have limited the application of active pixel structure soon be later developed instead. 有源像素内部包含一个有源器件,即包含一个由一个或多个晶体管组成的放大器,通常由源跟随晶体管构成,该放大器在像素内部具有放大和緩冲功能, 电荷不需要经过远距离而到达输出放大器,在列总线直接输出的是电压或电流信号,因此避免了像无源像素内的信号电荷必须经过很长列总线才能到达放大器的缺陷。 The active internal pixel includes an active device, i.e., comprising an amplifier of one or more transistors, usually composed of a source follower transistor, this amplifier having amplification and buffering functions inside the pixel, the charge does not need to undergo long and reaches the output amplifier, the column bus direct output voltage or current signal, thus avoiding the image signal charges within the passive pixel must pass through a long column bus to reach the amplifier defect. 目前,基于标准的CMOS制造过程的常用有源像素结构是包括三个晶体管和一个N+/P-阱的光电二极管,^旦这种有源4象素具有较大的暗电流,大大影响了CMOS图像传感器的动态范围,更严重的是大的暗电流将造成CMOS 图像传感器出现白点。 Currently, standards-based conventional active pixel structure of a CMOS manufacturing process is a photodiode three transistors and a N + / P- well, ^ once such an active four pixels having a large dark current, greatly affect the CMOS the dynamic range of the image sensor, the more serious is the large dark current will cause the CMOS image sensor has white spots. 另一种有源像素结构的设计是基于P型衬底的钉扎型光电二极管,这种光电二极管具有表面暗电流低、对蓝光具有良好的响应特性。 Design of a further active pixel architecture is based on a pinned photodiode P-type substrate, the photodiode having a surface low dark current, good response characteristics to blue light. 但该种结构的光电二极管依然没有改变CMOS工艺的本质特征,因此减少的暗电流并不很明显。 However photodiode this kind of configuration has not changed the essential characteristics of the CMOS process, thereby reducing dark current is not obvious. 发明内容鉴于上述现有技术所存在的问题,本发明的目的是提供一种低衬底漏电流的空穴积累型有源像素及其制造方法,制作在N型硅衬底上,从而获得低暗电流的特征。 View of the foregoing prior art problems, an object of the present invention is to provide a low substrate leakage current hole accumulation type active pixel and its manufacturing method, formed on the N type silicon substrate, thereby obtaining a low characterized in dark current. 本发明的目的是通过以下技术方案实现的:一种低衬底漏电流的空穴积累型有源像素,主体包括N型村底、P +外延层与P型外延层;P +外延层生长于N衬底上,P型外延层生长于P +外延层上;所述的? Object of the present invention is achieved by the following technical solution: hole accumulation type a low-substrate leakage current active pixel, the main body includes an N-type village substrate, P + epitaxial layer and the P type epitaxial layer; P + epitaxial layer grown on the N substrate, P-type epitaxial layer grown on a P + epitaxial layer; said? 型外延层还设有閃+区,形成一个PN结;在N+区上还设有P区,形成另一个PN结;所述的P型外延层上还设有深N+区,深N+区扩散至P+外延层,且该深N+区与N+区相互接触。 Type epitaxial layer is further provided with a flash + region forming a PN junction; on the N + region also has a P region formed in another PN junction; also a deep N + region on the P-type epitaxial layer, said deep N + region diffusion to P + epitaxial layer, and the deep N + region and the N + region contact with each other. 所述的N+区上设有电极,该电极加有偏置电压。 Said N + electrodes are provided on the area, the electrode applied with a bias voltage. . 所述的P型外延层上还设有N-阱,在N-阱上生长有栅氧层,在栅氧层上还生长有一层多晶硅层;在N-阱上还设有源漏区。 The P-type epitaxial layer is further provided N- well in the N- well grown gate oxide layer, further growth of a layer of a polysilicon layer on the gate oxide layer; in the N- well is also provided with source and drain regions. 所述的P型外延层上设有窄沟道隔离区,P区设于窄沟道隔离区下。 With narrow channel isolation region on said P-type epitaxial layer, P region disposed at a narrow trench isolation region. 一种基于上述低衬底漏电流的空穴积累型有源像素的制造方法,包括:A、 在N型衬底上外延生长P +型外延层;B、 在P +型外延层上面外延生长P型外延层;C、 在P型外延层上设置深N+区,所述深N+区扩散至P+外延层,且该深N+区与N+区相互接触;D、 将磷离子注入到P外延层3中,经过预定时间的高温退火,激活磷离子同时将其趋入,形成N+区;E、 生成读出电路的晶体管;F、 在N-阱的表面生长一层二氧化硅,注入离子注入BF^,形成表面P区。 A method for manufacturing a hole accumulation type above-described low substrate leakage current active pixel-based, including: A, epitaxially grown P + type epitaxial layer on N-type substrate; B, the P + type epitaxial layer epitaxially grown P-type epitaxial layer; C, provided a deep N + region on the P-type epitaxial layer, the deep N + region diffusion to P + epitaxial layer, and the deep N + region and the N + region in contact with each other; D, the phosphorus ions implanted into the P epilayer 3, the high temperature annealing for a predetermined time, the activation of phosphorus ions while being drive-in to form N + regions; E, generating transistor readout circuitry; F, the surface of the growth N- well layer of silicon dioxide implanted ion implantation BF ^, forming surface of the P region. 所述的步骤C包括:生长的二氧化硅层厚度控制在100埃〜150埃。 Said step C comprising: a silicon dioxide layer thickness of controlling the growth of 100 Angstroms ~150 Å. 所述的步骤E还包括: E1、在P型外延层中形成N-阱; E2、在N-阱上生长栅氧层; E3、在栅氧层上长一层多晶硅层层; E4、在N-阱上注入硼离子离子形成源漏区。 Said step E further comprising: E1, formed in a P-type epitaxial layer N- well; E2, at the N- well to grow the gate oxide layer; E3, on the gate oxide layer length a layer of polysilicon layers; E4, in boron ions are ion-implanted on the N- well forming source and drain regions. 所述的步骤F还包括: F1、在P型外延层上做出窄沟道隔离区;F2、在窄沟道隔离区下方的N-阱的表面生长一层二氧化硅,注入低能量、大剂量离子注入BF",形成表面P区。由上述本发明提供的技术方案可以看出,本发明的低衬底漏电流的空穴积累型有源像素的在N衬底上生长一层P+型外延层,在P+型外延层上生长一层P型外延层,在P外延层区内注入一层N+区,并在N+区浅注入一层P区, 从而形成两个PN结,可以吸收不同波长的注入光。本发明提出的是一种基于N衬底和光电二极管的有源像素结构,这种低衬底漏电流的空穴积累型有源像素结构有效的降低了暗电流、提高了量子效率。附图说明图1为本发明所述的低衬底漏电流的空穴积累型有源像素结构示意图一; 图2为本发明所述的低衬底漏电流的空穴积累型有源像素结构示意图二; 图3为本发明所述的低村底漏 Said step F further includes: F1, to make the narrow trench isolation regions on a P type epitaxial layer; F2 of, the surface of N- well below the narrow channel isolation region growing a layer of silicon dioxide, into low energy, high dose ion implantation BF ", is formed surface of the P region provided by the present invention, the technical solutions can be seen, hole accumulation type low substrate according to the present invention, leakage current active pixel grown layer P on the N + substrate type epitaxial layer grown on the P + type epitaxial layer of P-type epitaxial layer, the injection layer of N + regions in the P-epitaxial layer region, and a shallow implanted layer P region of the N + region, thereby forming two PN junction can absorb injecting light of different wavelengths. proposed by the invention is an active pixel architecture N substrate, and a photodiode-based hole accumulation type such low substrate leakage current active pixel architecture effectively reduces the dark current, improving the quantum efficiency of Figure 1 hole accumulation type active pixel structure of the present invention, the lower substrate leakage current diagram of a;. FIG. 2 of the present invention, the lower substrate leakage current hole accumulation type active pixel architecture Diagram II; FIG. 3 of the present invention is low village bottom drain 流的空穴积累型有源像素制造过程示意图图4为本发明所述的低衬底漏电流的空穴积累型有源像素制造过程示意图图5为本发明所述的低村底漏电流的空穴积累型有源像素制造过程示意图图6为本发明所述的低衬底漏电流的空穴积累型有源像素制造过程示意图四;图7为本发明所述的低衬底漏电流的空穴积累型有源像素制造过程示意图五。具体实施方式本发明的核心描述了一种新型适用于CMOS图像传感器的低暗电流的有源像素,该种有源像素最根本的特点在于制作在N型硅衬底上,从而获得低暗电流的特征。本发明的' 如图1所示,具体为:在N衬底1上生长一层P+型外延层2,在P+型外延层2上生长一层P型外延层3,在P外延层区3内注入一层N+区4,并在N+区4浅注入一层P区6,从而形成两个PN结,可以吸收不同波长的注入光。在所述的P型外延层3上还设有深N+区5,深N十 4 is a hole accumulation type low substrate leak current of the inventive active pixel manufacturing process hole accumulation type active pixel manufacturing process flow diagram of a low village claim 5 of the present invention, the substrate leakage current schematic diagram of the hole accumulation type active pixel manufacturing process schematic diagram of FIG. 6 is a hole accumulation type to the invention the lower substrate leakage current active pixel manufacturing process schematic four; low substrate leakage current according to FIG. 7 of the present invention hole accumulation type active pixel manufacturing process schematic V. core particular embodiments of the present invention describes a new type of suitable active pixel for low dark current CMOS image sensor, the most fundamental characteristics of this type of active pixel comprising fabricated N-type silicon substrate, so that the feature low dark current of the present invention 'FIG. 1, in particular: the N substrate 1 is grown on a layer P, the + type epitaxial layer 2 in the P + type epitaxial layer 2 growing a P type epitaxial layer 3, injected within the P-epitaxial layer region 3 layer N + region 4, and injected into a layer of P region 6 in the N + region 4 shallow, so as to form two PN junctions injected light may absorb different wavelengths on the P-type epitaxial layer 3 is further provided with a deep N + region 5, a deep N + 5扩散至P+型外延层2,深N+区5与N+区4接触。在所述的两个结PN处将光量子转变为光电荷,其中电子积累在N+区4, 产生的空穴电荷积累在P区6靠近PN结的一边,很快被设于闪+区4上的偏置电压11吸走。在所述的P型外延层S上还设有N-阱10,在N-阱上生长有栅氧层8,在栅氧层上还生长有一层多晶硅层9;在N -阱10上还设有源漏区分别为源极7 与漏极13。多晶硅层9上设有传输栅12与栅极14,将电子电荷运走;当传输栅12上加一高电平,在栅氧化层8下形成一反型层,形成低的势垒,从而将电荷读出到NMOS ( N-channel metal oxide semiconductor, 中文:N通道金属氧化半导体)管的源极7。 5 diffuse into the P + type epitaxial layer 2 is the deep N + region 5 in contact with the N + region 4 of the two junctions PN at the photons into photocharge, wherein electrons accumulate in the N + region 4, a hole charges generated accumulated P regions 6 near the side of the PN junction, and soon is provided in flash + bias voltage region 411 sucked in the P-type epitaxial layer S is also a N- well 10, a N- well in growing a gate oxide layer 8 on the gate oxide layer is further grown a layer of polycrystalline silicon layer 9; in N - the well 10 is also provided with source and drain regions are provided with the transfer gate on the source electrode 7 and the drain electrode 13. the polycrystalline silicon layer 9 12 and the gate electrode 14, the electric charge carried away; when applied to a high level on the 12 transfer gate, forming an inversion layer under the gate oxide layer 8, a low barrier, such that the charge read out to the NMOS (N -channel metal oxide semiconductor, Chinese: N-channel metal oxide semiconductor) tube source 7. NMOS管制造在P型阱内,NMOS管的漏极是13, —般接在高电平上, 当栅极14加一高电平将NMOS管置位,源极7置位为高电平,当传输栅12为低电平时,光电荷读出,在NMOS管源极7将电荷积分转变为电压读出。 NMOS transistor fabricated within a P-type well, the drain of the NMOS transistor 13, - generally connected to the high level, when the gate 14 plus a high level of the NMOS transistor is set, the source electrode 7 is set to a high level when the transfer gate 12 is low, photocharge readout electrode 7 will charge integrator into a voltage in the NMOS transistor source read. ,流的空穴积累型有源像素的结构二如图2所示,其结构与图1所示的具体实现结构相似,区别在于在P型外延层上3设有窄沟道隔离区(shallowtrench isolation) 15, P区6设于窄沟道隔离区15下方。 Structural hole accumulation type active pixel stream two shown in Figure 2, is similar to the specific implementation structure shown in the structure of FIG. 1, except that in the P-type epitaxial layer 3 is provided with a narrow trench isolation region (shallowtrench isolation) 15, P region 6 disposed below the narrow channel isolation region 15. 为对本发明有进一步理解,下而再对本发明所述的低衬底漏电流的空穴积累型有源像素的制造方法进行说明。 For the further understanding of the invention, the lower and then drain a method for producing a hole accumulation-mode current active pixel in the low substrate of the present invention will be described. 以实施例一为例,本发明所述的低衬底漏电流的空穴积累型有源像素的制作工艺的具体实施方式具体包括以下制作处理过程:首先,如图3所示,在N型衬底1上外延生长P外延层2,然后,再在P+外延层2上面外延生长P外延层3,其厚度略大于后面的N -阱10的深度即可;其次,如图4所示,在P外延层3上热生长一层Si02 , Si02的厚度为100 埃〜150埃,其目的是减小P外延层3受到离子注入的损伤;当向P外延层3注入高能量、大剂量的磷离子,并经高温退火,激活磷离子后,注入形成深N十区5;由于P外延层3较薄,可以使深N+区5扩散到P外延层3中;第三,如图5所示,高能量、大剂量的磷离子注入到P外延层3中,经过短时间的高温退火,激活磷离子同时将其驱入适当的深度,形成N+区4。 Example a Example, hole accumulation type low substrate leakage current according to the present invention, an active pixel DETAILED DESCRIPTION production process includes the following production process: First, as shown in FIG. 3, the N-type substrate 1 epitaxially grown on the P epitaxial layer 2, and then again in the P + epitaxial layer 2 epitaxially grown P epitaxial layer 3 with a thickness slightly larger than the back of the N - well 10 depth can; secondly, shown in Figure 4, on the P epitaxial layer 3 is thermally grown layer of Si02, the thickness of the Si02 was 100 Å ~ 150 Å, which aims to reduce the P epitaxial layer 3 by ion implantation damage; when injecting a high energy, large doses of the P epitaxial layer 3 phosphorus ions, and high temperature annealing, after the activation of phosphorus ions implanted is formed a deep N + region 5; since the P epitaxial layer 3 is thin, can make a deep N + region 5 diffuse into the P-epitaxial layer 3; the third, shown in Figure 5 shown, high-energy, high-dose phosphorus ions are implanted into the P-epitaxial layer 3, high temperature short-time annealing, activating phosphorus ions while being driven into an appropriate depth, forming N + regions 4. 第四,如图6所示,生成读出电路中晶体管,读出电路中晶体管的生成与传统基于CMOS工艺中制作PMOS的工艺流程相同;首先,在外延层3中形成N-阱10,生长栅氧层8,在栅氧层8上长一层多晶硅层9,最后注入离子形成源极7和漏极13示;最后,如图7所示,为了防止将PMOS (P沟道金属氧化物半导体)的源漏极的驱深,在完成PMOS工艺后,要避免长时间的高温过程,所以,采用低温氧化LTO方法在N+4的表面生长一层Si02,作为减小离子注入损伤的保护层,然后,低能量、大剂量离子注入BF^,形成表面P区6,使用RTP (Rapid Temperature Process,快速温度处理)将其激活。 Fourth, as shown, generates the read six circuit transistors, the readout generate conventional circuit of the transistor in the same based process CMOS process produced a PMOS; First, N- well 10 is formed in the epitaxial layer 3, grown the gate oxide layer 8, on the 8 long gate oxide layer of polycrystalline silicon layer 9, and finally implanting ions to form a source electrode 7 and the drain electrode 13 are shown; Finally, as shown in FIG. 7, in order to prevent the PMOS (P-channel metal oxide semiconductor) source and drain of the driving depth, after completion of PMOS process, to avoid high temperature during such a long, therefore, low temperature oxidation LTO a surface 4 of growing a layer of Si02 in N +, as to reduce the ion protection effect of injection layer, and then, low energy, high dose ion implantation BF ^, forming surface of the P regions 6, using RTP (rapid temperature process, rapid temperature process) to activate it. 本发明的低衬底漏电流的空穴积累型有源像素的实施例二制造方法的工9艺流程具体实施方法,与实施例一的区别在P型外延层上3构造窄沟道隔离区15,然后在窄沟道隔离区15下方注入低能量、大剂量离子BF",形成表面P区6,使用RTP将其激活。该低衬底漏电流空穴积累型有源像素主要针对深亚微米工艺,由于采用窄沟道隔离技术将感光结面积与表面隔离,可以获得低的暗电流和高的感光灵敏度。暗电流的主要是由硅/二氧化硅之间的界面态或硅衬底的体态(bulk states)产生。通过在N+区的表面浅注入一层P区,将体内与表面分开,将光转变为电荷的PN结位于半导体的体内,从而将暗电流降低。该优点主要通过降低表面悬桂键对光产生电荷的影响。暗电流的主要是由硅/二氧化硅之间的界面态或硅衬底的体态(bulk states)产生。大多数情况下,界面产生是体内产生的 Workers two methods hole accumulation type low substrate according to the present invention, leakage current active pixel Manufacturing Example 9 process flow specific implementation methods, differs from the embodiment 1 of the P-type epitaxial layer 3 is configured narrow channel isolation region 15, and then injected under the narrow channel isolation region 15 low energy, high dose ion-BF ", is formed surface of the P regions 6, using the RTP to activate it. the lower substrate leakage current hole accumulation type active pixel mainly for deep sub micron technology, since narrow trench isolation techniques photosensitive junction area of ​​the surface of the separator can be obtained with low dark current and high photosensitivity. dark current is mainly made between the silicon / silicon dioxide interface state or a silicon substrate, posture (bulk states) produced by the surface of the N + region of the shallow implant layer P region to separate the body to the surface of the light into the PN junction within the semiconductor charge, so that the dark current is reduced. the advantages primarily by reduce the surface hanging Gui key light impact charges. dark current is mainly generated by the body interface states or silicon substrate between the silicon / silicon dioxide (bulk states). in most cases, the interface generation is generated in vivo of 倍。在N衬底上生长一层P+型外延层,在P+型外延层上生长一层P型外延层,在P外延层区内注入一层N+区,在N+区的表面浅注入一层P区,将体内与表面分开,将光转变为电荷的PN结位于半导体的体内,从而将暗电流降低,同时因为形成了两个PN结,增加了储存电荷的容量。利用N衬底可以有效的防止像素之间的光电荷的扩散。N衬底本身有像N+扩散漏极的效果。当像素本身因照射光太强的时候,产生的多余电荷将向相临像素扩散,如果不加以疏散,将形成弥散(blooming)现象。当一个直流电位加在N村底时,多余的电荷将被衬底收集, 而不会向相临的像素扩散,从而防止弥散现象。以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在 Times grown on the N substrate layer of P + type epitaxial layer, growing a P type epitaxial layer on a P + type epitaxial layer, the injection layer N + regions in the P-epitaxial layer region, shallow implant layer on the surface of N + region P region to separate the body to the surface of the light into the PN junction within the semiconductor charge, so that the dark current is reduced, at the same time due to the formation of the two PN junctions, increases the charge storage capacity. using N substrate can be effectively preventing diffusion .N photo charge between the pixel substrate itself as the N + diffusion effect of the drain when the excess charge pixels themselves by irradiation with light is too strong when generated will be adjacent pixel diffusion, if not evacuated, forming the dispersion (Blooming) phenomenon. when a DC potential when applied to the N village bottom, the excess charges will be the substrate collected, and does not spread to the pixel adjacent to thereby prevent diffusion phenomenon. the above are only present preferred invention specific embodiments, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the scope of the invention disclosed, may be varied or replaced easily thought, should fall 本发明的保护范围之内。因此,本发明的保护范围应该以权利要求的保护范围为准。 Within the scope of the invention. Accordingly, the scope of the present invention should be defined by the scope of the claims.

Claims (9)

  1. 1. 一种低衬底漏电流的空穴积累型有源像素,其特征在于,主体包括N型衬底、P+外延层与P型外延层;P+外延层生长于N衬底上,P型外延层生长于P+外延层上;所述的P型外延层还设有N+区,形成一个PN结;在N+区上还设有P区,形成另一个PN结;所述的P型外延层上还设有深N+区,深N+区扩散至P+外延层,且该深N+区与N+区相互接触。 A low-substrate-drain hole accumulation type active pixel current, wherein the body includes an N-type substrate, P + epitaxial layer and the P type epitaxial layer; P + epitaxial layer grown on an N substrate, P-type an epitaxial layer grown on a P + epitaxial layer; the P-type epitaxial layer is further provided with N + region to form a PN junction; on the N + region also has a P region formed in another PN junction; the P-type epitaxial layer on further provided with a deep N + region, a deep N + region diffusion to P + epitaxial layer, and the deep N + region and the N + region in contact with each other.
  2. 2、 根据权利要求1所述的一种低衬底漏电流的空穴积累型有源像素,其特征在于,所述的N+区上设有电极,该电极加有偏置电压。 2, a low-substrate hole accumulation type active pixel leak current according to claim 1, wherein the electrodes are provided on the N + region, the electrode is applied with a bias voltage.
  3. 3、 根据权利要求1所述的一种低衬底漏电流的空穴积累型有源像素,其特征在于,所述的P型外延层上还设有N-阱,在N-阱上生长有栅氧层,在4册氧层上还生长有一层多晶硅层;在N -阱上还设有源漏区。 3. A low substrate hole accumulation type active pixel leak current according to claim 1, characterized in that further provided N- well on a P-type epitaxial layer according grown on the N- well a gate oxide layer, on the four oxygen layer is further grown a layer of polysilicon layer; N - the well is also provided with source and drain regions.
  4. 4、 根据权利要求1、 2或3所述的一种低衬底漏电流的空穴积累型有源像素,其特征在于,所述的P型外延层上设有窄沟道隔离区,P区设于窄沟道隔离区下。 4, according to claim hole accumulation type active pixel of a low substrate 1, or claim 23 leakage current, characterized in that a narrow channel isolation region on a P-type epitaxial layer according to, P area located at the narrow trench isolation region.
  5. 5、 一种低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,包括:A、 在N型衬底上外延生长P +型外延层;B、 在P +型外延层上面外延生长P型外延层;C、 在P型外延层上设置深N+区,所述深N+区扩散至P+外延层,且该深N+区与N+区相互接触;D、 将磷离子注入到P外延层中,经过预定时间的高温退火,激活磷离子同时将其趋入,形成N+区;E、 生成读出电路的晶体管;F、 在N-阱的表面生长一层二氧化硅,注入离子BF",形成表面P区。 5, the manufacturing method of the hole accumulation-one low substrate leakage current active pixel, characterized in that, comprising: A, epitaxially grown P + type epitaxial layer on N-type substrate; B, the P + type epitaxial layer epitaxially grown P-type epitaxial layer; C, provided a deep N + region on the P-type epitaxial layer, the deep N + region diffusion to P + epitaxial layer, and the deep N + region and the N + region in contact with each other; D, the phosphorus ions implanted the P epitaxial layer, high temperature annealing for a predetermined time, the activation of phosphorus ions while being drive-in to form N + regions; E, and generates the read transistor circuit; F, the surface of N- well grown layer of silicon dioxide, implanting ions BF ", is formed surface of the P region.
  6. 6、 根据权利要求5所述的低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤C包括:C1、在P型外延层一热生长一层二氧化硅; C2、注入磷离子,激活磷离子,形成深N+区。 6, according to claim lower substrate 5 of the method for manufacturing a hole accumulation type current active pixel drain, characterized in that said step C comprises: C1, P-type epitaxial layer of a thermally grown layer of titanium silica; C2, phosphorus ions are implanted to activate phosphorus ions to form a deep N + region.
  7. 7、 根据权利要求6所述的低村底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤C1包括:生长的二氧化硅层厚度控制在100 埃-150埃。 Hole accumulation type low village bottom leakage current method of manufacturing an active pixel 7, as claimed in claim 6, wherein said step C1 comprises: silicon dioxide layer thickness of controlling the growth of 100 Angstroms -150 Egypt.
  8. 8、 根据权利要求5所述的低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤E包括:E1、在P型外延层中形成N-阱;E2、在N-阱上生长栅氧层;E3、在栅氧层上长一层多晶硅层层;E4、在N-阱上注入硼离子离子形成源漏区。 8, according to claim lower substrate 5 of the method for manufacturing a hole accumulation type current active pixel drain, wherein said step E comprising: E1, form a N- well in a P-type epitaxial layer; E2, in the N- well to grow the gate oxide layer; E3, on the gate oxide layer length a layer of polysilicon layers; E4, implanted boron ions form source and drain regions in the N- well.
  9. 9、 根据权利要求5所述的低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤F包括:F1、在P型外延层上做出窄沟道隔离区;F2、在窄沟道隔离区下方的N-阱的表面生长一层二氧化硅,注入低能量、大剂量离子注入BF2、形成表面P区。 9. The lower substrate as claimed in claim producing method of the hole accumulation type active pixel leakage current, characterized in that said step F comprises: F1, to make the narrow channel on the P-type epitaxial layer isolation region; F2 of, surface grown under the narrow channel isolation region of N- well layer of silicon dioxide, injection of low energy, high dose ion implantation BF2, is formed surface of the P region.
CN 200510083007 2005-07-12 2005-07-12 Low-substrate leakage current hole accumulating active picture element and producing method thereof CN100416845C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200510083007 CN100416845C (en) 2005-07-12 2005-07-12 Low-substrate leakage current hole accumulating active picture element and producing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200510083007 CN100416845C (en) 2005-07-12 2005-07-12 Low-substrate leakage current hole accumulating active picture element and producing method thereof

Publications (2)

Publication Number Publication Date
CN1889268A true CN1889268A (en) 2007-01-03
CN100416845C true CN100416845C (en) 2008-09-03

Family

ID=37578531

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200510083007 CN100416845C (en) 2005-07-12 2005-07-12 Low-substrate leakage current hole accumulating active picture element and producing method thereof

Country Status (1)

Country Link
CN (1) CN100416845C (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103337509B (en) * 2013-06-13 2015-10-28 中国兵器工业集团第二一四研究所苏州研发中心 Anti electron multiplying charge-coupled device structure and fabrication process dispersion

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1231516A (en) 1998-02-28 1999-10-13 现代电子产业株式会社 Complementary MOS image sensor and making method thereof
US6084259A (en) 1998-06-29 2000-07-04 Hyundai Electronics Industries Co., Ltd. Photodiode having charge transfer function and image sensor using the same
EP1028470A2 (en) 1999-02-09 2000-08-16 Sony Corporation Solid-state image-sensing device and method for producing the same
US6501109B1 (en) 2001-08-29 2002-12-31 Taiwan Semiconductor Manufacturing Company Active CMOS pixel with exponential output based on the GIDL mechanism
CN1889269A (en) 2005-07-12 2007-01-03 北京思比科微电子技术有限公司 Low-dark current active picture element adapted to CMOS image sensor and producing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1231516A (en) 1998-02-28 1999-10-13 现代电子产业株式会社 Complementary MOS image sensor and making method thereof
US6084259A (en) 1998-06-29 2000-07-04 Hyundai Electronics Industries Co., Ltd. Photodiode having charge transfer function and image sensor using the same
EP1028470A2 (en) 1999-02-09 2000-08-16 Sony Corporation Solid-state image-sensing device and method for producing the same
US6501109B1 (en) 2001-08-29 2002-12-31 Taiwan Semiconductor Manufacturing Company Active CMOS pixel with exponential output based on the GIDL mechanism
CN1889269A (en) 2005-07-12 2007-01-03 北京思比科微电子技术有限公司 Low-dark current active picture element adapted to CMOS image sensor and producing method thereof

Also Published As

Publication number Publication date Type
CN1889268A (en) 2007-01-03 application

Similar Documents

Publication Publication Date Title
US7091536B2 (en) Isolation process and structure for CMOS imagers
US6713796B1 (en) Isolated photodiode
US6885047B2 (en) Solid-state image sensing device having pixels with barrier layer underneath transistor regions and camera using said device
US6661459B1 (en) Solid state image pickup device with LDD structure and reset transistor
US20050051701A1 (en) Image sensor having pinned floating diffusion diode
US20070108371A1 (en) PMOS pixel structure with low cross talk for active pixel image sensors
US6350127B1 (en) Method of manufacturing for CMOS image sensor
US20060118835A1 (en) Predoped transfer gate for an image sensor
US6329679B1 (en) Photodiode with increased photocollection area for image sensor
US7205627B2 (en) Image sensor cells
US20030169360A1 (en) Twin p-well CMOS imager
JPH11284166A (en) Solid-state imaging device
US20100224766A1 (en) Solid-state image device manufacturing method thereof, and image capturing apparatus
US7115925B2 (en) Image sensor and pixel having an optimized floating diffusion
CN101707202A (en) Semiconductor photosensitization device, production method and application thereof
JP2001053260A (en) Solid-state image pickup element and manufacture thereof
US6218210B1 (en) Method for fabricating image sensor with extended pinned photodiode
US6660553B2 (en) Semiconductor device having solid-state image sensor with suppressed variation in impurity concentration distribution within semiconductor substrate, and method of manufacturing the same
US20060275990A1 (en) Semiconductor device and method of producing same
US20060273359A1 (en) Solid state imaging device, camera, and method for fabricating solid state imaging device
US20070218613A1 (en) Fully isolated photodiode stack
US20070246756A1 (en) Image sensor with SOI substrate
US20100108864A1 (en) Solid-state imaging device, manufacturing method of the same, and imaging apparatus
US7408211B2 (en) Transfer transistor of CMOS image sensor
US20010000623A1 (en) Solid-state image sensor

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C14 Grant of patent or utility model
C56 Change in the name or address of the patentee

Owner name: BEIJING SUPERPIX MICRO TECHNOLOGY LIMITED

Free format text: FORMER NAME: SIBIKE MICROELECTRONIC TECH CO., LTD., BEIJING

CF01