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CN100416845C - Low-substrate leakage current hole accumulating active picture element and producing method thereof - Google Patents

Low-substrate leakage current hole accumulating active picture element and producing method thereof Download PDF

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CN100416845C
CN100416845C CN 200510083007 CN200510083007A CN100416845C CN 100416845 C CN100416845 C CN 100416845C CN 200510083007 CN200510083007 CN 200510083007 CN 200510083007 A CN200510083007 A CN 200510083007A CN 100416845 C CN100416845 C CN 100416845C
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picture
substrate
leakage
method
current
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CN 200510083007
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CN1889268A (en )
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金湘亮
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北京思比科微电子技术有限公司
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Abstract

本发明的低衬底漏电流的空穴积累型有源像素的在N衬底上生长一层P+型外延层,在P+型外延层上生长一层P型外延层,在P外延层区内注入一层N+区,并在N+区浅注入一层P区,从而形成两个PN结,可以吸收不同波长的注入光。 Low substrate of the present invention, the leakage current of the active pixel-type hole accumulation layer grown P + type epitaxial layer on an N substrate, growing a P type epitaxial layer on a P + type epitaxial layer, the epitaxial layer region in the P N + region implanted layer, and a shallow implanted P region a layer of N + region, thereby forming two PN junction, the injection may absorb light of different wavelengths. 本发明提出的是一种基于N衬底和光电二极管的有源像素结构,这种低衬底漏电流的空穴积累型有源像素结构有效的降低了暗电流、提高了量子效率。 Proposed by the present invention is an active pixel photodiode structure N based on the substrate, the substrate hole accumulation type low-leakage current of such active pixel architecture effectively reduces the dark current and improve quantum efficiency. 利用N衬底可以有效的防止像素之间的光电荷的扩散,防止弥散现象。 N substrate by using a diffusion light charge between the pixels can effectively prevent, prevent diffusion phenomenon.

Description

低衬底漏电流的空穴积累型有源像素及其制造方法技术领域本发明涉及微电子学的集成电路设计技术领域,尤其涉及一种低衬底漏电流的空穴积累型有源^象素及其制造方法。 Active pixel hole accumulation TECHNICAL FIELD The substrate of low leakage current The invention relates to the field of integrated circuit design technology of microelectronics, in particular, relates to a low-type hole accumulation substrate leakage current as active ^ hormone and its manufacturing method. 背景技术经过十几年的研究,CMOS ( Complementary Metal-Oxide-Semiconductor Transistor ,中文:互补从属氧化物半导体)图像传感器在某些性能方面取得了明显改善,但在噪声和成像质量等方面都比不上CCD (Charge Coupled Device,中文:电荷耦合器件)图Y象传感器。 BACKGROUND after ten years of research, CMOS (Complementary Metal-Oxide-Semiconductor Transistor, Chinese: complement dependent Oxide Semiconductor) image sensor has made significant improvements in certain properties, but not better than the image quality in terms of noise and the like a CCD (Charge Coupled device, Chinese: Charge Coupled device) image sensor Y of FIG. 相对于CCD图像传感器技术而言,基于CMOS工艺的图像传感器具有成本低、功耗低、便于大规^t集成等优点。 With respect to the CCD image sensor technology, CMOS-based image sensor having a low cost, low power consumption, to facilitate large-scale integration, etc. ^ t. 尤其是随着CMOS工艺的特征尺寸按等比例原则进一步缩小,对某些应用来说,CMOS图像传感器技术某些性能的优势更加突出。 Especially as the feature size of the CMOS process further refine the principle according equal proportions, for some applications, certain performance advantages of the CMOS image sensor technology is more prominent. CMOS图像传感器技术能够单芯片集成许多附加电路,如电源管理电路、图像处理电路、图像压缩电路等;同时CMOS器件中的像素单元可以作得比较小,能够提供比CCD图像传感器更高分辨率的图像器件。 CMOS image sensor technology can be a number of additional single-chip integrated circuit, such as power management circuit, image processing circuit, an image compression circuit or the like; the same unit pixel in a CMOS device can be made relatively small, can provide a higher resolution than that of the CCD image sensor image device. 目前,用于CMOS图像传感器结构的像素单元主要有无源像素结构和有源像素结构。 Currently, the pixel structure of the CMOS image sensor means for mainly passive pixel structure and the active pixel architecture. 无源像素结构的最大优点是像素内只集成一个晶体管,能获得大的填充系数;电路结构不复杂、寻址简单、获得的成品率高,因而价格低。 The biggest advantage of the passive pixel structure is integrated only one transistor within the pixel can obtain a large fill factor; circuit configuration is not complicated, simple addressing, obtained in high yield, and therefore low price. 但无源像素的列总线等效的电阻和电容比较大,使得像素读出的速度慢,特别是当像素阵列比较大时,由列总线带来的信号延迟和信号损失非常大;其次无源像素读出的噪声较大,信号电荷的损失随着列总线的增长而变大,降低了信噪比。 However, passive pixel column bus of the equivalent resistance and capacitance is large, such that pixel readout slow speed, particularly when a relatively large array of pixels, signal delay and signal loss caused by the very large column bus; second passive the noisy pixel readout, signal charge loss with increasing column bus becomes large, reducing the signal to noise ratio. 因为上述缺点限制了应用,很快被后来发展的有源像素结构代替。 Because of these shortcomings have limited the application of active pixel structure was soon replaced by later development. 有源像素内部包含一个有源器件,即包含一个由一个或多个晶体管组成的放大器,通常由源跟随晶体管构成,该放大器在像素内部具有放大和緩冲功能, 电荷不需要经过远距离而到达输出放大器,在列总线直接输出的是电压或电流信号,因此避免了像无源像素内的信号电荷必须经过很长列总线才能到达放大器的缺陷。 Internal active pixel includes an active device, i.e., comprising an amplifier of one or more transistors, usually composed of a source follower transistor, this amplifier having a function of amplifying and buffering inside the pixel, a charge to the output does not need to undergo long and amplifier, the output column bus is a direct voltage or current signal, thus avoiding the signal charges in the image must pass through a long passive pixel column bus to reach the amplifier defect. 目前,基于标准的CMOS制造过程的常用有源像素结构是包括三个晶体管和一个N+/P-阱的光电二极管,^旦这种有源4象素具有较大的暗电流,大大影响了CMOS图像传感器的动态范围,更严重的是大的暗电流将造成CMOS 图像传感器出现白点。 Currently, based on common standard structure of a CMOS active pixel manufacturing process comprising three transistors and a photodiode N + / P- well, ^ 4 once such an active pixel has a large dark current, greatly affect the CMOS the dynamic range of the image sensor, the more serious is the large dark current caused by the CMOS image sensor has white spots. 另一种有源像素结构的设计是基于P型衬底的钉扎型光电二极管,这种光电二极管具有表面暗电流低、对蓝光具有良好的响应特性。 Another design is based on the configuration of active pixel pinned photodiode P-type substrate, the photodiode having a surface low dark current, good response characteristics to blue light. 但该种结构的光电二极管依然没有改变CMOS工艺的本质特征,因此减少的暗电流并不很明显。 However, this type of photodiode structure remains unchanged essential characteristics of the CMOS process, thereby reducing dark current is not obvious. 发明内容鉴于上述现有技术所存在的问题,本发明的目的是提供一种低衬底漏电流的空穴积累型有源像素及其制造方法,制作在N型硅衬底上,从而获得低暗电流的特征。 In view of the above-described problems of the prior art, an object of the present invention is to provide a low leakage current of the substrate accumulation-hole and a manufacturing method of the active pixel, formed on N-type silicon substrate, thereby obtaining a low characterized in dark current. 本发明的目的是通过以下技术方案实现的:一种低衬底漏电流的空穴积累型有源像素,主体包括N型村底、P +外延层与P型外延层;P +外延层生长于N衬底上,P型外延层生长于P +外延层上;所述的? Object of the present invention is achieved by the following technical solution: a low-type hole accumulation leakage current active pixel substrate, an N-type body comprises a bottom village, P + epitaxial layer and the P type epitaxial layer; P + epitaxial layer grown on the N substrate, P-type epitaxial layer grown on a P + epitaxial layer; said? 型外延层还设有閃+区,形成一个PN结;在N+区上还设有P区,形成另一个PN结;所述的P型外延层上还设有深N+区,深N+区扩散至P+外延层,且该深N+区与N+区相互接触。 There is also a flash-type epitaxial layer + region forming a PN junction; on the N + region also has a P region, another PN junction is formed; also a deep N + region on the P-type epitaxial layer, the deep N + diffusion region to P + epitaxial layer, the deep N + region and the N + region in contact with each other. 所述的N+区上设有电极,该电极加有偏置电压。 Said N + region is provided on the electrode, the electrode is applied with a bias voltage. . 所述的P型外延层上还设有N-阱,在N-阱上生长有栅氧层,在栅氧层上还生长有一层多晶硅层;在N-阱上还设有源漏区。 The P-type epitaxial layer is further provided N- well, N- well grown on the gate oxide layer, a polysilicon layer is also grown on the gate oxide layer; N- well is also provided on the source and drain regions. 所述的P型外延层上设有窄沟道隔离区,P区设于窄沟道隔离区下。 Narrow channel is provided on the isolation region of the P-type epitaxial layer, P channel region disposed at a narrow isolation region. 一种基于上述低衬底漏电流的空穴积累型有源像素的制造方法,包括:A、 在N型衬底上外延生长P +型外延层;B、 在P +型外延层上面外延生长P型外延层;C、 在P型外延层上设置深N+区,所述深N+区扩散至P+外延层,且该深N+区与N+区相互接触;D、 将磷离子注入到P外延层3中,经过预定时间的高温退火,激活磷离子同时将其趋入,形成N+区;E、 生成读出电路的晶体管;F、 在N-阱的表面生长一层二氧化硅,注入离子注入BF^,形成表面P区。 A method for producing the above-described hole accumulation type low leakage current substrate-based active pixel, comprising: A, epitaxially grown P + type epitaxial layer on N-type substrate; B, the P + type epitaxial layer epitaxially grown P-type epitaxial layer; C, provided a deep N + region on the P-type epitaxial layer, the deep N + region diffusion to P + epitaxial layer, and the deep N + region and the N + region in contact with each other; D, the phosphorus ions implanted into the P epilayer 3, the high temperature annealing after a predetermined time, while the activation of phosphorus ions into the chemotaxis, the N + region; E, generates a readout circuit transistor; F, the surface of the growth layer of silicon dioxide N- well implanted ion implantation BF ^, P region to form a surface. 所述的步骤C包括:生长的二氧化硅层厚度控制在100埃〜150埃。 Said step C comprising: a silicon dioxide layer of a thickness of 100 angstroms in controlling the growth of ~150 Å. 所述的步骤E还包括: E1、在P型外延层中形成N-阱; E2、在N-阱上生长栅氧层; E3、在栅氧层上长一层多晶硅层层; E4、在N-阱上注入硼离子离子形成源漏区。 Said step E further comprising: E1, formed in a P-type epitaxial layer N- well; E2, N- well grown on the gate oxide layer; E3, on the length of the gate oxide layer a layer of polysilicon layers; E4, in boron ions on the ion implantation source and drain regions formed in the N- well. 所述的步骤F还包括: F1、在P型外延层上做出窄沟道隔离区;F2、在窄沟道隔离区下方的N-阱的表面生长一层二氧化硅,注入低能量、大剂量离子注入BF",形成表面P区。由上述本发明提供的技术方案可以看出,本发明的低衬底漏电流的空穴积累型有源像素的在N衬底上生长一层P+型外延层,在P+型外延层上生长一层P型外延层,在P外延层区内注入一层N+区,并在N+区浅注入一层P区, 从而形成两个PN结,可以吸收不同波长的注入光。本发明提出的是一种基于N衬底和光电二极管的有源像素结构,这种低衬底漏电流的空穴积累型有源像素结构有效的降低了暗电流、提高了量子效率。附图说明图1为本发明所述的低衬底漏电流的空穴积累型有源像素结构示意图一; 图2为本发明所述的低衬底漏电流的空穴积累型有源像素结构示意图二; 图3为本发明所述的低村底漏 Said step F further includes: F1, to make the narrow trench isolation regions on a P type epitaxial layer; F2 of, the surface of N- well below the narrow channel isolation region growing a layer of silicon dioxide, low energy implantation, high dose ion implantation BF ", P region to form a surface provided by the technical solution of the present invention can be seen, hole accumulation type low substrate according to the present invention, the leakage current of the active layer of the pixel P is grown on the N + substrate type epitaxial layer grown on the P + type epitaxial layer of P-type epitaxial layer, a layer of implanted N + regions in the P-epitaxial layer region, and a shallow implanted P region a layer of N + region, thereby forming two PN junction can absorb injection of different wavelengths of light. the present invention is made of an active pixel photodiode structure N based on the substrate, the substrate hole accumulation type low-leakage current of such active pixel architecture effectively reduces the dark current, improving FIG quantum efficiency of 1 active pixel-type hole accumulation structure of the present invention, a low leakage current diagram of a substrate; Figure 2 according to the present invention, a low leakage current of the substrate accumulation-mode cavity two structural diagram of an active pixel; FIG. 3 of the present invention, a low leakage bottom village 流的空穴积累型有源像素制造过程示意图图4为本发明所述的低衬底漏电流的空穴积累型有源像素制造过程示意图图5为本发明所述的低村底漏电流的空穴积累型有源像素制造过程示意图图6为本发明所述的低衬底漏电流的空穴积累型有源像素制造过程示意图四;图7为本发明所述的低衬底漏电流的空穴积累型有源像素制造过程示意图五。具体实施方式本发明的核心描述了一种新型适用于CMOS图像传感器的低暗电流的有源像素,该种有源像素最根本的特点在于制作在N型硅衬底上,从而获得低暗电流的特征。本发明的' 如图1所示,具体为:在N衬底1上生长一层P+型外延层2,在P+型外延层2上生长一层P型外延层3,在P外延层区3内注入一层N+区4,并在N+区4浅注入一层P区6,从而形成两个PN结,可以吸收不同波长的注入光。在所述的P型外延层3上还设有深N+区5,深N十 4 is a hole accumulation type low substrate leak current of the manufacturing process of the present invention the active pixel-type hole accumulation of active pixel manufacturing process flow diagram of a low village 5 of the present invention according to a schematic view of the bottom leakage current the active pixel-type hole accumulation FIG. 6 is a schematic manufacturing process of hole accumulation type according to the invention a low leakage current active pixel substrate manufacturing process schematic four; low substrate leakage current according to the present invention. FIG. 7 the active pixel-type hole accumulation manufacturing process schematic V. DETAILED core embodiment of the present invention describes a new type suitable for low dark current active pixel CMOS image sensor, the most fundamental characteristics of this type of active pixel produced in that N-type silicon substrate, so that the feature of the present invention, low dark current 'of FIG. 1, in particular: the N-P layer is grown on the substrate 1, + type epitaxial layer 2 on the P + type epitaxial layer 2 growing a P type epitaxial layer 3, P injected into the epitaxial layer of N + layer region 3 region 4, and a layer of P implanted region 6 in a shallow N + region 4, thereby forming two PN junction, the injection may absorb light of different wavelengths on the P-type epitaxial layer 3 is further provided with a deep N + region 5, N + deep 5扩散至P+型外延层2,深N+区5与N+区4接触。在所述的两个结PN处将光量子转变为光电荷,其中电子积累在N+区4, 产生的空穴电荷积累在P区6靠近PN结的一边,很快被设于闪+区4上的偏置电压11吸走。在所述的P型外延层S上还设有N-阱10,在N-阱上生长有栅氧层8,在栅氧层上还生长有一层多晶硅层9;在N -阱10上还设有源漏区分别为源极7 与漏极13。多晶硅层9上设有传输栅12与栅极14,将电子电荷运走;当传输栅12上加一高电平,在栅氧化层8下形成一反型层,形成低的势垒,从而将电荷读出到NMOS ( N-channel metal oxide semiconductor, 中文:N通道金属氧化半导体)管的源极7。 5 diffuse into the P + type epitaxial layer 2 is the deep N + region 5 in contact with the N + region 4 of the two junctions PN at the photons into photocharge, wherein electrons accumulate in the N + region 4, a hole charges generated accumulated P regions 6 near the side of the PN junction, provided by flash quickly on the bias voltage + region 411 sucked in the P-type epitaxial layer S is also a N- well 10, a N- well in gate oxide layer 8 is grown on the gate oxide layer grown further layer of polysilicon layer 9; the N - well 10 is also provided on the source and drain regions are provided on the transmission gate 13. the source electrode 7 and the drain polysilicon layer 9 12 and the gate electrode 14, the electric charge carried away; plus a high level when the transfer gate 12, an inversion layer is formed under the gate oxide layer 8, a low potential barrier is formed, so that the charge read out to the NMOS (N the source 7 N-channel metal oxide semiconductor) tube: -channel metal oxide semiconductor, Chinese. NMOS管制造在P型阱内,NMOS管的漏极是13, —般接在高电平上, 当栅极14加一高电平将NMOS管置位,源极7置位为高电平,当传输栅12为低电平时,光电荷读出,在NMOS管源极7将电荷积分转变为电压读出。 NMOS transistor fabricated within a P-type well, the drain of the NMOS transistor 13 is - like connected to the high level, plus a high level when the gate 14 is set to the NMOS transistor, the source electrode 7 is set to a high level when the transfer gate 12 is low, the light charge readout, the charge integrator electrode 7 into the NMOS transistor source voltage readout. ,流的空穴积累型有源像素的结构二如图2所示,其结构与图1所示的具体实现结构相似,区别在于在P型外延层上3设有窄沟道隔离区(shallowtrench isolation) 15, P区6设于窄沟道隔离区15下方。 , Hole accumulation structure of the active pixel-type two streams shown in Figure 2, the specific implementation structure is similar to the structure shown in FIG. 1, except that in the P-type epitaxial layer 3 is provided with a narrow trench isolation region (shallowtrench isolation) 15, P region 6 narrow channel disposed below the isolation region 15. 为对本发明有进一步理解,下而再对本发明所述的低衬底漏电流的空穴积累型有源像素的制造方法进行说明。 There is a further understanding of the invention, the method of manufacturing the hole and then the drain current of the accumulation-mode active pixel of the lower substrate of the present invention will be described. 以实施例一为例,本发明所述的低衬底漏电流的空穴积累型有源像素的制作工艺的具体实施方式具体包括以下制作处理过程:首先,如图3所示,在N型衬底1上外延生长P外延层2,然后,再在P+外延层2上面外延生长P外延层3,其厚度略大于后面的N -阱10的深度即可;其次,如图4所示,在P外延层3上热生长一层Si02 , Si02的厚度为100 埃〜150埃,其目的是减小P外延层3受到离子注入的损伤;当向P外延层3注入高能量、大剂量的磷离子,并经高温退火,激活磷离子后,注入形成深N十区5;由于P外延层3较薄,可以使深N+区5扩散到P外延层3中;第三,如图5所示,高能量、大剂量的磷离子注入到P外延层3中,经过短时间的高温退火,激活磷离子同时将其驱入适当的深度,形成N+区4。 In one embodiment, as an example, the substrate hole accumulation type low leakage current according to the present invention, the active pixel DETAILED DESCRIPTION production process includes the following production process: First, as shown in FIG. 3, the N-type 1 is epitaxially grown on the substrate P epitaxial layer 2, and then the P + epitaxial layer 2 is epitaxially grown above the P epitaxial layer 3 having a thickness slightly larger than the latter N - well 10 to depth; second, shown in Figure 4, epitaxial layer 3 on the P layer of thermally grown Si02, Si02 thickness of ~150 Å 100 Å, which aims to reduce the P epitaxial layer 3 by ion implantation damage; when injecting a high energy, large doses of the epitaxial layer 3 to P phosphorus ions and annealed at high temperature, after activation of phosphorus ions implanted is formed a deep N + region 5; since the P epitaxial layer 3 is thin, can make a deep N + diffusion region 5 into the P-epitaxial layer 3; the third, shown in Figure 5 shown, high-energy, high-dose implantation of phosphorus ions into the P-epitaxial layer 3, after a short-time high-temperature annealing to activate the phosphorous ions while being driven into an appropriate depth, forming N + regions 4. 第四,如图6所示,生成读出电路中晶体管,读出电路中晶体管的生成与传统基于CMOS工艺中制作PMOS的工艺流程相同;首先,在外延层3中形成N-阱10,生长栅氧层8,在栅氧层8上长一层多晶硅层9,最后注入离子形成源极7和漏极13示;最后,如图7所示,为了防止将PMOS (P沟道金属氧化物半导体)的源漏极的驱深,在完成PMOS工艺后,要避免长时间的高温过程,所以,采用低温氧化LTO方法在N+4的表面生长一层Si02,作为减小离子注入损伤的保护层,然后,低能量、大剂量离子注入BF^,形成表面P区6,使用RTP (Rapid Temperature Process,快速温度处理)将其激活。 Fourth, as shown in FIG circuit 6 generates the read transistor, the read transistor circuit generating the conventional process based on the same CMOS process produced a PMOS; First, N- well 10 is formed in the epitaxial layer 3, grown the gate oxide layer 8, 8 on the gate oxide layer of the long polysilicon layer 9, and finally the ion implantation forming the source electrode 7 and the drain electrode 13 are shown; Finally, as shown in FIG. 7, in order to prevent the PMOS (P-channel metal oxide semiconductor) deep source and drain of the drive, after the completion of PMOS process, to avoid high temperature during such a long, therefore, low temperature oxidation method of the surface 4 of the LTO Si02 layer grown on N +, as to reduce the ion implantation damage protection layer, and then, low energy, high dose ion implantation BF ^, P region to form a surface 6, using the RTP (rapid temperature process, rapid temperature process) to activate it. 本发明的低衬底漏电流的空穴积累型有源像素的实施例二制造方法的工9艺流程具体实施方法,与实施例一的区别在P型外延层上3构造窄沟道隔离区15,然后在窄沟道隔离区15下方注入低能量、大剂量离子BF",形成表面P区6,使用RTP将其激活。该低衬底漏电流空穴积累型有源像素主要针对深亚微米工艺,由于采用窄沟道隔离技术将感光结面积与表面隔离,可以获得低的暗电流和高的感光灵敏度。暗电流的主要是由硅/二氧化硅之间的界面态或硅衬底的体态(bulk states)产生。通过在N+区的表面浅注入一层P区,将体内与表面分开,将光转变为电荷的PN结位于半导体的体内,从而将暗电流降低。该优点主要通过降低表面悬桂键对光产生电荷的影响。暗电流的主要是由硅/二氧化硅之间的界面态或硅衬底的体态(bulk states)产生。大多数情况下,界面产生是体内产生的 The method of working of two hole accumulation type low substrate according to the present invention, the leakage current active pixel Manufacturing Example 9 particular embodiment process flow method differs from the embodiment of the embodiment in a P-type epitaxial layer 3 on the narrow channel isolation region configured 15, and then injected into the narrow channel below the isolation region 15 of low energy, high dose ion-BF ", is formed surface of the P region 6, to activate it using the RTP. the lower substrate leakage current active pixel-type hole accumulation mainly for deep sub micron technology, since narrow channel isolation junction area of ​​the surface of the photosensitive isolated, low dark current can be obtained and a high photosensitivity. mainly by dark current between the silicon / silicon dioxide interface states or silicon substrate posture (bulk states) produced by the surface of the N + region of the shallow implant layer P region to separate the body to the surface of the light into the PN junction within the semiconductor charge, so that the dark current is reduced. the advantages primarily by Gui key hanging light to reduce the surface charge of impact. the dark current is generated by the main body of the interface state between a silicon substrate or silicon / silicon dioxide (bulk states). in most cases, it is produced in vivo generated at the interface of 倍。在N衬底上生长一层P+型外延层,在P+型外延层上生长一层P型外延层,在P外延层区内注入一层N+区,在N+区的表面浅注入一层P区,将体内与表面分开,将光转变为电荷的PN结位于半导体的体内,从而将暗电流降低,同时因为形成了两个PN结,增加了储存电荷的容量。利用N衬底可以有效的防止像素之间的光电荷的扩散。N衬底本身有像N+扩散漏极的效果。当像素本身因照射光太强的时候,产生的多余电荷将向相临像素扩散,如果不加以疏散,将形成弥散(blooming)现象。当一个直流电位加在N村底时,多余的电荷将被衬底收集, 而不会向相临的像素扩散,从而防止弥散现象。以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在 Times N substrate layer grown on the P + type epitaxial layer, a layer of P-type epitaxial layer grown on a P + type epitaxial layer, a layer of implanted N + regions in the P-epitaxial layer region, a shallow N + implanted layer in a surface region P region, the surface of the body to separate the light into the PN junction of the semiconductor body of charge, thereby reducing the dark current, and because of the two PN junctions are formed, the charge storage capacity is increased. the substrate may be effectively utilize N .N photocharge preventing diffusion between the substrate itself as the pixel N + drain diffusion effect. when the pixel itself due to the extra charge when irradiated with light is too strong, will be generated adjacent pixel diffusion, if not evacuated, the dispersion is formed (Blooming) phenomenon. when a DC potential is applied when the end of the village of N, the excess charges will be collected by the substrate, and does not spread to adjacent pixels, thereby preventing the phenomenon of dispersion. the above are only present DETAILED DESCRIPTION preferred embodiments of the present invention, but the scope of the present invention is not limited thereto, any skilled in the art in the art within the technical scope of the present invention is disclosed, variations may occur easily, or alternatively, should fall 本发明的保护范围之内。因此,本发明的保护范围应该以权利要求的保护范围为准。 Within the scope of the invention. Accordingly, the scope of the present invention should be defined by the scope of the claims.

Claims (9)

1. 一种低衬底漏电流的空穴积累型有源像素,其特征在于,主体包括N型衬底、P+外延层与P型外延层;P+外延层生长于N衬底上,P型外延层生长于P+外延层上;所述的P型外延层还设有N+区,形成一个PN结;在N+区上还设有P区,形成另一个PN结;所述的P型外延层上还设有深N+区,深N+区扩散至P+外延层,且该深N+区与N+区相互接触。 A hole accumulation type low substrate leakage current in active pixel, wherein the body includes an N-type substrate, P + epitaxial layer and the P type epitaxial layer; P + N epitaxial layer is grown on the substrate, a P-type an epitaxial layer grown on a P + epitaxial layer; the P-type epitaxial layer is further provided with N + region forming a PN junction; on the N + region also has a P region, another PN junction is formed; the P-type epitaxial layer There is also a deep N + region, a deep N + region diffusion to P + epitaxial layer, the deep N + region and the N + region in contact with each other.
2、 根据权利要求1所述的一种低衬底漏电流的空穴积累型有源像素,其特征在于,所述的N+区上设有电极,该电极加有偏置电压。 2, a low-active type hole accumulation substrate leak current of the pixel according to claim 1, wherein said electrodes are provided on the N + region, there is a bias voltage applied to the electrode.
3、 根据权利要求1所述的一种低衬底漏电流的空穴积累型有源像素,其特征在于,所述的P型外延层上还设有N-阱,在N-阱上生长有栅氧层,在4册氧层上还生长有一层多晶硅层;在N -阱上还设有源漏区。 3, a low-active type hole accumulation substrate leak current of the pixel according to claim 1, wherein further provided on the P-well N- type epitaxial layer according grown on the N- well a gate oxide layer on the oxide layer 4 is also grown layer of polysilicon layer; N - trap is further provided on the source and drain regions.
4、 根据权利要求1、 2或3所述的一种低衬底漏电流的空穴积累型有源像素,其特征在于,所述的P型外延层上设有窄沟道隔离区,P区设于窄沟道隔离区下。 4, according to claim active pixel-type hole accumulation of a low substrate 1, or the leakage current in claim 23, characterized in that the narrow channel is provided on the isolation region of the P-type epitaxial layer, P a channel region disposed at a narrow isolation region.
5、 一种低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,包括:A、 在N型衬底上外延生长P +型外延层;B、 在P +型外延层上面外延生长P型外延层;C、 在P型外延层上设置深N+区,所述深N+区扩散至P+外延层,且该深N+区与N+区相互接触;D、 将磷离子注入到P外延层中,经过预定时间的高温退火,激活磷离子同时将其趋入,形成N+区;E、 生成读出电路的晶体管;F、 在N-阱的表面生长一层二氧化硅,注入离子BF",形成表面P区。 5, hole accumulation type method for producing a low-leakage current active pixel substrate, characterized in that, comprising: A, epitaxially grown P + type epitaxial layer on N-type substrate; B, the P + type epitaxial layer epitaxially grown P-type epitaxial layer; C, provided a deep N + region on the P-type epitaxial layer, the deep N + region diffusion to P + epitaxial layer, and the deep N + region and the N + region in contact with each other; D, the phosphorus ions implanted P into the epitaxial layer, high temperature annealing after a predetermined time, while the activation of phosphorus ions into the chemotaxis, the N + region; E, and generates the read transistor circuit; F, the surface of N- well grown layer of silicon dioxide, implanting ions BF ", is formed surface of the P region.
6、 根据权利要求5所述的低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤C包括:C1、在P型外延层一热生长一层二氧化硅; C2、注入磷离子,激活磷离子,形成深N+区。 6, according to claim 5, wherein the lower substrate manufacturing method of claim hole accumulation type active pixel drain current, wherein said step C comprises: C1, a P-type epitaxial layer thermally grown layer of titanium silica; C2, implanted phosphorus ions, phosphorus ions are activated to form a deep N + region.
7、 根据权利要求6所述的低村底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤C1包括:生长的二氧化硅层厚度控制在100 埃-150埃。 Village bottom hole accumulation type low leakage current method of manufacturing an active pixel 7, as claimed in claim 6, wherein said step C1 comprises: growing a silicon dioxide layer thickness is controlled at 100 Å -150 Egypt.
8、 根据权利要求5所述的低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤E包括:E1、在P型外延层中形成N-阱;E2、在N-阱上生长栅氧层;E3、在栅氧层上长一层多晶硅层层;E4、在N-阱上注入硼离子离子形成源漏区。 8, according to claim 5, wherein the lower substrate manufacturing method of claim hole accumulation type active pixel drain current, wherein said step E comprising: E1, N- well is formed in the P type epitaxial layer; E2, N- well grown on the gate oxide layer; E3, on the length of the gate oxide layer a layer of polysilicon layers; E4, ion implantation of boron ions to form source and drain regions in the N- well.
9、 根据权利要求5所述的低衬底漏电流的空穴积累型有源像素的制造方法,其特征在于,所述的步骤F包括:F1、在P型外延层上做出窄沟道隔离区;F2、在窄沟道隔离区下方的N-阱的表面生长一层二氧化硅,注入低能量、大剂量离子注入BF2、形成表面P区。 9, the substrate 5 according to the low manufacturing method according to claim active pixel-type hole accumulation of leak current, characterized in that said step F comprises: F1, to make the narrow channel in the P-type epitaxial layer isolation region; F2 of, narrow channel below the surface of the growth in the isolation region of N- well layer of silicon dioxide, low implantation energy, high dose ion implantation BF2, P region to form a surface.
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