CN100485966C - High-voltage P-type metal oxide transistor and producing method thereof - Google Patents

Abstract

A method for preparing high voltage P type of metal oxide semiconductor tube includes setting P type of drift region with P type of drain and N type of trap with N type of contact hole and P type of source on P type of substrate, arranging grate oxidation layer on said trap and drift region, setting poly-silicon grate above oxidation layer, setting field oxidation layer above grate oxidation layer and said grate, arranging poly-silicon field polar plate in field oxidation layer, forming P type of drift region by four regions and setting doping concentration of four region to be one greater than another.

Description

High-voltage P-type metal oxide transistor and preparation method thereof

Technical field

The present invention is a kind of MOS (metal-oxide-semiconductor) transistor and preparation method thereof, especially high-voltage P-type metal oxide transistor and preparation method thereof.

Background technology

The MOS type power device has advantages such as switching characteristic is good, power consumption is little, what is more important MOS type power device is easy to compatibility standard low pressure metal oxide semiconductor technology, reduce production cost of chip, therefore in the range of application of 10V-600V, the MOS type power device is widely used in the power integrated circuit, puncture voltage and conducting resistance are two most important parameters of high-voltage metal oxide semiconductor device, it also is a pair of paradox, puncture voltage improves, and conducting resistance will correspondingly increase.Recently, some new technologies or new construction occur and overcome above shortcoming, promptly when improving puncture voltage, do not increased conducting resistance, as many field plates structure, multidimensional grid structure, linear injection in drift region or the like.But the linear injection technique in the drift region that proposes is an one dimension at present, does not consider the influence of different oxidated layer thickness and field plate, and is therefore comprehensive not enough.

Summary of the invention

The invention provides a kind of can improve withstand voltage, reduce conducting resistance, and the high-voltage P-type metal oxide transistor that injects with the compatible mutually drift region piecewise linearity of standard epitaxial metal oxide semiconductor technology and preparation method thereof.

Product technology scheme of the present invention is as follows:

A kind of high-voltage P-type metal oxide transistor of linear doping; Comprise P type substrate; Be provided with N-type trap and P type drift district at P type substrate; In the N-type trap, be provided with N-type contact hole and P type source; Being provided with the P type in P type drift district leaks; Above N-type trap and P type drift district, be provided with the grid oxide layer; Above being provided with above the grid oxide layer that polysilicon gate and polysilicon gate be positioned at that N-type trap and P type drift district has a common boundary; Above grid oxide layer and polysilicon gate, be provided with field oxide; Be connected with the aluminium lead-in wire in N-type contact hole and P type source

On polysilicon gate, be connected with aluminum lead, on leaking, the P type is connected with aluminum lead, in field oxide, be provided with the polysilicon field plate, this polysilicon field plate is connected with polysilicon gate, P type drift region by, second district, the 3rd district and the 4th district form, the direction that leak along P type source to the P type in these four districts is arranged in order, the border that above-mentioned first district starts from N type trap is the end of polysilicon gate finally, the end that second district starts from polysilicon gate is the end of polysilicon field plate finally, the end that is connected aluminum lead is leaked with the P type finally in the end that the 3rd district starts from the polysilicon field plate, the 4th district starts from the end that leaks the end P type leakage finally that is connected aluminum lead with the P type, the doping content in above-mentioned the 4th district is greater than the 3rd district, the doping content in the 3rd district is greater than second district, and the doping content in second district is greater than first district.

The method of the invention technical scheme is as follows:

A kind of preparation method who is used to make above-mentioned high-voltage P-type metal oxide transistor prepares P type substrate earlier, and concentration is 1 * 10 ¹⁵Cm ^-3About, again in P type substrate preparation P type drift region, four linear injections in district are distinguished in its drift, on the reticle of first to fourth drift region, offer ascending injection window successively, after ion injected, through thermal diffusion, impurity formed piecewise linearity and distributes in the drift region, after this, prepare field oxide, gate oxide, polysilicon gate, N type trap, P type source, leakage and P type substrate contact hole and contact hole and metallic aluminium lead-in wire again.

Compared with prior art, the present invention has following advantage:

(1) the present invention has introduced the drift region that piecewise linearity is mixed, this structure can reduce the peak value electric field at drift region, gate oxide below, polycrystalline grid field plate edge and drain terminal aluminium field plate edge, can improve puncture voltage greatly like this, puncture voltage can improve more than 30%; Because the drift region adopts piecewise linearity to mix, the drift region concentration of the concentration ratio routine of drift region will improve much like this, so conducting resistance can reduce greatly, approximately can reduce more than 40% simultaneously.

(2) because the drift region that the piecewise linearity that the present invention introduces is mixed can be based on realizing on the standard body silicon low pressure metal oxide semiconductor processing line, can not increase any processing step, be easy to be integrated in the power integrated circuit, so the present invention has low cost of manufacture, but advantages such as industrialization.

Description of drawings

Fig. 1 is a structure cutaway view of the present invention.

Fig. 2 is the linear schematic diagram that injects of drift region of the present invention subregion.

Embodiment 1

With reference to Fig. 1, a kind of high-voltage P-type metal oxide transistor of linear doping, comprise P type substrate 1, on P type substrate 1, be provided with N type trap 2 and P type drift region 3, in N type trap 2, be provided with N type contact hole 6 and P type source 5, in P type drift region 3, be provided with the P type and leak 4, above N type trap 2 and P type drift region 3, be provided with gate oxide 7, above being provided with above the gate oxide 7 that polysilicon gate 8 and polysilicon gate 8 be positioned at that N type trap 2 and P type drift region 3 have a common boundary, above gate oxide 7 and polysilicon gate 8, be provided with field oxide 10, on N type contact hole 6 and P type source 5, be connected with aluminum lead 11, on polysilicon gate 8, be connected with aluminum lead 12, in P type leakage 4, be connected with aluminum lead 13, in field oxide 10, be provided with polysilicon field plate 9, this polysilicon field plate 9 is connected with polysilicon gate 8, P type drift region 3 by, the second district N2, the 3rd district N3 and the 4th district N4 form, these four districts are arranged in order along the direction of P type source 5 to P types leakage 4, the border that the above-mentioned first district N1 starts from N type trap 2 is the end of polysilicon gate 8 finally, the end that the second district N2 starts from polysilicon gate 8 is the end of polysilicon field plate 9 finally, 4 ends that are connected aluminum lead 13 are leaked with the P type finally in the end that the 3rd district N3 starts from polysilicon field plate 9, the 4th district N4 starts from the end of the end P type leakage finally 4 that is connected aluminum lead 13 with P type leakage 4, the doping content of above-mentioned the 4th district N4 is greater than the 3rd district N3, the doping content of the 3rd district N3 is greater than the second district N2, and the doping content of the second district N2 is greater than the first district N1.

Embodiment 2

A kind of preparation method who is used to make above-mentioned high-voltage P-type metal oxide transistor prepares P type substrate earlier, and concentration is 1 * 10 ¹⁵Cm ^-3About, again in P type substrate preparation P type drift region, four linear injections in district are distinguished in its drift, on the reticle of first to fourth drift region, offer ascending injection window successively, after ion injected, through thermal diffusion, impurity formed piecewise linearity and distributes in the drift region, after this, prepare field oxide, gate oxide, polysilicon gate, N type trap, P type source, leakage and P type substrate contact hole and contact hole and metallic aluminium lead-in wire again.

With reference to Fig. 2, when P type substrate preparation P type drift region, four sections linear injections are distinguished in its drift, and each part is mixed according to following equation respectively.

$N_1\left(x\right)={\mathrm{M\α}}_{f1}x-\frac{{\mathrm{\ϵ}}_0{\mathrm{\ϵ}}_{\mathrm{ax}}}{{\mathrm{qt}}_1{t}_d}{V}_g$ 0≤x≤L ₁

$N_2\left(x\right)={\mathrm{M\α}}_{f2}x-\frac{{\mathrm{\ϵ}}_0{\mathrm{\ϵ}}_{\mathrm{ax}}}{{\mathrm{qt}}_2{t}_d}{V}_g$ L ₁≤x≤L ₂

N ₃(x)＝Mα _f3x L ₂≤x≤L ₃

$N_4\left(x\right)={\mathrm{M\α}}_{f4}x-\frac{{\mathrm{\ϵ}}_0{\mathrm{\ϵ}}_{\mathrm{ax}}}{{\mathrm{qt}}_3{t}_d}{V}_d$ L ₃≤x≤L ₄

Wherein $M=\frac{{\mathrm{\ϵ}}_0{\mathrm{\ϵ}}_{\mathrm{si}}}{q{L}_4}{V}_d$

${\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="1"\; label="f"\; filenames="C200610041322E00091.png"\; state="\{\{state\}\}">f</figure-callout>}1}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_1{t}_d}+\frac{2}{t_d(t_d+t_{s1})},$ ${\mathrm{\&beta;}}_{\mathrm{<figure-callout\; id="1"\; label="f"\; filenames="C200610041322E00091.png"\; state="\{\{state\}\}">f</figure-callout>}1}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_1{t}_d}{V}_g]$

${\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="2"\; label="f"\; filenames="C200610041322E00091.png"\; state="\{\{state\}\}">f</figure-callout>}2}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_2{t}_d}+\frac{2}{t_d(t_d+t_{s2})},$ ${\mathrm{\&beta;}}_{\mathrm{<figure-callout\; id="2"\; label="f"\; filenames="C200610041322E00091.png"\; state="\{\{state\}\}">f</figure-callout>}2}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_2{t}_d}{V}_g$

${\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="3"\; label="f"\; filenames="C200610041322E00091.png"\; state="\{\{state\}\}">f</figure-callout>}3}=\frac{2}{t_d(t_d+t_{s3})},$ ${\mathrm{\&beta;}}_{\mathrm{<figure-callout\; id="3"\; label="f"\; filenames="C200610041322E00091.png"\; state="\{\{state\}\}">f</figure-callout>}3}=-\left[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}\right]$

${\mathrm{\&alpha;}}_{f4}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_3{t}_d}+\frac{2}{t_d(t_d+t_{s4})},$ ${\mathrm{\&beta;}}_{f4}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_3{t}_d}{V}_d]$

L ₁, L ₂, L ₃And L ₄Be respectively N1, N2, the right margin position in N3 and N4 zone.t _1s, t _2s, t _3sAnd t _4sBe respectively L ₁, L ₂, L ₃And L ₄The depletion width in zone.t ₁Be the thickness of gate oxide, t ₂And t ₃Thickness for each self-corresponding oxygen layer under polycrystalline grid field plate and the drain terminal aluminium field plate.ε _OxAnd ε _SiBe respectively the relative dielectric constant of silicon dioxide and silicon.V _gBe the gate voltage of device, V _dBe the required puncture voltage of device.t _dBe the junction depth of P type drift region, N _d(x) be initial impurity concentration.

In prepared, can on the reticle of drift region, offer the injection window 14 (with reference to Fig. 2) of different sizes according to above formula, the impurity dose that is injected into the surface, drift region like this is just different, and through after the thermal diffusion, impurity just can form piecewise linearity and distribute in the drift region.

Claims (2)

1, a kind of high-pressure N-type metal oxide semiconductor tube of linear doping, comprise N type substrate (1), on N type substrate (1), be provided with P type trap (2) and N type drift region (3), in P type trap (2), be provided with P type contact hole (6) and N type source (5), in N type drift region (3), be provided with the N type and leak (4), top in P type trap (2) and N type drift region (3) is provided with gate oxide (7), be provided with the top that polysilicon gate (8) and polysilicon gate (8) are positioned at P type trap (2) and boundary, N type drift region (3) in gate oxide (7) top, top at gate oxide (7) and polysilicon gate (8) is provided with field oxide (10), on P type contact hole (6) and N type source (5), be connected with aluminum lead (11), on polysilicon gate (8), be connected with aluminum lead (12), in N type leakage (4), be connected with aluminum lead (13), in field oxide (10), be provided with polysilicon field plate (9), this polysilicon field plate (9) is connected with polysilicon gate (8), it is characterized in that N type drift region (3) is by the first district N1, the second district N2, the 3rd district N3 and the 4th district N4 form, (4) are leaked in these four districts along N type source (5) to the N type direction is arranged in order from left to right, the right margin that the above-mentioned first district N1 starts from P type trap (2) is the right part of polysilicon gate (8) finally, the right part that the second district N2 starts from polysilicon gate (8) is the right part of polysilicon field plate (9) finally, the left-end point that (4) are connected aluminum lead (13) is leaked with the N type finally in the right part that the 3rd district N3 starts from polysilicon field plate (9), the 4th district N4 starts from the N type and leaks the right end that (4) are connected the left-end point N type leakage (4) finally of aluminum lead (13), the doping content of above-mentioned the 4th district N4 is greater than the 3rd district N3, the doping content of the 3rd district N3 is greater than the second district N2, the doping content of the second district N2 is greater than the first district N1, the described first district N1, the second district N2, the doping content of the 3rd district N3 and the 4th district N4 is respectively:

$\begin{array}{cc}N1\left(x\right)={\mathrm{M\&alpha;}}_{f1}x-\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{qt}}_1{t}_d}{V}_g& 0\&le;x<L_1\end{array}$

$\begin{array}{cc}N2\left(x\right)={\mathrm{M\&alpha;}}_{f2}x-\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{qt}}_2{t}_d}{V}_g& L_1\&le;x\&le;L_2\end{array}$

N3(x)＝Mα _f3x L ₂<x<L ₃

$\begin{array}{cc}N4\left(x\right)={\mathrm{M\&alpha;}}_{f4}x-\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{qt}}_3{t}_d}{V}_d& L_3\&le;x\&le;L_4\end{array}$

Wherein $M=\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}{{\mathrm{qL}}_4}{V}_d$

${\mathrm{\&alpha;}}_{f1}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_1{t}_d}+\frac{2}{t_d(t_d+t_{s1})},$ ${\mathrm{\&beta;}}_{f1}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_1{t}_d}{V}_g]$

${\mathrm{\&alpha;}}_{f2}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_2{t}_d}+\frac{2}{t_d(t_d+t_{s2})},$ ${\mathrm{\&beta;}}_{f2}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_2{t}_d}{V}_g]$

${\mathrm{\&alpha;}}_{f3}=\frac{2}{t_d(t_d+t_{s3})},$ ${\mathrm{\&beta;}}_{f3}=-\left[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}\right]$

${\mathrm{\&alpha;}}_{f4}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_3{t}_d}+\frac{2}{t_d(t_d+t_{s4})},$ ${\mathrm{\&beta;}}_{f4}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_3{t}_d}{V}_d]$

L ₁, L ₂, L ₃And L ₄Be respectively N1, N2, the right margin position in N3 and N4 zone, t _S1, t _S2, t _S3And t _S4Be respectively L ₁, L ₂, L ₃And L ₄The depletion width in zone, t ₁Be the thickness of gate oxide, t ₂And t ₃Be the thickness of each self-corresponding oxygen layer under polycrystalline grid field plate and the drain terminal aluminium field plate, ε _OxAnd ε _SiBe respectively the relative dielectric constant of silicon dioxide and silicon, V _gBe the gate voltage of device, V _dBe the required puncture voltage of device, t _dBe the junction depth of N type drift region, N _d(x) be initial impurity concentration.

2, a kind of preparation method who is used to make the described high-pressure N-type metal oxide semiconductor tube of claim 1 is characterized in that preparation N type substrate earlier, and concentration is 1 * 10 ¹⁵Cm ^-3About, again in N type substrate preparation N type drift region, four linear injections in district are distinguished in its drift, on the reticle in first to fourth district, offer ascending injection window successively, after ion injects, through thermal diffusion, impurity forms piecewise linearity and distributes in the drift region, after this, prepare field oxide, gate oxide, polysilicon gate, P type trap, N type source, leakage and N type substrate contact hole and P type contact hole and metallic aluminium lead-in wire again, described four districts carry out linear doping by following formula respectively:

$\begin{array}{cc}N1\left(x\right)={\mathrm{M\&alpha;}}_{f1}x-\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{qt}}_1{t}_d}{V}_g& 0\&le;x<L_1\end{array}$

$\begin{array}{cc}N2\left(x\right)={\mathrm{M\&alpha;}}_{f2}x-\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{qt}}_2{t}_d}{V}_g& L_1\&le;x\&le;L_2\end{array}$

N3(x)＝Mα _f3x L ₂<x<L ₃

$\begin{array}{cc}N4\left(x\right)={\mathrm{M\&alpha;}}_{f4}x-\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{qt}}_3{t}_d}{V}_d& L_3\&le;x\&le;L_4\end{array}$

Wherein $M=\frac{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}{{\mathrm{qL}}_4}{V}_d$

${\mathrm{\&alpha;}}_{f1}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_1{t}_d}+\frac{2}{t_d(t_d+t_{s1})},$ ${\mathrm{\&beta;}}_{f1}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_1{t}_d}{V}_g]$

${\mathrm{\&alpha;}}_{f2}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_2{t}_d}+\frac{2}{t_d(t_d+t_{s2})},$ ${\mathrm{\&beta;}}_{f2}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_2{t}_d}{V}_g]$

${\mathrm{\&alpha;}}_{f3}=\frac{2}{t_d(t_d+t_{s3})},$ ${\mathrm{\&beta;}}_{f3}=-\left[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}\right]$

${\mathrm{\&alpha;}}_{f4}=\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_3{t}_d}+\frac{2}{t_d(t_d+t_{s4})},$ ${\mathrm{\&beta;}}_{f4}=-[\frac{{\mathrm{qN}}_d\left(x\right)}{{\mathrm{\&epsiv;}}_0{\mathrm{\&epsiv;}}_{\mathrm{si}}}+\frac{{\mathrm{\&epsiv;}}_{\mathrm{ox}}}{{\mathrm{\&epsiv;}}_{\mathrm{si}}{t}_3{t}_d}{V}_d]$

L ₁, L ₂, L ₃And L ₄Be respectively N1, N2, the right margin position in N3 and N4 zone, t _S1, t _S2, t _S3And t _S4Be respectively L ₁, L ₂, L ₃And L ₄The depletion width in zone, t ₁Be the thickness of gate oxide, t ₂And t ₃Be the thickness of each self-corresponding oxygen layer under polycrystalline grid field plate and the drain terminal aluminium field plate, ε _AxAnd ε _SiBe respectively the relative dielectric constant of silicon dioxide and silicon, V _gBe the gate voltage of device, V _dBe the required puncture voltage of device, t _dBe the junction depth of N type drift region, N _d(x) be initial impurity concentration.

Images