CN201422095Y - PWM complementary output unit circuit capable of increasing dead time at will - Google Patents
PWM complementary output unit circuit capable of increasing dead time at will Download PDFInfo
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- CN201422095Y CN201422095Y CN2009200567632U CN200920056763U CN201422095Y CN 201422095 Y CN201422095 Y CN 201422095Y CN 2009200567632 U CN2009200567632 U CN 2009200567632U CN 200920056763 U CN200920056763 U CN 200920056763U CN 201422095 Y CN201422095 Y CN 201422095Y
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- pwm
- stage trigger
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Abstract
The utility model provides a PWM complementary output circuit capable of increasing dead time, which comprises a forward stage trigger U1A, a backward stage trigger U1B, two AND gate units U3A, U3B and a NOT gate unit U2A. The PWM signal output end is connected with a pin D of the forward stage trigger U1A, the dead zone signal output end is connected with a pin CLK of the forward stage trigger U1A, other two control pins of the forward stage trigger U1A are grounded, one output end Q1 of the forward stage trigger U1A is connected with the pin D of the backward stage trigger U1B, the dead zonesignal output end is connected with the pin CLK of the backward stage trigger U1B after being connected with the NOT gate unit U2A, and other two control pins of the backward stage trigger U1B are grounded. The input end of the AND gate unit U3A is connected with Q1 and Q2, the output end of the AND gate unit U3A outputs a path of complementary signals, one input end of the AND gate unit U3B is connected with * and *, and the output end of the AND gate unit U3A outputs another path of complementary signals. The PWM complementary output unit circuit has the characteristics of simple structure,low manufacturing cost and reliable as well as stable working; moreover, the dead time can be adjusted at will, so that the PWM complementary output unit circuit is practical and convenient.
Description
Technical field:
The utility model relates to a kind of PWM complementary output element circuit of any increase Dead Time.
Background technology:
At present, the control mode of dc brushless motor is to realize the change of current and the variable frequency control of phase line current by pwm signal control H bridge, thus the running of the rotor of drive motors.Fig. 1 is a kind of fundamental diagram of three-phase direct-current brushless motor, when adopting complementary PWM mode to drive half-bridge, for two switching tube conductings simultaneously (for example T1, T2 conducting simultaneously) about preventing half-bridge are short-circuited, burn controller, need to increase Dead Time, guarantee switch transistor T 1 another switch transistor T 2 ability conductings behind certain hour, vice versa.So just require to control same half-bridge up and down the two-way pwm control signal of two switching tubes must complementation and increases certain Dead Time.The PWM complementary output function of band Dead Time needs to adopt the microprocessor of high-grade performance just can realize, will increase manufacturing cost like this.Be restricted for a large amount of meetings of practical application cheaply.
The utility model content:
The purpose of this utility model is the PWM complementary output element circuit that a kind of any increase Dead Time is provided for the microprocessor of many low-cost low performances, and its circuit structure is simple, low cost of manufacture, and Dead Time can be provided with arbitrarily.
The utility model is to finish by following technical scheme: a kind of PWM complementary output element circuit of any increase Dead Time, it comprises prime D flip-flop U1A, back level D flip-flop U1B, two and gate cell U3A, U3B and a non-gate cell U2A, wherein: the pwm signal output connects the D pin of prime D flip-flop U1A, and the dead band signal output part connects the CLK pin of prime D flip-flop U1A; The output Q1 of prime D flip-flop U1A connects the D pin of back level D flip-flop U1B, and the dead band signal output part is connected with the CLK pin of back level D flip-flop U1B after connecting a non-gate cell U2A; An output Q1 who is connected prime D flip-flop U1A with the input of gate cell U3A, another input connect the output Q2 of back level D flip-flop U1B, export one road complementary signal with the output of gate cell U3A; An output Q1 who is connected prime D flip-flop U1A with the input of gate cell U3B, another input connect the output Q2 of back level D flip-flop U1B, export another road complementary signal with the output of gate cell U3A.
Above-mentioned described pwm signal is to be provided by single-chip microprocessor MCU or digital signal processor DSP.
Above-mentioned described dead band signal is to be provided by single-chip microprocessor MCU or digital signal processor DSP, also can be provided by oscillating circuit.
Compared with prior art, the utlity model has advantage has: circuit structure is simple, low cost of manufacture, and working stability is reliable, and Dead Time can arbitrarily be provided with, and is convenient and practical.
Description of drawings:
Below in conjunction with accompanying drawing the utility model is done detailed explanation:
Fig. 1 is the control principle figure of dc brushless motor;
Fig. 2 is circuit theory diagrams of the present utility model;
Fig. 3 is the sequential chart of each point signal among Fig. 2.
Embodiment:
As shown in Figure 1 and Figure 2, a kind of PWM complementary output circuit that increases Dead Time, it comprises prime D flip-flop U1A, back level D flip-flop U1B, two and gate cell U3A, U3B and a non-gate cell U2A, wherein: the pwm signal output connects the D pin of prime D flip-flop U1A, the dead band signal output part connects the CLK pin of prime D flip-flop U1A, all the other two control pin PRE of prime D flip-flop U1A, CLR ground connection; The output Q1 of prime D flip-flop U1A connects the D pin of back level D flip-flop U1B, the dead band signal output part is connected all the other two control pin PRE, the CLR ground connection of back level D flip-flop U1B with the CLK pin of back level D flip-flop U1B after connecting a non-gate cell U2A; An output Q1 who is connected prime D flip-flop U1A with the input of gate cell U3A, another input connect the output Q2 of back level D flip-flop U1B, export one road complementary signal H with the output of gate cell U3A; An output Q1 who is connected prime D flip-flop U1A with the input of gate cell U3B, another input connects the output Q2 of back level D flip-flop U1B, export another road complementary signal I with the output of gate cell U3A, complementary signal I, H control half-bridge switch.PWM-U is the PWM input signal, is provided by single-chip microprocessor MCU or digital signal processor DSP.D-TIME is that the dead band signal is to be provided by single-chip microprocessor MCU or digital signal processor DSP, also can be provided by oscillating circuit.The clock signal of each point A, the B among Fig. 2, C, D, E, F, G, H, I output as shown in Figure 3, H, I point is to have the pwm signal that complementary output has Dead Time deadtime.By changing the dead band signal increase Dead Time that A is ordered.Circuit structure is simple, and cost is low.
The utility model is applied on the controller of three-phase direct-current brushless motor, adopts three groups of identical circuit as shown in Figure 2, controls three half-bridge switch pipes, can export 6 road pwm signals.
The foregoing description is a better embodiment of the present utility model; but execution mode of the present utility model is not limited thereto; other are any not to deviate from change, the modification done under spirit of the present utility model and the principle, substitute, combination, simplify; be the substitute mode of equivalence, be included within the protection range of the present utility model.
Claims (3)
1. PWM complementary output element circuit that increases arbitrarily Dead Time is characterized in that: it comprise prime D flip-flop U1A, back level D flip-flop U1B, two with gate cell U3A, U3B and a non-gate cell U2A, wherein:
The pwm signal output connects the D pin of prime D flip-flop U1A, and the dead band signal output part connects the CLK pin of prime D flip-flop U1A;
The output Q1 of prime D flip-flop U1A connects the D pin of back level D flip-flop U1B, and the dead band signal output part is connected with the CLK pin of back level D flip-flop U1B after connecting a non-gate cell U2A;
An output Q1 who is connected prime D flip-flop U1A with the input of gate cell U3A, another input connect the output Q2 of back level D flip-flop U1B, export one road complementary signal with the output of gate cell U3A;
An output Q1 who is connected prime D flip-flop U1A with the input of gate cell U3B, another input connect the output Q2 of back level D flip-flop U1B, export another road complementary signal with the output of gate cell U3A.
2, the PWM complementary output element circuit of a kind of any increase Dead Time according to claim 1, it is characterized in that: pwm signal is to be provided by single-chip microprocessor MCU or digital signal processor DSP.
3, the PWM complementary output element circuit of a kind of any increase Dead Time according to claim 1 and 2, it is characterized in that: the dead band signal is to be provided by single-chip microprocessor MCU or digital signal processor DSP, also can be provided by oscillating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200567632U CN201422095Y (en) | 2009-05-11 | 2009-05-11 | PWM complementary output unit circuit capable of increasing dead time at will |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009200567632U CN201422095Y (en) | 2009-05-11 | 2009-05-11 | PWM complementary output unit circuit capable of increasing dead time at will |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201422095Y true CN201422095Y (en) | 2010-03-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009200567632U Expired - Lifetime CN201422095Y (en) | 2009-05-11 | 2009-05-11 | PWM complementary output unit circuit capable of increasing dead time at will |
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| CN (1) | CN201422095Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075177A (en) * | 2010-12-24 | 2011-05-25 | 苏州华芯微电子股份有限公司 | Method for producing non-overlapping signal with reasonable dead-zone time |
-
2009
- 2009-05-11 CN CN2009200567632U patent/CN201422095Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075177A (en) * | 2010-12-24 | 2011-05-25 | 苏州华芯微电子股份有限公司 | Method for producing non-overlapping signal with reasonable dead-zone time |
| CN102075177B (en) * | 2010-12-24 | 2012-12-12 | 苏州华芯微电子股份有限公司 | Method for producing non-overlapping signal with reasonable dead-zone time |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100310 |