CN103051331B - A kind of phase lock circuitry for ultrasonic power - Google Patents
A kind of phase lock circuitry for ultrasonic power Download PDFInfo
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- CN103051331B CN103051331B CN201210541902.7A CN201210541902A CN103051331B CN 103051331 B CN103051331 B CN 103051331B CN 201210541902 A CN201210541902 A CN 201210541902A CN 103051331 B CN103051331 B CN 103051331B
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Abstract
The present invention relates to a kind of phase lock circuitry for ultrasonic power, comprise the first comparator and the second comparator, comparator exports the electric current and voltage synchronous square-wave signal produced and is linked into first to fourth monostable flipflop, and XOR gate and the second d type flip flop and the 3rd D trigger.The output of first to fourth monostable flipflop and XOR gate accesses second, third d type flip flop, the two pulse signals that second, third d type flip flop exports is respectively through identical first, second RC filter circuit of parameter, be input in the 3rd comparator, the output of the 3rd comparator can determine that frequency increases the direction reduced.Phase lock circuitry disclosed by the invention may be used for the different voltage of duty ratio, current synchronization square-wave signal, reaches the object that frequency of phase locking is followed the tracks of.
Description
Technical field
The present invention relates to a kind of phase lock circuitry for ultrasonic power.
Background technology
Ultrasonic power is commonly referred to ultrasonic wave generating source, and its effect is that electric energy is converted to the high-frequency ac signal of telecommunication matched with ultrasonic transducer.Ultrasonic power generally must have frequency-tracking system, when transducer is operated in resonant frequency point, it is most effective, work the most stable, and the resonant frequency point of transducer can due to assembling reason and the aging rear change of work, be called resonance frequency point drift, the effect of frequency-tracking system is exactly the resonance frequency allowing the AC signal exported always work in transducer, makes transducer operating efficiency the highest.
At present, the frequency-tracking system of ultrasonic power often adopts frequency of phase locking to follow the tracks of, and traditional frequency of phase locking tracking, be applicable to output voltage, situation that current synchronous signal duty ratio is equal, and when output voltage is different from the duty ratio of current synchronous signal, the PS-PWM control method of output voltage is such as controlled by changing phase shifting angle, the duty ratio of its output voltage, current synchronous signal is unequal, if still use traditional frequency of phase locking tracking, then can not reach the object of output voltage current in phase.
Summary of the invention
The object of the invention is the deficiency overcoming prior art existence, discloses a kind of phase lock circuitry for ultrasonic power.The present invention discloses a kind of phase lock circuitry for ultrasonic power, be applicable to output voltage, current synchronization square-wave signal duty ratio not etc. when realize the effect that frequency of phase locking follows the tracks of.Described ultrasonic power phase lock circuitry is in the moment of varying level by sampling and outputting voltage, current synchronization square-wave signal, and is represented by the form of pulse.Equal by the two pulse signals pulsewidth controlling the output of d type flip flop link, reach the object that frequency phase lock is followed the tracks of.
Object of the present invention can realize by the following technical solutions:
A kind of phase lock circuitry for ultrasonic power, it comprises two comparators, XOR gate, four monostable flipflops, three d type flip flops and two RC filter circuits, wherein, the output of the first comparator accesses the second monostable flipflop and the 3rd monostable flipflop, the output of the second comparator accesses the first monostable flipflop and the 4th monostable flipflop, first comparator is also connected with the input of XOR gate and the first d type flip flop with the output of the second comparator, the output of first to fourth monostable flipflop and XOR gate accesses the second d type flip flop and 3d flip-flop, second d type flip flop, the two pulse signals that 3d flip-flop exports is respective through a RC filter circuit respectively, finally be input in the 3rd comparator.
Further optimization, the positive input terminal pin of the first comparator and the positive input terminal pin of the second comparator connect voltage, current sampling signal respectively, the negative input end pin of the first comparator and negative input end pin all ground connection of the second comparator; The first input end pin of the output pin access XOR gate of the first comparator, the second input pin of the output pin access XOR gate of the second comparator.The first output pin compared accesses the clock end pin of the first d type flip flop, and the output pin of the second comparator connects the D input port pin of the first d type flip flop.
Further optimization, the non-output of Q of the first d type flip flop is unsettled, the output pin of the first comparator connects the trailing edge pin of the second monostable flipflop rising edge pin and the 3rd monostable flipflop respectively, the output pin of the second comparator connects rising edge pin and the 4th monostable flipflop trailing edge pin of the first monostable flipflop respectively, and the Q output pin of the first monostable flipflop and the Q output pin of the second monostable flipflop are linked into the clock port pin of the second d type flip flop respectively through a diode; The Q output pin of the 3rd monostable flipflop and the Q output pin of the 4th monostable flipflop are input to the clock end pin of 3d flip-flop respectively through a diode; The trailing edge input end grounding of the first monostable flipflop and the second monostable flipflop, the rising edge input end grounding of the 3rd monostable flipflop and the 4th monostable flipflop; The non-output of Q of first to fourth monostable flipflop is unsettled; The output of XOR gate accesses the D input pin of the second d type flip flop and the D input pin pin of 3d flip-flop respectively; The output of the second d type flip flop and 3d flip-flop is input to negative input end pin and the positive input terminal pin of the 3rd comparator respectively through first, second RC filter circuit that parameter is identical; The non-output of Q of second, third d type flip flop is unsettled.
Further optimization, in two RC filter circuits, a RC filter circuit is made up of the first resistance and the first electric capacity, and the 2nd RC filter circuit is made up of the second resistance and the second electric capacity.
Further optimization, a RC filter circuit is identical with the 2nd RC filter circuit parameter.
Further optimization, the Q output of first to fourth monostable flipflop accesses the clock end of second, third d type flip flop respectively through a diode.
Further optimization, equal by the two pulse signals pulsewidth controlling the output of second, third d type flip flop, make output voltage, current in phase position.
Compared with the prior art the present invention has the following advantages:
Ultrasonic power phase lock circuitry proposed by the invention is different from traditional phase lock circuitry, traditional phase lock circuitry, is first rising edge synch making output voltage, current synchronization square-wave signal, thus reaches the effect of voltage, current in phase position.This method is only applicable to the equal situation of duty ratio of voltage, current synchronization square-wave signal.If when voltage, current synchronization square-wave signal duty ratio are different, this method will encounter problems.
Ultrasonic power phase lock circuitry proposed by the invention be applicable to when output voltage, current synchronization square-wave signal duty ratio not etc. when.In one-period, voltage, current sampling signal, two-way output pulse signal can be obtained respectively through first, second comparator in described phase lock circuitry, XOR gate, first to fourth monostable flipflop and second, third d type flip flop, as long as the pulsewidth controlling this two pulse signals is equal, the duty ratio anisochrouous frequency of phase locking tracking effect of output voltage, current synchronization square-wave signal just can be realized.
Accompanying drawing explanation
Fig. 1 is the structural representation of described phase lock circuitry.
Fig. 2 is the structural representation of traditional phase lock circuitry.
Fig. 3 is the output waveform of XOR gate XOR1 and the Q output output waveform of second, third d type flip flop.
Fig. 4 is the output voltage current synchronization square-wave waveform that described phase lock circuitry is applied to ultrasonic power.
Fig. 5 is that described phase lock circuitry is applied to ultrasonic power, the sample waveform of its output voltage, electric current.
Fig. 6 is that traditional locks circuitry phase is applied to ultrasonic power, the asynchronous synchronous square-wave waveform of its output voltage current synchronization duty cycle square wave and output voltage, current waveform.
Embodiment
Below in conjunction with accompanying drawing, enforcement of the present invention is further described in detail, but enforcement of the present invention and protection range are not limited thereto.
When the synchronous square-wave signal that phase lock circuitry disclosed by the invention is mainly used in output voltage electric current has different duty.As shown in Figure 1, voltage sampling signal and current sampling signal, respectively through the first comparator COMP1 and the second comparator COMP2, obtain the square-wave signal synchronous with electric current and voltage.First, synchronizing signal be input in XOR gate XOR1, when electric current and voltage synchronizing signal is in varying level, goalkeeper XOR1 exports high level, can obtain a series of pulse signal like this, is in the moment of varying level corresponding to electric current and voltage synchronizing signal.Then the output signal of XOR1 door is accessed the D input of the second d type flip flop DFF2 and 3d flip-flop DFF3, then by the synchronizing signal of electric current and voltage, by the mode of connection in figure, access the first ~ four monostable flipflop (MONO5, MONO6, MONO7, MONO8), the Q output of the first ~ four monostable flipflop is accessed the clock end of the second d type flip flop DFF2 and 3d flip-flop DFF3 by the mode of connection in figure, the one tunnel pulse that XOR gate XOR1 can be exported like this, be divided into corresponding to output current, the two pulse signals of voltage signal geometric center point, as in Fig. 3, XOR gate output signal V11, by second, after 3d flip-flop link, V43 can be obtained, the pulse signal that the two-way of V44 is discrete.As long as the pulsewidth of control V43 and V44 two pulse signals is equal, the effect of electric current and voltage Phase-Locked Synchronous just can be obtained.So by this two pulse signals, by first, second RC filter circuit that parameter is equal, as shown in Figure 1, can obtain the d. c. voltage signal be directly proportional to pulsewidth, the equal and opposite in direction controlling two voltage signals just can obtain the equal effect of pulsewidth.As in Fig. 4, V8, V9 are the synchronous square-wave signals of electric current and voltage, and can find out, its geometric center point is still more synchronous.Shown in Fig. 5, the sampled signal of electric current and voltage, VP7 is voltage sampling signal, and V7 is current sampling signal, in order to clearly comparative voltage current signal, through amplifying during the current signal of V7.Can find out, phase-locked or reasonable.
This circuit components annexation is as shown in Figure 1: voltage, current sampling signal access the negative input end pin 4 of the positive input terminal pin 3 of the first comparator COMP1 and positive input terminal pin 1, the first comparator COMP1 of the second comparator COMP2 and negative input end pin 2 all ground connection of the second comparator COMP2 respectively.The output pin 5 that the output pin 6 of the first comparator COMP1 accesses first input end pin 8, the second comparator COMP2 of XOR gate XOR1 accesses the second input pin 7 of XOR gate XOR1.The output pin 5 that the output pin 6 of the first comparator COMP1 accesses clock end pin 9, the second comparator COMP2 of the first d type flip flop DFF1 connects the D input port pin 10 of the first d type flip flop DFF1.The non-output of Q of the first d type flip flop is unsettled.The output pin 6 of the first comparator COMP1 connects the trailing edge pin 13 of the second monostable flipflop MONO6 rising edge pin 12 and the 3rd monostable flipflop MONO7 respectively.The output pin 5 of the second comparator COMP2 connects rising edge pin 11 and the 4th monostable flipflop MONO8 trailing edge pin 14 of the first monostable flipflop MONO5 respectively.The Q output pin 15 of the first monostable flipflop MONO5 and the Q output pin 16 of the second monostable flipflop MONO6 are linked into the clock port pin 20 of the second d type flip flop DFF2 respectively through a diode.The Q output pin 17 of the 3rd monostable flipflop MONO7 and the Q output pin 18 of the 4th monostable flipflop MONO8 are input to the clock end pin 22 of 3d flip-flop DFF3 respectively through a diode.The trailing edge input end grounding of the first monostable flipflop MONO5 and the second monostable flipflop MONO6, the rising edge input end grounding of the 3rd monostable flipflop MONO7 and the 4th monostable flipflop MONO8.The non-output of Q of first to fourth monostable flipflop is unsettled.The output of XOR gate XOR1 accesses the D input pin 19 of the second d type flip flop DFF2 and the D input pin pin 21 of 3d flip-flop DFF3 respectively.Second d type flip flop DFF2 exports with the Q of 3d flip-flop DFF3 the negative input end pin 26 and the positive input terminal pin 25 that are input to the 3rd comparator COMP11 respectively through first, second RC filter circuit that parameter is identical.The non-output of Q of second, third d type flip flop is unsettled.In two RC filter circuits, a RC filter circuit is made up of the first resistance R34 and the first electric capacity C34, and the 2nd RC filter circuit is made up of the second resistance R35 and the second electric capacity C35.
As shown in Figure 2, voltage sampling signal and current sampling signal, respectively by comparator the 4th comparator C1 and the 5th comparator C2, produce the square-wave signal synchronous with voltage, current signal to traditional phase lock circuitry.What C1 exported access the clock end of d type flip flop with the square-wave signal of voltage synchronous, and the voltage signal that C2 exports accesses the D input of d type flip flop.When voltage signal and current signal out of phase, XOR gate can export the pulse signal with the equal pulsewidth of difference.The output level of the d type flip flop Q output that traditional locks circuitry phase obtains, increases for determining or reduces frequency, by the size of XOR gate XOR output pulse width, for determining the speed of frequency shift, to reach the object of transducer resonance.It just according to the rising edge synch of the synchronizing signal of current/voltage, reaches the object that current and voltage signals is synchronous.If the unequal words of the pulsewidth of electric current and voltage synchronizing signal, synchronizing signal rising edge synch, can not reach electric current and voltage with phase effect, particularly when PS-PWM control method.
PS-PWM regulate and control method is the effective value being changed output voltage by the phase shifting angle of change phase-shifting full-bridge, thus reaches the object of pressure regulation.Therefore, the bridge arm voltage output regulated and controled by PS-PWM mode is not the square-wave signal of standard, but the square wave output that duty ratio is adjustable.And brachium pontis signal puts on transducer system, its resonance current is sinusoidal signal, therefore the synchronizing signal of sinusoidal current to be duty ratio be 0.5 standard block signal.If use traditional phase lock circuitry, the object of electric current and voltage homophase can not be reached.
If adopt traditional control method, make first rising edge synch of first voltage, current signal, its output voltage electric current as shown in Figure 6, so traditional control method cannot make the output voltage current in phase position of PS-PWM control method.Wherein, VP1, V7 are the sample waveform of output voltage and output current respectively, and V8, V9 are the synchronous square-wave waveform of electric current, voltage respectively.
Claims (5)
1. the phase lock circuitry for ultrasonic power, it is characterized in that comprising two comparators, XOR gate, four monostable flipflops, three d type flip flops and two RC filter circuits, wherein, the output of the first comparator (COMP1) accesses the second monostable flipflop and the 3rd monostable flipflop, the output of the second comparator (COMP2) accesses the first monostable flipflop and the 4th monostable flipflop, first comparator is also connected with the input of XOR gate and the first d type flip flop (DFF1) with the output of the second comparator, the output of first to fourth monostable flipflop and XOR gate accesses the second d type flip flop (DFF2) and 3d flip-flop (DFF3), second d type flip flop, the two pulse signals that 3d flip-flop exports is respective through a RC filter circuit respectively, finally be input in the 3rd comparator (COMP11), the positive input terminal pin of the first comparator and the positive input terminal pin of the second comparator connect voltage, current sampling signal respectively, the negative input end pin of the first comparator and negative input end pin all ground connection of the second comparator, the first input end pin of the output pin access XOR gate of the first comparator, the second input pin of the output pin access XOR gate of the second comparator,
The first output pin compared accesses the clock end pin of the first d type flip flop, and the output pin of the second comparator connects the D input port pin of the first d type flip flop; The non-output of Q of the first d type flip flop is unsettled, the output pin of the first comparator connects the trailing edge pin of the second monostable flipflop rising edge pin and the 3rd monostable flipflop respectively, the output pin of the second comparator connects rising edge pin and the 4th monostable flipflop trailing edge pin of the first monostable flipflop respectively, and the Q output pin of the first monostable flipflop and the Q output pin of the second monostable flipflop are linked into the clock port pin of the second d type flip flop respectively through a diode; The Q output pin of the 3rd monostable flipflop and the Q output pin of the 4th monostable flipflop are input to the clock end pin of 3d flip-flop respectively through a diode; The trailing edge input end grounding of the first monostable flipflop and the second monostable flipflop, the rising edge input end grounding of the 3rd monostable flipflop and the 4th monostable flipflop; The non-output of Q of first to fourth monostable flipflop is unsettled; The output of XOR gate accesses the D input pin of the second d type flip flop and the D input pin pin of 3d flip-flop respectively; The output of the second d type flip flop and 3d flip-flop is input to negative input end pin and the positive input terminal pin of the 3rd comparator respectively through first, second RC filter circuit that parameter is identical; The non-output of Q of second, third d type flip flop is unsettled.
2. a kind of phase lock circuitry for ultrasonic power according to claim 1, it is characterized in that, in two RC filter circuits, a RC filter circuit is made up of the first resistance and the first electric capacity, the 2nd RC filter circuit is made up of the second resistance and the second electric capacity.
3. a kind of phase lock circuitry for ultrasonic power according to claim 1, is characterized in that a RC filter circuit is identical with the 2nd RC filter circuit parameter.
4. a kind of phase lock circuitry for ultrasonic power according to claim 1, is characterized in that the Q output of first to fourth monostable flipflop accesses the clock end of second, third d type flip flop respectively through a diode.
5. a kind of phase lock circuitry for ultrasonic power according to claim 1, is characterized in that the two pulse signals pulsewidth by controlling the output of second, third d type flip flop is equal, making output voltage, current in phase position.
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