CN103401218B - A kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof - Google Patents
A kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof Download PDFInfo
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Abstract
The invention discloses a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD, comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit thereof.Described dsp controller produces with Dead Time and the between two complementary pwm signal in 4 tunnels; The output of 4 road pwm signals, current sample and comparison circuit thereof that 5 I/O mouths of described CPLD programmable logic device export with dsp controller is respectively connected, and exports 4 tunnels by 4 I/O mouths and have overcurrent protection and with Dead Time and pwm signal complementary between two.Cycle self-protection circuit of the present invention is simple and practical, realizes over current fault protection, save design cost with minimum pwm signal, eliminates the transformer bias phenomenon because continuous fault protection produces simultaneously.
Description
Technical field
The present invention relates to phase-shifting full-bridge switch power technology field, be specifically related to a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof.
Background technology
Phase whole-bridging circuit, as the soft switch circuit of a comparative maturity, is usually used in middle large power, electrically source circuit.Full-bridge circuit commonly uses IGBT as switching tube, and when occurring over current fault, the time general no more than 10us of the instantaneous overcurrent that IGBT can bear, if certainly will burn IGBT by means of only dsp controller process over current fault.Drive the four road PWM of IGBT generally to be produced by dsp controller, the 4 road pwm signals exported due to dsp controller are complementary between two, so when there is over current fault, IGBT cannot be made simultaneously all to turn off, cannot meet real work requirement simultaneously.Moreover conventional overcurrent period protection circuit working at continuous over current fault time can cause voltage bias phenomenon, affect device lifetime.
Summary of the invention
For the deficiency that prior art exists; the present invention discloses a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof; when there is over current fault; the complete shut-down that can realize switching tube with minimum pwm signal breaks and eliminates the bias phenomenon that transformer produces when there is continuous over current fault; improve dsp controller utilance; cost-saving, this control method is reliable, circuit simple, be easy to realization.
The present invention is for achieving the above object, and the technical scheme adopted is as follows:
Based on a phase-shifting full-bridge overcurrent self-protection circuit of CPLD, comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit thereof; Described dsp controller produces with Dead Time and the between two complementary pwm signal in 4 tunnels: the first input pwm signal, the second input pwm signal, the 3rd input pwm signal, the 4th input pwm signal; The output of 4 road pwm signals, current sample and comparison circuit thereof that 5 I/O mouths of described CPLD programmable logic device export with dsp controller is respectively connected, and exports 4 tunnels by its 4 I/O mouths and have overcurrent protection and with Dead Time and pwm signal complementary between two: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal.
The first described input pwm signal, the second input pwm signal, the 3rd input pwm signal (PWM3), the 4th input pwm signal form 4 road phase-shifting full-bridge pwm signals, wherein the second input pwm signal is oppositely obtained by the first input pwm signal, and the 4th input pwm signal is oppositely obtained by the 3rd input pwm signal (PWM3).
As preferably, described dsp processor selects Texas Instruments 2000 series DSP controller.
As preferably, described CPLD Programmable Logic Controller selects the MAX7000 series CPLD Programmable Logic Controller of altera corp.
Described current sample and comparison circuit thereof, comprising: Hall current sensor P, 16 resistance R
1-R
16, 7 electric capacity C
1-C
7, 4 diode D
1-D
4with 2 operational amplifier U
1and U
2; The current signal of described current sample and comparison circuit sampling thereof is the electric current flowing through IGBT, and when overcurrent appears in IGBT, the output of the output of current sample and comparison circuit 1 thereof is low level; When IGBT electric current is normal, the output of the output of current sample and comparison circuit 1 thereof is high level on the contrary.
The control method of described a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD is: when over current fault appears in circuit; the output of the output of current sample and comparison circuit 1 thereof is low level; CPLD programmable logic device exports 4 roads immediately when this low level being detected and is low level pwm signal: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal; thus turn off full-bridge circuit 4 IGBT, and the first state inputting pwm signal when latch fault occurs.
When the electric current of IGBT recovers normal, if the first input pwm signal that when there is over current fault, CPLD programmable logic device latches is low level, then when the first input pwm signal is high level, CPLD programmable logic device exports the 4 normal pwm signals in road: the first output pwm signal, second output pwm signal, 3rd output pwm signal, 4th output pwm signal, now to input pwm signal the same for the first output pwm signal and first, it is the same that second output pwm signal and second inputs pwm signal, it is the same that 3rd output pwm signal and the 3rd inputs pwm signal, it is the same that 4th output pwm signal and the 4th inputs pwm signal, if and the first input pwm signal that when breaking down, CPLD programmable logic device latches is high level, then when the first input pwm signal is low level, CPLD programmable logic device exports the 4 normal pwm signals in road: the first output pwm signal, second output pwm signal, 3rd output pwm signal, 4th output pwm signal, now to input pwm signal the same for the first output pwm signal and first, it is the same that second output pwm signal and second inputs pwm signal, it is the same that 3rd output pwm signal and the 3rd inputs pwm signal, it is the same that 4th output pwm signal and the 4th inputs pwm signal, over current fault is avoided to recur when first cycle, IGBT always closes in first cycle, thus the asymmetric electric current that eliminating transformer produces because only there is half-wave current, eliminating transformer bias phenomenon.
Compared with prior art, the present invention has the following advantages and technique effect:
1, circuit is simple and easy to realize, and simultaneously when over current fault appears in circuit, four IGBT can turn off simultaneously;
2, by phase-shifting full-bridge overcurrent self-shield control method, make circuit working in self-shield state, eliminate the transformer bias phenomenon caused when continuous over current fault appears in IGBT;
3, realize the self-shield of full-bridge circuit overcurrent with minimum pwm signal, be conducive to multi-machine parallel connection and control, cost-saving.
Accompanying drawing explanation
Fig. 1 is a kind of phase-shifting full-bridge overcurrent self-protection circuit circuit diagram based on CPLD of execution mode;
Fig. 2 is current sample and the comparison circuit figure thereof of execution mode.
Fig. 3 is the logical circuitry that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode controls;
Fig. 4 is the active crystal oscillating circuit figure of execution mode;
Fig. 5 is the sequential logic figure that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode controls.
Embodiment
Below in conjunction with accompanying drawing, enforcement of the present invention is further described in detail.
As shown in Figure 1, a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD, figure comprises: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit 1 thereof; Described dsp controller produces with Dead Time and the between two complementary pwm signal in 4 tunnels: the first input pwm signal PWM1, the second input pwm signal PWM2, the 3rd input pwm signal PWM3, the 4th input pwm signal PWM4; The output of 4 road pwm signals, current sample and comparison circuit thereof that 5 I/O mouths of described CPLD programmable logic device export with dsp controller is respectively connected, and exports 4 tunnels by its 4 I/O mouths and have overcurrent protection and with Dead Time and pwm signal complementary between two: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD.
The first described input pwm signal PWM1, the second input pwm signal PWM2, the 3rd input pwm signal PWM3, the 4th input pwm signal PWM4 form 4 road phase-shifting full-bridge pwm signals, wherein the second input pwm signal PWM2 is oppositely obtained by the first input pwm signal PWM1, and the 4th input pwm signal PWM4 is oppositely obtained by the 3rd input pwm signal PWM3.
As preferably, described dsp processor selects Texas Instruments 2000 series DSP controller.
As preferably, described CPLD Programmable Logic Controller selects the MAX7000 series CPLD Programmable Logic Controller of altera corp.
As shown in Figure 2, described current sample and comparison circuit 1, figure thereof comprise: Hall current sensor P, 16 resistance R
1-R
16, 7 electric capacity C
1-C
7, 4 diode D
1-D
4with 2 operational amplifier U
1and U
2;
Described Hall current sensor P adopts CSM300LT series Hall current sensor, and when the electric current flowing through IGBT is timing, Hall current sensor CSM300LT exports positive current, the first resistance R
1upper voltage u
1for positive voltage signal u
1+, the second diode D
2conducting, the first operational amplifier u
1form anti-phase scaling circuit, its output is
When flowing through the electric current of IGBT for time negative, Hall current sensor exports negative current, the first resistance R
1upper voltage u
1for negative voltage signal u
1-, the first diode D
1conducting, the first operational amplifier u
1form voltage follower, now the first operational amplifier u
1export because of the second diode D
2end and can not late-class circuit be inputted.
By the second amplifier u
2u1 and u2 sues for peace by the anti-phase summation operation circuit formed, and its output voltage is
u
1＝u
1++u
1-（3）
Formula (1) and (3) are substituted into formula (2) have
Positive 12V voltage is through the 12 resistance R
12, the 13 resistance R
13dividing potential drop obtains u
o*and and u
owith u
o*relatively, wherein
The u when overcurrent appears in IGBT
obe greater than u
o*, now the first comparator U
3output low level, namely the output VI of the output of current sample and comparison circuit 1 thereof is low level; The u when IGBT electric current is normal on the contrary
obe less than u
o *, the first comparator U
3export high level, namely the output VI of the output of current sample and comparison circuit 1 thereof is high level.
Control method for above-mentioned a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD is: when over current fault appears in circuit; the output VI of the output of current sample and comparison circuit 1 thereof is low level; CPLD programmable logic device exports 4 roads immediately when this low level being detected and is low level pwm signal: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD; thus turn off full-bridge circuit 4 IGBT, and the first state inputting pwm signal PWM1 when latch fault occurs.
When the electric current of IGBT recovers normal, if the first input pwm signal PWM1 that when there is over current fault, CPLD programmable logic device latches is low level, then when the first input pwm signal PWM1 is high level, CPLD programmable logic device exports the 4 normal pwm signals in road: the first output pwm signal PWMA, second output pwm signal PWMB, 3rd output pwm signal PWMC, 4th output pwm signal PWMD, now to input pwm signal PWM1 the same for the first output pwm signal PWMA and first, it is the same that second output pwm signal PWMB and second inputs pwm signal PWM2, it is the same that 3rd output pwm signal PWMC and the 3rd inputs pwm signal PWM3, it is the same that 4th output pwm signal PWMD and the 4th inputs pwm signal PWM4, if and the first input pwm signal PWM1 that when breaking down, CPLD programmable logic device latches is high level, then when the first input pwm signal PWM1 is low level, CPLD programmable logic device exports the 4 normal pwm signals in road: the first output pwm signal PWMA, second output pwm signal PWMB, 3rd output pwm signal PWMC, 4th output pwm signal PWMD, now to input pwm signal PWM1 the same for the first output pwm signal PWMA and first, it is the same that second output pwm signal PWMB and second inputs pwm signal PWM2, it is the same that 3rd output pwm signal PWMC and the 3rd inputs pwm signal PWM3, it is the same that 4th output pwm signal PWMD and the 4th inputs pwm signal PWM4, over current fault is avoided to recur when first cycle, IGBT always closes in first cycle, thus the asymmetric electric current that eliminating transformer produces because only there is half-wave current, eliminating transformer bias phenomenon.
Fig. 3 is the logical circuitry that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD controls, figure comprises: dsp controller 4 PWM outputs, current sample and comparison circuit 1 thereof, active crystal oscillating circuit 2, first trailing edge triggered D flip flop D1, second trailing edge triggered D flip flop D2, first dual input or door OR1, second dual input or door OR2, first not gate NOT1, first dual input and door AND1, second dual input and door AND2, 3rd dual input and door AND3, 4th three value and gate AND4, 5th dual input and door AND5, 6th dual input and door AND6, 7th dual input and door AND7, 8th dual input and door AND8, described dsp controller 4 PWM outputs are: the first input pwm signal output 3, second inputs pwm signal output the 4, the 3rd and inputs pwm signal output the 5, the 4th input pwm signal output 6, the D input and first of described first trailing edge triggered D flip flop D1 inputs pwm signal output 3 and is connected, and CLK input is connected with the output of the second dual input or door OR2, the output and first of described first not gate NOT1 inputs pwm signal output 3 and is connected, described first dual input is connected with the output of the first not gate NOT1 with the first input end of door AND1, and the second input is connected with the output Q of the first trailing edge triggered D flip flop D1, the first input end of described second dual input and door AND2 and the output Q of the first trailing edge triggered D flip flop D1 disconnected, the second input and first inputs pwm signal output 3 and is connected, the first input end of described first dual input or door OR1 is connected with the output of the first dual input with door AND1, and the second input is connected with the output of the second dual input with door AND2, the D input of described second trailing edge triggered D flip flop D2 is connected with the output of the second dual input or door OR2, and CLK input is connected with the output CLKIN of active crystal oscillating circuit 2, the output VI of the output of the first input end of described 3rd dual input and door AND3 and current sample and comparison circuit 1 thereof is connected, and the second input is connected with the output Q of the second trailing edge triggered D flip flop D2, the first input end of described 4th three value and gate AND4 and the output Q of the second trailing edge triggered D flip flop D2 disconnected, the output VI of the output of the second input and current sample and comparison circuit 1 thereof is connected, and the 3rd input is connected with the output of the first dual input or door OR1, the second described dual input or the first input end of door OR2 are connected with the output of door AND3 with the 3rd dual input, and the second input is connected with the output of the 4th three value and gate AND4, the 5th described dual input and door AND5, the 6th dual input and door AND6, the 7th dual input and door AND7, the 8th dual input and the first input end of door AND8 input pwm signal output 3, second respectively and input pwm signal output 4, the 3rd and input pwm signal output 5, the 4th and input pwm signal output 6 and be connected with first, second input of described 5th dual input and door AND5, the 6th dual input and door AND6, the 7th dual input and door AND7, the 8th dual input and door AND8 all connects together, and is connected with the second dual input or door OR2 output, the switch of output 4 switching tubes on control circuit two brachium pontis of described 5th dual input and door AND5, the 6th dual input and door AND6, the 7th dual input and door AND7, the 8th dual input and door AND8.
As shown in Figure 4, described active crystal oscillating circuit 2, comprising: active crystal oscillator OSC, the 17 resistance R
17, 2 electric capacity (C
8and C
9), the first inductance L
1; The first described inductance L
1the positive 3.3V power supply of a termination, the other end and the 8th electric capacity C
8with the 9th electric capacity C
9one end connect, then to be connected with the vdd terminal of active crystal oscillator OSC; The 8th described electric capacity C
8with the 9th electric capacity C
9the other end all ground connection; The 17 described resistance R
17one end hold with the OUT of active crystal oscillator OSC and be connected, the other end is the output CLKIN of active crystal oscillating circuit 2; The GND of described active crystal oscillator OSC holds ground connection, and OE end is unsettled.
Described a kind of control method realizing the logical circuit of phase-shifting full-bridge overcurrent self-shield control based on CPLD is:
When overcurrent appears in IGBT, comprise the steps:
(S1) output (VI) of the output of current sample and comparison circuit (1) thereof is low level, makes the 3rd dual input and door (AND3), the 4th three value and gate (AND4) output low level;
(S2) because the output of the 3rd dual input and door (AND3), the 4th three value and gate (AND4) is low level, so the output (Y) of the second dual input or door (OR2) is low level;
(S3) output (Y) of the second dual input or door (OR2) is low level, make the second trailing edge triggered D flip flop (D2) output Q and Q non-output low level and high level respectively, namely the output (Y*) of the second trailing edge triggered D flip flop (D2) output Q is low level; Make the 5th dual input and door (AND5), the 6th dual input and door (AND6), the 7th dual input and door (AND7), the 8th dual input and door (AND8) output low level, 4 IGBT in breaking circuit simultaneously;
(S4) output (Y) of now the second dual input or door (OR2) drops to low level by high level, and then trigger the first trailing edge triggered D flip flop (D1), first trailing edge triggered D flip flop (D1) preserves the state of the first input pwm signal (PWM1), and namely the output (PWM1*) of the output Q of the first trailing edge triggered D flip flop (D1) equals the first value inputting pwm signal (PWM1) when overcurrent occurs;
When the electric current flowing through IGBT recovers normal, comprise the steps:
If the output that 1. now output Q and Q of the first trailing edge triggered D flip flop (D1) is non-is respectively low level and high level, when namely representing generation overcurrent, first input pwm signal (PWM1) is in low level, then when the first input pwm signal (PWM1) is for high level, the output (PWM1*) non-due to the output Q of the first trailing edge triggered D flip flop (D1) and the first input pwm signal (PWM1) are high level, make the second dual input and door (AND2) export high level;
2. the second dual input and door (AND2) export high level, make the first dual input or door (OR1) export high level;
3. because the output (VI) of the first dual input or door, the output Q not sum current sample of the second trailing edge triggered D flip flop (D2) and the output of comparison circuit (1) thereof is high level, the 4th three value and gate (AND4) is made to export high level;
4. the 4th three value and gate (AND4) exports high level, and make the output of the second dual input or door (OR2) revert to high level, then four road PWM normally export;
5. the output that output Q and Q of the first trailing edge triggered D flip flop (D1) is non-is respectively high level and low level, when namely representing generation overcurrent, first input pwm signal (PWM1) is in high level, then when the first input pwm signal (PWM1) is for low level, because the first input pwm signal (PWM1) is low level, the first not gate (NOT1) is made to export high level;
6. the output of the output Q of the first not gate (NOT1) and the first trailing edge triggered D flip flop (D1) is high level, makes the first dual input and door (AND1) export high level;
7. because the first dual input and door (AND1) export high level, the first dual input or door (OR1) is made to export high level;
8. because the output (VI) of the first dual input or door (OR1), the output Q not sum current sample of the second trailing edge triggered D flip flop (D2) and the output of comparison circuit (1) thereof is high level, then the 4th three value and gate (AND4) exports high level;
9. the 4th three value and gate (AND4) exports high level, and make the output of the second dual input or door (OR2) revert to high level, then four road PWM normally export.
Fig. 5 is the sequential logic figure that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode controls, when t1, the first output VI inputting the output of pwm signal PWM1 and current sample and comparison circuit 1 thereof is low level, then now the output Y of the second dual input or door OR2 becomes low level, all become high level to the first output VI inputting the output of pwm signal PWM1 and current sample and comparison circuit 1 thereof during t2, then the output Y of the second dual input or door OR2 recovers high level; When t3, first inputs pwm signal PWM1 and is high level and the output VI of the output of current sample and comparison circuit 1 thereof is low level, then now the output Y of the second dual input or door OR2 becomes low level, to first inputting pwm signal PWM1 and become low level and the output VI of the output of current sample and comparison circuit 1 thereof is high level during t4, then the output Y of the second dual input or door OR2 recovers high level, four road pwm signals are normally exported, thus can eliminating transformer bias phenomenon.
Table 1 is the truth table that a kind of phase-shifting full-bridge overcurrent self-shield based on CPLD of execution mode controls, in table, state Z1 represents that the output VI of the output of now current sample and comparison circuit 1 thereof is low level, then the first input pwm signal PWM1 is the output Y of high level or low level second dual input or door OR2 is all low level; State Z2 represents that the output VI of the output of now current sample and comparison circuit 1 thereof and the output Y* of the second trailing edge triggered D flip flop D2 output Q is high level, then the first input pwm signal PWM1 is the output Y of high level or low level second dual input or door OR2 is all high level; State Z3 represents that the output PWM1* that the output VI of the output of now current sample and comparison circuit 1 thereof is high level, the output Q of the output Y* of the second trailing edge triggered D flip flop D2 output Q and the first trailing edge triggered D flip flop D1 is non-is low level, then now only have when the first input pwm signal PWM1 is high level, the output Y of the second dual input or door OR2 is just high level; State Z4 represents that the output PWM1* that the output Q of the output VI of the output of now current sample and comparison circuit 1 thereof and the first trailing edge triggered D flip flop D1 is non-is high level, the output Y* of the second trailing edge triggered D flip flop D2 output Q is low level, then now only have when the first input pwm signal PWM1 is low level, the output Y of the second dual input or door OR2 is just high level.
Table 1
Those skilled in the art can make various amendment to this specific embodiment or supplement or adopt similar mode to substitute under the prerequisite without prejudice to principle of the present invention and essence, but these changes all fall into protection scope of the present invention.Therefore the technology of the present invention scope is not limited to above-described embodiment.
Claims (5)
1. based on a phase-shifting full-bridge overcurrent self-protection circuit of CPLD, it is characterized in that comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit (1) thereof; Described dsp controller produces with Dead Time and the between two complementary pwm signal in 4 tunnels: the first input pwm signal (PWM1), the second input pwm signal (PWM2), the 3rd input pwm signal (PWM3), the 4th input pwm signal (PWM4); The output of 4 road pwm signals, current sample and comparison circuit thereof that 5 I/O mouths of described CPLD programmable logic device export with dsp controller is respectively connected, and exports 4 tunnels by its 4 I/O mouths and have overcurrent protection and with Dead Time and pwm signal complementary between two: the first output pwm signal (PWMA), the second output pwm signal (PWMB), the 3rd output pwm signal (PWMC), the 4th output pwm signal (PWMD); Described current sample and comparison circuit (1) thereof comprising: Hall current sensor P, 16 resistance (R
1-R
16), 7 electric capacity (C
1-C
7), 4 diode (D
1-D
4) and 2 operational amplifier (U
1, U
2); The current signal that described current sample and comparison circuit (1) thereof are sampled is the electric current flowing through IGBT, and when overcurrent appears in IGBT, the output (VI) of the output of current sample and comparison circuit (1) thereof is low level; When IGBT electric current is normal, the output (VI) of the output of current sample and comparison circuit (1) thereof is high level on the contrary.
2. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1, is characterized in that described dsp processor adopts Texas Instruments 2000 series DSP controller.
3. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1, is characterized in that described CPLD Programmable Logic Controller adopts the MAX7000 series CPLD Programmable Logic Controller of altera corp.
4. a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD according to claim 1; it is characterized in that the first described input pwm signal (PWM1), the second input pwm signal (PWM2), the 3rd input pwm signal (PWM3), the 4th input pwm signal (PWM4) form 4 road phase-shifting full-bridge pwm signals; wherein the second input pwm signal (PWM2) is oppositely obtained by the first input pwm signal (PWM1), and the 4th input pwm signal (PWM4) is oppositely obtained by the 3rd input pwm signal (PWM3).
5. the control method for a kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD described in any one of claim 1-4 is: when over current fault appears in circuit, the output (VI) of the output of current sample and comparison circuit (1) thereof is low level, CPLD programmable logic device exports 4 roads immediately when this low level being detected and is low level pwm signal: the first output pwm signal (PWMA), second output pwm signal (PWMB), 3rd output pwm signal (PWMC), 4th output pwm signal (PWMD), thus turn off full-bridge circuit 4 IGBT, and latch fault first state inputting pwm signal (PWM1) when occurring,
When the electric current of IGBT recovers normal, if the first input pwm signal (PWM1) that when there is over current fault, CPLD programmable logic device latches is low level, then export the 4 normal pwm signals in road in the first input pwm signal (PWM1) for CPLD programmable logic device during high level: the first output pwm signal (PWMA), second output pwm signal (PWMB), 3rd output pwm signal (PWMC), 4th output pwm signal (PWMD), now to input pwm signal (PWM1) the same for the first output pwm signal (PWMA) and first, it is the same that second output pwm signal (PWMB) and second inputs pwm signal (PWM2), it is the same that 3rd output pwm signal (PWMC) and the 3rd inputs pwm signal (PWM3), it is the same that 4th output pwm signal (PWMD) and the 4th inputs pwm signal (PWM4), if and the first input pwm signal (PWM1) that when breaking down, CPLD programmable logic device latches is high level, then export the 4 normal pwm signals in road in the first input pwm signal (PWM1) for CPLD programmable logic device during low level: the first output pwm signal (PWMA), second output pwm signal (PWMB), 3rd output pwm signal (PWMC), 4th output pwm signal (PWMD), now to input pwm signal (PWM1) the same for the first output pwm signal (PWMA) and first, it is the same that second output pwm signal (PWMB) and second inputs pwm signal (PWM2), it is the same that 3rd output pwm signal (PWMC) and the 3rd inputs pwm signal (PWM3), it is the same that 4th output pwm signal (PWMD) and the 4th inputs pwm signal (PWM4), over current fault is avoided to recur when first cycle, IGBT always closes in first cycle, thus the asymmetric electric current that eliminating transformer produces because only there is half-wave current, eliminating transformer bias phenomenon.
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|---|---|---|---|---|
| CN105633918B (en) * | 2014-11-07 | 2019-02-12 | 北京时代科技股份有限公司 | A kind of diamagnetic saturation device of inverter |
| CN104660257A (en) * | 2015-03-25 | 2015-05-27 | 天津七六四通信导航技术有限公司 | L-band frequency synthesizer circuit |
| CN104967091A (en) * | 2015-07-08 | 2015-10-07 | 置富存储科技(深圳)有限公司 | Overvoltage and overcurrent protection circuit |
| CN105656298B (en) * | 2016-04-11 | 2018-01-05 | 北京国铁路阳技术有限公司 | A kind of peak point current current-limiting apparatus based on DSP+CPLD controls |
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| CN203434601U (en) * | 2013-07-31 | 2014-02-12 | 华南理工大学 | Phase shift full bridge over-current self-protection circuit based on CPLD |
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| CN103036405A (en) * | 2011-09-30 | 2013-04-10 | 艾默生网络能源有限公司 | Synchronous rectification switching tube driving method and device of phase-shifted full-bridge circuit |
| CN103078505A (en) * | 2013-01-12 | 2013-05-01 | 华南理工大学 | Phase-shifted full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
| CN203434601U (en) * | 2013-07-31 | 2014-02-12 | 华南理工大学 | Phase shift full bridge over-current self-protection circuit based on CPLD |
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