CN103401218A - CPLD (Complex Programmable Logic Device)-based phase-shifted full bridge over-current self-protection circuit and control method thereof - Google Patents
CPLD (Complex Programmable Logic Device)-based phase-shifted full bridge over-current self-protection circuit and control method thereof Download PDFInfo
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- CN103401218A CN103401218A CN2013103288247A CN201310328824A CN103401218A CN 103401218 A CN103401218 A CN 103401218A CN 2013103288247 A CN2013103288247 A CN 2013103288247A CN 201310328824 A CN201310328824 A CN 201310328824A CN 103401218 A CN103401218 A CN 103401218A
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Abstract
The invention discloses a CPLD (Complex Programmable Logic Device)-based phase-shifted full bridge over-current self-protection circuit. The circuit comprises a DSP (Digital Signal Processor) controller, a CPLD programmable controller, a current sampler and a comparison circuit thereof, wherein the DSP controller generates four paths of mutually complementary PWM (Pulse Width Modulation) signals with dead zone time; five I/O (Input/Output) ports of the CPLD programmable logic device are connected with four paths of PWM signals output by the DSP controller and outputs of the current sampler and the comparison circuit thereof respectively; and four paths of mutually complementary PWM signals with over-current protection and dead zone time are output through the four I/O ports. The periodic self-protection circuit is simple and practical to realize over-current fault protection with least PWM signals, save the design cost and meanwhile eliminate the transformer bias phenomenon produced by continuous fault protection.
Description
Technical field
The present invention relates to phase-shifting full-bridge switch power technology field, be specifically related to a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit and control method thereof.
Background technology
Phase whole-bridging circuit, as the soft switch circuit of a comparative maturity, is usually used in middle large power, electrically source circuit.Full-bridge circuit IGBT commonly used is as switching tube, when over current fault occurring, IGBT can bear moment overcurrent general no more than 10us of time, certainly will burn IGBT if only by dsp controller, process over current fault.The four road PWM that drive simultaneously IGBT are generally produced by dsp controller, and the 4 road pwm signals of exporting due to dsp controller are complementary in twos,, so when over current fault occurring, IGBT is all turn-offed simultaneously, can't meet the real work requirement.Moreover overcurrent period protection commonly used can cause the voltage bias phenomenon at circuit working during at continuous over current fault, affects device lifetime.
Summary of the invention
Deficiency for the prior art existence; the present invention discloses a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit and control method thereof; when over current fault occurring; can realize that the complete shut-down of switching tube breaks and eliminates the bias phenomenon that transformer produces when continuous over current fault occurring with minimum pwm signal; improve the dsp controller utilance; save cost, this control method is reliable, circuit simple, be easy to realization.
The present invention is for achieving the above object, and the technical scheme that adopts is as follows:
A kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit, comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit thereof; Described dsp controller produces 4 tunnels with Dead Time and complementary pwm signal in twos: the first input pwm signal, the second input pwm signal, the 3rd input pwm signal, the 4th input pwm signal; 5 I/O mouths of described CPLD programmable logic device are connected with the output of 4 road pwm signals, current sample and the comparison circuit thereof of dsp controller output respectively, and by its 4 I/O mouths output 4 tunnels, have overcurrent protection and with Dead Time and the pwm signal of complementation in twos: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal.
Described the first input pwm signal, the second input pwm signal, the 3rd input pwm signal (PWM3), the 4th input pwm signal form 4 road phase-shifting full-bridge pwm signals, wherein the second input pwm signal is oppositely obtained by the first input pwm signal, and the 4th input pwm signal is oppositely obtained by the 3rd input pwm signal (PWM3).
As preferably, described dsp processor is selected Texas Instruments's 2000 series DSP controllers.
As preferably, described CPLD Programmable Logic Controller is selected the MAX7000 series CPLD Programmable Logic Controller of altera corp.
Described current sample and comparison circuit thereof comprise: Hall current sensor P, 16 resistance R
1-R
16, 7 capacitor C
1-C
7, 4 diode D
1-D
4With 2 operational amplifier U
1And U
2The current signal of described current sample and comparison circuit sampling thereof is the electric current that flows through IGBT, and when overcurrent appearred in IGBT, the output of current sample and comparison circuit 1 thereof was output as low level; The output of current sample and comparison circuit 1 thereof is output as high level when the IGBT electric current is normal on the contrary.
The described a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit's control method is: when over current fault appears in circuit; the output of current sample and comparison circuit 1 thereof is output as low level; export immediately 4 roads when the CPLD programmable logic device detects this low level and be low level pwm signal: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal; thereby turn-off 4 IGBT of full-bridge circuit, and the state of latch fault first input pwm signal while occurring.
when the electric current of IGBT recovers normal, if the first input pwm signal that when over current fault occurs, the CPLD programmable logic device latchs is low level, the CPLD programmable logic device is exported the 4 normal pwm signals in road when the first input pwm signal is high level: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal, this moment, the first output pwm signal was the same with the first input pwm signal, the second output pwm signal is the same with the second input pwm signal, the 3rd output pwm signal is the same with the 3rd input pwm signal, the 4th output pwm signal is the same with the 4th input pwm signal, if and the first input pwm signal that the CPLD programmable logic device latchs while breaking down is high level, the CPLD programmable logic device is exported the 4 normal pwm signals in road when the first input pwm signal is low level: the first output pwm signal, the second output pwm signal, the 3rd output pwm signal, the 4th output pwm signal, this moment, the first output pwm signal was the same with the first input pwm signal, the second output pwm signal is the same with the second input pwm signal, the 3rd output pwm signal is the same with the 3rd input pwm signal, the 4th output pwm signal is the same with the 4th input pwm signal, avoid over current fault to recur when first cycle, IGBT always closes in first cycle, thereby the asymmetric electric current of eliminating transformer because only occurring that half-wave current produces, the eliminating transformer bias phenomenon.
Compare with the prior art scheme, the present invention has the following advantages and technique effect:
1, circuit is simple and easy to realize, when over current fault appearred in circuit, four IGBT can turn-off simultaneously simultaneously;
2, by phase-shifting full-bridge overcurrent self-shield control method, make circuit working at the self-shield state, disappear except when IGBT caused transformer bias phenomenon while continuous over current fault occurring;
3, realize the self-shield of full-bridge circuit overcurrent with minimum pwm signal, be conducive to multi-machine parallel connection and control, save cost.
Description of drawings
Fig. 1 is a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit circuit diagram of execution mode;
Fig. 2 is current sample and the comparison circuit figure thereof of execution mode.
Fig. 3 is the logical circuitry that a kind of overcurrent of phase-shifting full-bridge based on CPLD self-shield of execution mode is controlled;
Fig. 4 is the active crystal oscillating circuit figure of execution mode;
Fig. 5 is the sequential logic figure that a kind of overcurrent of phase-shifting full-bridge based on CPLD self-shield of execution mode is controlled.
Embodiment
Below in conjunction with accompanying drawing, enforcement of the present invention is further described in detail.
As shown in Figure 1, a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit, figure comprises: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit 1 thereof; Described dsp controller generation 4 tunnels are with Dead Time and the pwm signal of complementation: the first input pwm signal PWM1, second inputs pwm signal PWM2, the 3rd input pwm signal PWM3, the 4th inputs pwm signal PWM4 in twos; 5 I/O mouths of described CPLD programmable logic device are connected with the output of 4 road pwm signals, current sample and the comparison circuit thereof of dsp controller output respectively, and by its 4 I/O mouths output 4 tunnels, have overcurrent protection and with Dead Time and the pwm signal of complementation in twos: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD.
Described the first input pwm signal PWM1, the second input pwm signal PWM2, the 3rd input pwm signal PWM3, the 4th input pwm signal PWM4 form 4 road phase-shifting full-bridge pwm signals, wherein the second input pwm signal PWM2 is oppositely obtained by the first input pwm signal PWM1, and the 4th input pwm signal PWM4 is oppositely obtained by the 3rd input pwm signal PWM3.
As preferably, described dsp processor is selected Texas Instruments's 2000 series DSP controllers.
As preferably, described CPLD Programmable Logic Controller is selected the MAX7000 series CPLD Programmable Logic Controller of altera corp.
As shown in Figure 2, described current sample and comparison circuit 1 thereof, figure comprises: Hall current sensor P, 16 resistance R
1-R
16, 7 capacitor C
1-C
7, 4 diode D
1-D
4With 2 operational amplifier U
1And U
2
Described Hall current sensor P adopts CSM300LT series Hall current sensor, and when the electric current that flows through IGBT is timing, Hall current sensor CSM300LT exports positive current, the first resistance R
1Upper voltage u
1For positive voltage signal u
1+, the second diode D
2Conducting, the first operational amplifier u
1Form anti-phase scale operation circuit, it is output as
When the electric current that flows through IGBT when negative, Hall current sensor output negative current, the first resistance R
1Upper voltage u
1For negative voltage signal u
1-, the first diode D
1Conducting, the first operational amplifier u
1Form voltage follower, at this moment the first operational amplifier u
1Output is because of the second diode D
2End and can not input late-class circuit.
By the second amplifier u
2The anti-phase summation operation circuit that forms is with u1 and u2 summation, and its output voltage is
u
1＝u
1++u
1- （3）
Formula (1) and (3) substitution formula (2) are had
Positive 12V voltage is through the 12 resistance R
12, the 13 resistance R
13Dividing potential drop obtains u
o*And and u
oWith u
o*Relatively, wherein
U when overcurrent appears in IGBT
oGreater than u
o*, this moment the first comparator U
3Output low level, namely the output VI of the output of current sample and comparison circuit 1 thereof is low level; Opposite when the IGBT electric current is normal u
oLess than u
o *, the first comparator U
3The output high level, namely the output VI of the output of current sample and comparison circuit 1 thereof is high level.
The control method that is used for the above-mentioned a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit is: when over current fault appears in circuit; the output VI of the output of current sample and comparison circuit 1 thereof is low level; export immediately 4 roads when the CPLD programmable logic device detects this low level and be low level pwm signal: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD; thereby turn-off 4 IGBT of full-bridge circuit, and the state of latch fault first input pwm signal PWM1 while occurring.
when the electric current of IGBT recovers normal, if the first input pwm signal PWM1 that when over current fault occurs, the CPLD programmable logic device latchs is low level, the CPLD programmable logic device is exported the 4 normal pwm signals in road when the first input pwm signal PWM1 is high level: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD, this moment, the first output pwm signal PWMA was the same with the first input pwm signal PWM1, the second output pwm signal PWMB is the same with the second input pwm signal PWM2, the 3rd output pwm signal PWMC is the same with the 3rd input pwm signal PWM3, the 4th output pwm signal PWMD is the same with the 4th input pwm signal PWM4, if and the first input pwm signal PWM1 that the CPLD programmable logic device latchs while breaking down is high level, the CPLD programmable logic device is exported the 4 normal pwm signals in road when the first input pwm signal PWM1 is low level: the first output pwm signal PWMA, the second output pwm signal PWMB, the 3rd output pwm signal PWMC, the 4th output pwm signal PWMD, this moment, the first output pwm signal PWMA was the same with the first input pwm signal PWM1, the second output pwm signal PWMB is the same with the second input pwm signal PWM2, the 3rd output pwm signal PWMC is the same with the 3rd input pwm signal PWM3, the 4th output pwm signal PWMD is the same with the 4th input pwm signal PWM4, avoid over current fault to recur when first cycle, IGBT always closes in first cycle, thereby the asymmetric electric current of eliminating transformer because only occurring that half-wave current produces, the eliminating transformer bias phenomenon.
Fig. 3 is the logical circuitry that a kind of overcurrent of phase-shifting full-bridge based on CPLD self-shield is controlled, figure comprises: 4 PWM outputs of dsp controller, current sample and comparison circuit 1 thereof, active crystal oscillating circuit 2, the first trailing edge triggers d type flip flop D1, the second trailing edge triggers d type flip flop D2, the first dual input or door OR1, the second dual input or door OR2, the first not gate NOT1, the first dual input and door AND1, the second dual input and door AND2, the 3rd dual input and door AND3, the 4th three value and gate AND4, the 5th dual input and door AND5, the 6th dual input and door AND6, the 7th dual input and door AND7, the 8th dual input and door AND8, 4 PWM outputs of described dsp controller are: the first input pwm signal output 3, the second input pwm signal output 4, the 3rd input pwm signal output 5, the 4th input pwm signal output 6, the D input that described the first trailing edge triggers d type flip flop D1 is connected with the first input pwm signal output 3, and the CLK input is connected with the output of the second dual input or door OR2, the output of described the first not gate NOT1 is connected with the first input pwm signal output 3, described the first dual input is connected with the output of the first not gate NOT1 with the first input end of door AND1, and the second input is connected with the output Q that the first trailing edge triggers d type flip flop D1, the output Q of the first input end of described the second dual input and door AND2 and the first trailing edge triggering d type flip flop D1 is disconnected, and the second input and the first input pwm signal output 3 are connected, the first input end of described the first dual input or door OR1 is connected with the output of door AND1 with the first dual input, and the second input is connected with the output of door AND2 with the second dual input, the D input that described the second trailing edge triggers d type flip flop D2 is connected with the output of the second dual input or door OR2, and the CLK input is connected with the output CLKIN of active crystal oscillating circuit 2, described the 3rd dual input is connected with the output VI of the output of current sample and comparison circuit 1 thereof with the first input end of door AND3, and the second input is connected with the output Q that the second trailing edge triggers d type flip flop D2, the output Q of the first input end of described the 4th three value and gate AND4 and the second trailing edge triggering d type flip flop D2 is disconnected, the second input is connected with the output VI of the output of current sample and comparison circuit 1 thereof, and the 3rd input is connected with the output of the first dual input or door OR1, the first input end of described the second dual input or door OR2 is connected with the output of door AND3 with the 3rd dual input, and the second input is connected with the output of the 4th three value and gate AND4, described the 5th dual input is connected with the first input pwm signal output 3, the second input pwm signal output 4, the 3rd input pwm signal output 5, the 4th input pwm signal output 6 respectively with the first input end of door AND8 with door AND7, the 8th dual input with door AND6, the 7th dual input with door AND5, the 6th dual input, described the 5th dual input all connects together with the second input of door AND8 with door AND7, the 8th dual input, and with the second dual input or door OR2 output, is connected with door AND6, the 7th dual input with door AND5, the 6th dual input, the output of described the 5th dual input and an AND5, the 6th dual input and a door AND6, the 7th dual input and an AND7, the 8th dual input and an AND8 is used for the switch of 4 switching tubes on control circuit two brachium pontis.
As shown in Figure 4, described active crystal oscillating circuit 2 comprises: active crystal oscillator OSC, the 17 resistance R
17, 2 electric capacity (C
8And C
9), the first inductance L
1Described the first inductance L
1Termination positive 3.3V power supply, the other end and the 8th capacitor C
8With the 9th capacitor C
9An end connect, then with the vdd terminal of active crystal oscillator OSC, be connected; Described the 8th capacitor C
8With the 9th capacitor C
9Other end ground connection all; Described the 17 resistance R
17The OUT end of an end and active crystal oscillator OSC be connected, the other end is the output CLKIN of active crystal oscillating circuit 2; The GND end ground connection of described active crystal oscillator OSC, the OE end is unsettled.
Describedly a kind ofly based on CPLD, realize that the control method of the logical circuit that the self-shield of phase-shifting full-bridge overcurrent is controlled is:
When overcurrent appears in IGBT, comprise the steps:
(S1) output (VI) of the output of current sample and comparison circuit thereof (1) is low level, makes the 3rd dual input and door (AND3), the 4th three value and gate (AND4) output low level;
(S2) because the 3rd dual input and the output of door (AND3), the 4th three value and gate (AND4) are low level, so the output (Y) of the second dual input or door (OR2) is low level;
(S3) output (Y) of the second dual input or door (OR2) is low level, make the second trailing edge trigger d type flip flop (D2) output Q and Q non-output low level and high level respectively, namely the output (Y*) of the second trailing edge triggering d type flip flop (D2) output Q is low level; Make simultaneously the 5th dual input and door (AND5), the 6th dual input and door (AND6), the 7th dual input and door (AND7), the 8th dual input and door (AND8) output low level, 4 IGBT in breaking circuit;
(S4) output (Y) of the second dual input this moment or door (OR2) drops to low level by high level, and then trigger the first trailing edge and trigger d type flip flop (D1), the first trailing edge triggers d type flip flop (D1) and preserves the state of the first input pwm signal (PWM1), i.e. the value of the first input pwm signal (PWM1) when the output (PWM1*) of the output Q of the first trailing edge triggering d type flip flop (D1) equals the overcurrent generation;
When the electric current that flows through IGBT recovers normal, comprise the steps:
If 1. output Q and the non-output of Q of trailing edge triggering d type flip flop this moment first (D1) are respectively low level and high level, when namely overcurrent occurs in expression, the first input pwm signal (PWM1) is in low level, when the first input pwm signal (PWM1) is high level, non-output (PWM1*) and the first input pwm signal (PWM1) of output Q that triggers d type flip flop (D1) due to the first trailing edge is high level, makes the second dual input and door (AND2) output high level;
2. the second dual input and door (AND2) output high level, make the first dual input or door (OR1) output high level;
3. the output (VI) that triggers the output of the output Q not sum current sample of d type flip flop (D2) and comparison circuit (1) thereof due to the first dual input or door, the second trailing edge is high level, makes the 4th three value and gate (AND4) output high level;
4. the 4th three value and gate (AND4) output high level, make the output of the second dual input or door (OR2) revert to high level ，Ze Si road PWM and normally export;
5. output Q and the non-output of Q of the first trailing edge triggering d type flip flop (D1) are respectively high level and low level, when namely overcurrent occurs in expression, the first input pwm signal (PWM1) is in high level, when the first input pwm signal (PWM1) is low level,, because the first input pwm signal (PWM1) is low level, make the first not gate (NOT1) output high level;
6. the output of the output Q of the first not gate (NOT1) and the first trailing edge triggering d type flip flop (D1) is high level, makes the first dual input and door (AND1) output high level;
7., due to the first dual input and door (AND1) output high level, make the first dual input or door (OR1) output high level;
8. the output (VI) that triggers the output of the output Q not sum current sample of d type flip flop (D2) and comparison circuit (1) thereof due to the first dual input or door (OR1), the second trailing edge is high level, the 4th three value and gate (AND4) output high level;
9. the 4th three value and gate (AND4) output high level, make the output of the second dual input or door (OR2) revert to high level ，Ze Si road PWM and normally export.
Fig. 5 is the sequential logic figure that a kind of overcurrent of phase-shifting full-bridge based on CPLD self-shield of execution mode is controlled, the output VI of the output of the first input pwm signal PWM1 and current sample and comparison circuit 1 thereof is low level when t1, the output Y of the second dual input this moment or door OR2 becomes low level, during to t2, the output VI of the output of the first input pwm signal PWM1 and current sample and comparison circuit 1 thereof all becomes high level, and the output Y of the second dual input or door OR2 recovers high level; The first input pwm signal PWM1 is that the output VI of the output of high level and current sample and comparison circuit 1 thereof is low level when t3, the output Y of the second dual input this moment or door OR2 becomes low level, during to t4, to become the output VI of the output of low level and current sample and comparison circuit 1 thereof be high level to the first input pwm signal PWM1, the output Y of the second dual input or door OR2 recovers high level, four road pwm signals are normally exported, thus can the eliminating transformer bias phenomenon.
Table 1 is the truth table that a kind of overcurrent of phase-shifting full-bridge based on CPLD self-shield of execution mode is controlled, in table, state Z1 represents that the output VI of the output of this moment current sample and comparison circuit 1 thereof is low level, and the first input pwm signal PWM1 is that high level or the output Y of low level the second dual input or door OR2 are low level; State Z2 represents that the output VI of output of this moment current sample and comparison circuit 1 thereof and the output Y* that the second trailing edge triggers d type flip flop D2 output Q be high level, and the first input pwm signal PWM1 is that high level or the output Y of low level the second dual input or door OR2 are high level; State Z3 represents that the output VI of the output of this moment current sample and comparison circuit 1 thereof is that high level, the second trailing edge trigger the output Y* of d type flip flop D2 output Q and the non-output PWM1* of output Q that the first trailing edge triggers d type flip flop D1 is low level, only have this moment when the first input pwm signal PWM1 is high level, the output Y of the second dual input or door OR2 is just high level; State Z4 represents that the output VI of output of this moment current sample and comparison circuit 1 thereof and the output Y* that the non-output PWM1* of output Q that the first trailing edge triggers d type flip flop D1 be high level, the second trailing edge triggering d type flip flop D2 output Q are low level, only have this moment when the first input pwm signal PWM1 is low level, the output Y of the second dual input or door OR2 is just high level.
Table 1
Those skilled in the art can make various modifications to this specific embodiment or supplement or adopt similar mode to substitute under the prerequisite without prejudice to principle of the present invention and essence, but these changes all fall into protection scope of the present invention.Therefore the technology of the present invention scope is not limited to above-described embodiment.
Claims (6)
1. the overcurrent of the phase-shifting full-bridge based on a CPLD self-protection circuit, is characterized in that comprising: dsp controller, CPLD Programmable Logic Controller, current sample and comparison circuit (1) thereof; Described dsp controller produces 4 tunnels with Dead Time and complementary pwm signal in twos: the first input pwm signal (PWM1), the second input pwm signal (PWM2), the 3rd input pwm signal (PWM3), the 4th input pwm signal (PWM4); 5 I/O mouths of described CPLD programmable logic device are connected with the output of 4 road pwm signals, current sample and the comparison circuit thereof of dsp controller output respectively, and by its 4 I/O mouths output 4 tunnels, have overcurrent protection and with Dead Time and the pwm signal of complementation in twos: the first output pwm signal (PWMA), the second output pwm signal (PWMB), the 3rd output pwm signal (PWMC), the 4th output pwm signal (PWMD).
2. a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit according to claim 1, is characterized in that described dsp processor adopts Texas Instruments's 2000 series DSP controllers.
3. a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit according to claim 1, is characterized in that described CPLD Programmable Logic Controller adopts the MAX7000 series CPLD Programmable Logic Controller of altera corp.
4. a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit according to claim 1; it is characterized in that described the first input pwm signal (PWM1), the second input pwm signal (PWM2), the 3rd input pwm signal (PWM3), the 4th input pwm signal (PWM4) form 4 road phase-shifting full-bridge pwm signals; wherein the second input pwm signal (PWM2) is oppositely obtained by the first input pwm signal (PWM1), and the 4th input pwm signal (PWM4) is oppositely obtained by the 3rd input pwm signal (PWM3).
5. a kind of overcurrent of phase-shifting full-bridge based on CPLD self-protection circuit according to claim 1, is characterized in that described current sample and comparison circuit thereof (1) comprising: Hall current sensor P, 16 resistance (R
1-R
16), 7 electric capacity (C
1-C
7), 4 diode (D
1-D
4) and 2 operational amplifier (U
1, U
2); The current signal of described current sample and comparison circuit thereof (1) sampling is the electric current that flows through IGBT, and when overcurrent appearred in IGBT, the output (VI) of the output of current sample and comparison circuit thereof (1) was low level; The output (VI) of the output of current sample and comparison circuit (1) thereof is high level when the IGBT electric current is normal on the contrary.
6. the control method that is used for the described a kind of overcurrent of phase-shifting full-bridge based on the CPLD self-protection circuit of claim 1-5 any one is: when over current fault appears in circuit, the output (VI) of the output of current sample and comparison circuit thereof (1) is low level, export immediately 4 roads when the CPLD programmable logic device detects this low level and be low level pwm signal: the first output pwm signal (PWMA), the second output pwm signal (PWMB), the 3rd output pwm signal (PWMC), the 4th output pwm signal (PWMD), thereby turn-off 4 IGBT of full-bridge circuit, and the state of latch fault first input pwm signal (PWM1) while occurring,
when the electric current of IGBT recovers normal, if the first input pwm signal (PWM1) that when over current fault occurs, the CPLD programmable logic device latchs is low level, the CPLD programmable logic device is exported the 4 normal pwm signals in road when the first input pwm signal (PWM1) is high level: the first output pwm signal (PWMA), the second output pwm signal (PWMB), the 3rd output pwm signal (PWMC), the 4th output pwm signal (PWMD), the first output pwm signal this moment (PWMA) is the same with the first input pwm signal (PWM1), the second output pwm signal (PWMB) is the same with the second input pwm signal (PWM2), the 3rd output pwm signal (PWMC) is the same with the 3rd input pwm signal (PWM3), the 4th output pwm signal (PWMD) is the same with the 4th input pwm signal (PWM4), if and the first input pwm signal (PWM1) that the CPLD programmable logic device latchs while breaking down is high level, the CPLD programmable logic device is exported the 4 normal pwm signals in road when the first input pwm signal (PWM1) is low level: the first output pwm signal (PWMA), the second output pwm signal (PWMB), the 3rd output pwm signal (PWMC), the 4th output pwm signal (PWMD), the first output pwm signal this moment (PWMA) is the same with the first input pwm signal (PWM1), the second output pwm signal (PWMB) is the same with the second input pwm signal (PWM2), the 3rd output pwm signal (PWMC) is the same with the 3rd input pwm signal (PWM3), the 4th output pwm signal (PWMD) is the same with the 4th input pwm signal (PWM4), avoid over current fault to recur when first cycle, IGBT always closes in first cycle, thereby the asymmetric electric current of eliminating transformer because only occurring that half-wave current produces, the eliminating transformer bias phenomenon.
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|---|---|---|---|
| CN201310328824.7A CN103401218B (en) | 2013-07-31 | 2013-07-31 | A kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof |
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|---|---|---|---|
| CN201310328824.7A CN103401218B (en) | 2013-07-31 | 2013-07-31 | A kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof |
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| CN103401218A true CN103401218A (en) | 2013-11-20 |
| CN103401218B CN103401218B (en) | 2016-03-02 |
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| CN201310328824.7A Active CN103401218B (en) | 2013-07-31 | 2013-07-31 | A kind of phase-shifting full-bridge overcurrent self-protection circuit based on CPLD and control method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104660257A (en) * | 2015-03-25 | 2015-05-27 | 天津七六四通信导航技术有限公司 | L-band frequency synthesizer circuit |
| CN104967091A (en) * | 2015-07-08 | 2015-10-07 | 置富存储科技(深圳)有限公司 | Overvoltage and overcurrent protection circuit |
| CN105633918A (en) * | 2014-11-07 | 2016-06-01 | 北京时代科技股份有限公司 | Inversion power supply magnetic saturation prevention apparatus |
| CN105656298A (en) * | 2016-04-11 | 2016-06-08 | 北京国铁路阳技术有限公司 | Peak current limiting device based on DSP (Digital Signal Processor)+CPLD (Complex Programmable Logic Device) control and control method |
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| CN103036405A (en) * | 2011-09-30 | 2013-04-10 | 艾默生网络能源有限公司 | Synchronous rectification switching tube driving method and device of phase-shifted full-bridge circuit |
| CN103078505A (en) * | 2013-01-12 | 2013-05-01 | 华南理工大学 | Phase-shifted full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
| CN203434601U (en) * | 2013-07-31 | 2014-02-12 | 华南理工大学 | Phase shift full bridge over-current self-protection circuit based on CPLD |
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| CN103036405A (en) * | 2011-09-30 | 2013-04-10 | 艾默生网络能源有限公司 | Synchronous rectification switching tube driving method and device of phase-shifted full-bridge circuit |
| CN103078505A (en) * | 2013-01-12 | 2013-05-01 | 华南理工大学 | Phase-shifted full-bridge power supply module parallel circuit based on digital signal processor (DSP) |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105633918A (en) * | 2014-11-07 | 2016-06-01 | 北京时代科技股份有限公司 | Inversion power supply magnetic saturation prevention apparatus |
| CN105633918B (en) * | 2014-11-07 | 2019-02-12 | 北京时代科技股份有限公司 | A kind of diamagnetic saturation device of inverter |
| CN104660257A (en) * | 2015-03-25 | 2015-05-27 | 天津七六四通信导航技术有限公司 | L-band frequency synthesizer circuit |
| CN104967091A (en) * | 2015-07-08 | 2015-10-07 | 置富存储科技(深圳)有限公司 | Overvoltage and overcurrent protection circuit |
| CN105656298A (en) * | 2016-04-11 | 2016-06-08 | 北京国铁路阳技术有限公司 | Peak current limiting device based on DSP (Digital Signal Processor)+CPLD (Complex Programmable Logic Device) control and control method |
| CN105656298B (en) * | 2016-04-11 | 2018-01-05 | 北京国铁路阳技术有限公司 | A kind of peak point current current-limiting apparatus based on DSP+CPLD controls |
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