CN105656298B - One kind of peak current limiting device based on the control dsp + cpld - Google Patents

One kind of peak current limiting device based on the control dsp + cpld Download PDF

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CN105656298B
CN105656298B CN 201610220560 CN201610220560A CN105656298B CN 105656298 B CN105656298 B CN 105656298B CN 201610220560 CN201610220560 CN 201610220560 CN 201610220560 A CN201610220560 A CN 201610220560A CN 105656298 B CN105656298 B CN 105656298B
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output
peak current
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CN105656298A (en )
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王树桐
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北京国铁路阳技术有限公司
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一种基于DSP+CPLD控制的峰值电流限流装置及控制方法。 Apparatus and control method based DSP + CPLD control peak current limiting. 装置包括DSP控制电路、CPLD可编程逻辑控制器、峰值限流比较电路和峰值电流采样电路;DSP控制电路与CPLD可编程逻辑控制器连接,峰值电流采样电路与峰值限流比较电路连接,峰值限流比较电路与CPLD可编程逻辑控制器连接。 DSP control means comprises a circuit, a programmable logic controller CPLD, peak current limit comparator circuit and a peak current sampling circuit; CPLD and DSP control circuit connected to a programmable logic controller, the peak current sampling circuit and the peak current limit comparator circuit, peak limit CPLD current comparator circuit connected to the programmable logic controller. 本发明提供的基于DSP+CPLD控制的峰值电流限流装置及控制方法,能够用于在为铁路信号设备提供直流电源的电源模块输出出现短路情况下实现自动保护;当短路解除后能够快速恢复输出供电,因此能够大量减少电源模块短路情况下造成的模块损坏以及模块故障率,进一步提高经济效益。 The present invention provides DSP + peak current limiting device and a control method based on CPLD control, it can be used to automatically short circuit protection of the output in the case of providing DC power to the railway signal to the power modules; when the short releasing can quickly resume the output power supply, it is possible to significantly reduce the module damage caused by short circuit of the power module and a module failure rate, further improving economic efficiency.

Description

一种基于DSP+CPLD控制的峰值电流限流装置 One kind of a peak current limiting means based DSP + CPLD control

技术领域 FIELD

[0001] 本发明属于DSP+CPLD组合控制技术领域,特别是涉及一种基于DSP+CPLD控制的峰值电流限流装置及控制方法。 [0001] The present invention pertains to a combination of DSP + CPLD control technology, particularly to a DSP + peak current limiting device and control method CPLD control.

背景技术 Background technique

[0002] 电源模块是铁路信号电源屏的配套模快,该模块为铁路信号设备提供直流24V电源,以满足铁路信号电源系统对24V直流电源的相关技术要求。 [0002] Power module supporting fast railway signal power mode screen, the module provides 24V DC for the railway signaling equipment, railway signal power to meet system requirements related art 24V DC power. 电源模块是采用移相全桥软开关技术的开关电源,主要由输入防雷、输入滤波、前级AC/DC变换电路、后级DC/DC隔离变压器变换电路、辅助电源、显示功能电路、风扇控制电路和控制电路组成。 Power modules is the use of soft-switching full-bridge phase shift art switching power supply, input from the main lightning protection, input filter, the first stage AC / DC conversion circuit, the stage DC / DC converter circuit isolation transformer, an auxiliary power supply, display circuit, fan The control circuit and a control circuit. 为了提高电源模块的可靠性,该模块还设有完善的保护功能,对于关键保护功能采用软硬件双级保护措施。 In order to improve the reliability of the power module, the module also has a perfect protection for the hardware key using the two-stage protection safeguards.

[0003] 现阶段,直流电源主要采用传统的模拟控制技术实现,但存在控制参数一致性差、 故障定位不准确、效率低等问题。 [0003] At this stage, the main DC power supply using the traditional analog control techniques, but there are control parameters consistency is poor, the fault location is not accurate, and low efficiency. 随着电力电子技术的迅速发展,为了使铁路领域的高频开关电源能够跟上开关电源的发展,提高开关电源的技术含量和智能水平,开发带单片机采用软开关技术的电源已经迫在眉睫。 With the rapid development of electronic technology, in order to make railway field frequency switching power supply switching power supply can keep up with the development, improve the technical content and levels of intelligent switching power supply, with the development of soft-switching technology, single-chip power supply is imminent. 实际工况中,由于各种原因而导致电源模块输出会出现短路情况,这时电源模块短路对模块内部器件的破坏程度最大,如果电源模块输出能够在瞬态出现短路情况下自动保护模块内部器件,当短路解除后仍能继续工作,那将会极大提高电源模块的使用寿命。 The actual operating condition, due to various reasons resulting in the output power is short-circuit condition occurs, then the power module the module is shorted to the extent of damage inside the device's maximum, if the output power is the transient short circuit can occur in the automatic protection device inside the module when the short releasing can still continue to work, it will greatly improve the life of the power module.

发明内容 SUMMARY

[0004]为了解决上述问题,本发明的目的在于提供一种基于DSP+CPLD控制的峰值电流限流装置及控制方法。 [0004] In order to solve the above problems, an object of the present invention is to provide a DSP + peak current limiting device and control method CPLD control.

[0005]为了达到上述目的,本发明提供的基于DSP+CPLD控制的峰值电流限流装置包括: DSP控制电路、CPLD可编程逻辑控制器、峰值限流比较电路和峰值电流采样电路;其中:DSP 控制电路与CPLD可编程逻辑控制器连接,峰值电流采样电路与峰值限流比较电路连接,峰值限流比较电路与CPLD可编程逻辑控制器连接。 [0005] To achieve the above object, the present invention provides a peak current limiting means based DSP + CPLD control comprises: DSP control circuit, CPLD programmable logic controller, the peak current limit comparator circuit and a peak current sampling circuit; wherein: DSP CPLD control circuit connected to a programmable logic controller, the peak current sampling circuit and the peak current limit comparator circuit, the peak current limit comparator circuit connected to the programmable logic controller CPLD.

[0006]所述的DSP控制电路的输出信号端和输入信号端均与CPLD可编程逻辑控制器相连接。 [0006] The input signal and the signal output terminal of the DSP control circuit are connected to a programmable logic controller CPLD.

[0007]所述的峰值电流采样电路的输入端通过电流互感器与变压器原边相连接,输出端与峰值限流比较电路连接。 [0007] The input of the peak current sampling circuit is connected through the current transformer with the transformer primary, the output of the peak current limit comparator circuit.

[000S]所述的CPLD可编程逻辑控制器为可编程逻辑器件,其输入端包括:驱动A输入端、 驱动B输入端、驱动C输入端、驱动D输入端和峰值状态输入端,输出端包括:驱动输出A端、驱动输出B端、驱动输出C端、驱动输出D端和峰值状态输出端;其中:驱动A输入端、驱动B输入端、驱动C输入端和驱动D输入端与DSP控制电路连接、峰值状态输入端与峰值限流比较电路连接,驱动输出A端、驱动输出B端、驱动输出C端和驱动输出D端与移相全桥开关管的控制端直接连接,峰值状态输出端与DSP控制电路连接。 [000s] CPLD said programmable logic controller is a programmable logic device, an input terminal comprising: a drive A input, the B input of the drive, the drive input terminal C, an input terminal D and the peak drive status input terminal, an output terminal comprising: a driver output terminal A to drive the output terminal B, the drive output of the C-terminus, the drive output of the D terminal and a peak state output terminal; wherein: the drive A input, the drive B input, the drive C input terminals and the drive D input and DSP a control circuit connected to the peak state input coupled to peak current limit comparator circuit to drive the output terminal a to drive the output terminal B, the drive output of the C-terminus and the drive output of the D terminal and phase shift control terminal of the full bridge switching transistor directly connected state peak an output terminal connected to the DSP control circuits.

[0009]所述的CPLD可编程逻辑控制器的内部逻辑结构组成包括:第一或门、第二或门、第三或门、延时器、第一触发器、第二触发器、第一与门、第二与门、第三与门、第四与门、第五与门、第六与门、第一非门和第二非门; [0009] The internal logical structure of a programmable logic controller CPLD composition comprising: a first OR gate, a second OR gate, a third OR gate, a delay, a first flip-flop, a second flip-flop, a first aND gate, a second aND gate, the third aND gate, a fourth aND gate, a fifth aND gate, a sixth aND gate, a first NAND gate and a second NAND gate;

[0010]第一或门的两个输入端分别与驱动A输入端和驱动B输入端连接、其输出端与延时器的输入端连接,延时器输出端与第一触发器的第一输入端连接,第一触发器的第二输入端与峰值状态输入端连接,第一触发器输出延时信号; [0010] or the two input terminals of the first gate driver respectively drive A input and the B input terminal, an input terminal and an output terminal connected to a delay device, a first output terminal of the first delay flip-flop input terminal, a second input of the first flip-flop is connected to the peak-status input of the first delay flip-flop output signal;

[0011]第二触发器的第一输入端与第一或门的输出端连接、其第二输入端与峰值状态输入端连接,第二触发器输出端同时与第一与门的输入端和第二与门的第一输入端连接,第一与门的输出端与驱动输出A端连接,第二与门的第二输入端与驱动B输入端连接,第二与门的输出端与驱动输出B端连接; [0011] The second flip-flop a first input terminal connected to the first output terminal to which a second input terminal connected to an input terminal of the peak state, while the second flip-flop output terminal of the first AND gate and an input of a second input terminal connected to the first gate, a first terminal connected to an output terminal a and the gate drive output, a second input of the second aND gate with the drive B input terminal, an output terminal of the second aND gate with the drive B output terminal;

[0012]第一非门的输入端接收延时信号、其输出端与第三与门的第一输入端连接,第三与门的第二输入端与驱动A输入端连接,第三与门的输出端与第二或门的第一输入端连接, 第四与门的第一输入端与驱动C输入端连接、其第二输入端接收延时信号,第四与门的输出端与第二或门的第二输入端连接、第二或门的输出端与驱动输出C端连接; [0012] The input of the first NAND gate receiving the delayed signal, and an output terminal connected to the first input of the third gate, a third input terminal connected to the second input of AND gate drive A, the third AND gate the output terminal and the first input of a second oR gate is connected to a fourth input terminal connected to the first input terminal C of the driving gate, a second input for receiving the delay signal, the fourth output terminal of the first aND gate a second input terminal of the oR gate is connected to two output terminal of the second oR gate is connected to the drive output terminal C;

[0013]第二非门的输入端接收延时信号、其输出端与第五与门的第一输入端连接,第五与门的第二输入端与驱动D输入端连接,第五与门的输出端与第三或门的第一输入端连接, 第六与门的输入端连接延时信号、其输出端与第三或门的第二输入端连接,第三或门的输出端与驱动输出D端连接。 [0013] input of a second NAND gate receiving the delayed signal, and an output terminal connected to the first input terminal of the fifth gate, a fifth input terminal connected to the second input terminal D of the driving gate, a fifth AND gate a first input terminal and the output terminal of the third oR gate is connected to the sixth input terminal connected to the signal delay of the gate, a second input terminal and an output terminal of the third oR gate is connected to the output terminal of the third oR gate D drive output terminal.

[00M]所述的第一触发器和第二触发器为D触发器,其第一输入端为触发器的时钟端,第二输入端为触发器的置1端。 [00M] said first and second flip-flop is a D flip-flop, a first input terminal of the flip-flop clock terminal, a second input terminal of the flip-flop of the opposite end.

[0015]本发明提供的基于DSP+CPLD控制的峰值电流限流装置的控制方法包括按顺序进行的下列步骤: [0015] The control method based on DSP + peak current limiting means CPLD control comprising the steps performed in sequence according to the present invention provides:

[0016]步骤1)正常阶段:在装置正常控制过程中,峰值限流比较电路输出高电平,即峰值状态信号为“高电平”,此时,DSP控制电路的输出驱动信号为正常的移相全桥控制信号; [0017]步骤2)峰值限流阶段:当电源模块中的DC/DC隔离变压器原边电流信号过大,经过峰值电流采样电路后,采样电流信号送入峰值限流比较电路后输出低电平,即峰值状态信号为“低电平”,此时在CPLD可编程逻辑控制器内部会瞬态封锁输入驱动,关闭移相全桥开关管; [0016] Step 1) Normal phase: during the normal control means, peak current limit comparator circuit outputs a high level, i.e., the peak value state signal is "high" at this time, the control circuit outputs a drive signal for the DSP normal phase-shifted full bridge control signals; [0017] step 2) peak limiting stages: when the power supply module, a DC / DC isolation transformer primary current signal is too large, a peak current after the sampling circuit, the sampling signal into the current peak limiting after the comparator circuit outputs a low level, i.e., the peak value state signal is "low", then the programmable logic within CPLD controller input drive blocked transient, phase-shifted full bridge switching off the tube;

[0018]步骤3) DSP控制阶段:DSP控制电路检测到峰值限流比较电路输出低电平时,关闭所有移相全桥开关管的驱动,然后等待20个开关周期后,即延时400微秒,DSP控制电路将以一定的比例缓慢放开输出驱动信号。 [0018] Step. 3) DSP control stage: DSP control circuit detects the peak current limit comparator circuit outputs a low level, the drive off all phase-shifted full bridge switch, and then wait 20 switching cycles, i.e. 400 microseconds delay , DSP will be a certain percentage of the control circuit outputs a drive signal is released slowly.

[0019] 在步骤2)中,所述的瞬态封锁输入驱动,关闭移相全桥开关管的方法包括按顺序进行的下列步骤: [0019] In step 2), the transient blocking input drive phase-shifted full bridge method of closing the switch comprises the following steps in sequence:

[0020] 步骤2.1)峰值电流信号采样阶段:峰值电流采样电路采集变压器原边电流采样信号后传送给峰值限流比较电路,当出现峰值限流时峰值限流比较电路会输出低电平,即峰值状态信号为低电平; [0020] Step 2.1) peak current signal sampling stage: the peak current sampling circuit collects the transformer primary current sensing signal to the peak current limit comparator circuit, when there is a peak current limit peak current limit comparator circuit outputs a low level, i.e., peak state signal is low;

[0021] 步骤2.2)峰值限流硬件保护第一阶段:峰值状态信号瞬态封锁第二触发器,第二触发器输出低电平经过第一与门后输出给驱动输出A端;第二触发器输出低电平与驱动B信号一起经过第二与门后输出给驱动输出B端; [0021] Step 2.2) peak limiting hardware protection first stage: peak transient state signal triggers the second block, the first through the second flip-flop output low and the gate driver output to the output terminal A; second trigger B outputs a low level signal to the drive through the door, together with a second output terminal B to the output driver;

[0022]步骤2.3)峰值限流硬件保护第二阶段:峰值限流硬件保护第一阶段发生的同时, 峰值状^彳目5瞬态封锁第一触发器,第一触发器的输出经过第一非门后与驱动人信号一起经过第三与门输出;第一触发器的输出与驱动c信号一起经过第四与门输出;第三与门输出和第四与门输出一起经过第二或门后输出到驱动输出c端; [0022] Step 2.3) peak limiting hardware protection second stage: hardware protection at the same time limiting the peak occurred first stage, a peak-shaped head 5 ^ left foot transient blockade first flip-flop, a first output of the first flip-flop through the NAND gate of the driving signal through the man with the third output gate; a first flip-flop output signal c through the drive together with the fourth output gate; together with the gate output through the third and fourth aND gate output of the second oR gate after the drive output to the output terminal c;

[0023] ^骤2 • 4)峰值限流硬件保护第三阶段:峰值限流硬件保护第一阶段发生的同时, 峰值状态信号瞬态封锁第一触发器,第一触发器的输出经过第二非门后与驱动〇信号一起经过第五与门输出;第一触发器的输出经过第六与门输出;第五与门的输出和第六与门的输出一起经过第三或门后输出到驱动输出D端; [0023] ^ step 2 • 4) peak current limit protection hardware third stage: the first stage occurring at the same time, the peak transient state signal block a first flip-flop, flip-flop outputs a first peak current limit through the second hardware protection NAND gate through the square drive signal with the fifth output of the aND gate; a first output of the sixth flip-flop through the aND gate output; the output of the fifth aND gate and the output of the sixth aND gate outputs together via the oR gate after a third drive output terminal D;

[0024]步骤2.5)峰值限流控制软件保护阶段:峰值限流硬件保护第一阶段发生的同时, 峰值状态信号送给DSP控制电路,DSP控制电路检测到该低电平脉冲后,关闭所有移相全桥开关管的驱动,并延时400微秒,后逐次放开控制占空比,直至达到正常控制占空比。 [0024] Step 2.5) software to control the peak current limit protection phase: hardware protection peak limiting occurs while the first phase, the peak signal to the DSP status control circuit, the DSP of the control circuit detects a low-level pulse, close all shift phase full bridge drive switch, and 400 microsecond delay, the duty ratio is controlled sequential release, the duty cycle until it reaches the normal control.

[0025]1本发明提供的基于DSP+CPLD控制的峰值电流限流装置及控制方法,能够用于在为铁路信号设备提供直流电源的电源模块输出出现短路情况下实现自动保护;当短路解除后能够快速恢复输出供电,因此能够大量减少电源模块短路情况下造成的模块损坏以及模块故障率,进一步提高经济效益。 [0025] The invention provides a DSP + peak current limiting device and a control method based on CPLD control, it can be used to automatically short circuit protection of the output in the case of providing DC power to the railway signal to the power modules; when the short releasing can quickly restore the output power, it is possible to significantly reduce the module damage caused by short circuit of the power module and a module failure rate, further improving economic efficiency.

附图说明 BRIEF DESCRIPTION

[0026]图1为本发明提供的基于DSP+CPLD控制的峰值电流限流装置的结构示意图。 [0026] Fig 1 a schematic view of the structure of DSP + CPLD control peak current limiting device based on the present disclosure.

[0027]图2为CPLD可编程逻辑控制器内部所需硬件延时信号的原理框图。 [0027] FIG. 2 is a schematic block diagram of the hardware required CPLD signal delay inside the programmable logic controller.

[0028]图3为CPLD可编程逻辑控制器内部所需硬件驱动A,B信号的原理框图。 [0028] FIG. 3 is a programmable logic controller CPLD desired internal hardware drivers A, B block diagram of a signal.

[0029]图4为CPLD可编程逻辑控制器内部所需硬件驱动C信号的原理框图。 [0029] FIG. 4 is a schematic block diagram of the hardware required for the internal signal C driving CPLD programmable logic controller.

[0030]图5为CPLD可编程逻辑控制器内部所需硬件驱动D信号的原理框图。 [0030] FIG. 5 is a schematic block diagram of the hardware required for the drive signal D CPLD internal programmable logic controller.

[0031]图6为本发明提供的采用DSP+CPLD控制的峰值电流限流装置的控制方法流程图。 [0031] FIG. 6 is a control method of the current limiting device using DSP + CPLD control a peak current of a flowchart of the present invention.

具体实施方式 Detailed ways

[0032]下面结合附图和具体实施例对本发明提供的基于DSP+CPLD控制的峰值电流限流装置及控制方法进行详细说明。 The drawings and detailed description of specific embodiments DSP + peak current limiting device and a control method based on the control of the CPLD present invention provides [0032] the following binding.

[0033]如图1所示,本发明提供的基于DSP+CPLD控制的峰值电流限流装置包括:DSP控制电路1、CPLD可编程逻辑控制器2、峰值限流比较电路3和峰值电流采样电路4;其中:DSP控制电路1与CPLD可编程逻辑控制器2连接,峰值电流采样电路4与峰值限流比较电路3连接,峰值限流比较电路3与CPLD可编程逻辑控制器2连接。 [0033] As shown in FIG. 1, the present invention provides DSP + peak current limiting means comprises a CPLD control based on: DSP control circuit 1, a programmable logic controller CPLD 2, the peak current limit comparator circuit 3 and the peak current sampling circuit 4; wherein: DSP control circuit 12 is connected to the CPLD programmable logic controller, the peak current sampling circuit 4 and the peak current limit comparator circuit 3, the peak current limit comparator circuit 2 is connected to a programmable logic controller and CPLD 3.

[0034] DSP控制电路1为本装置总的输入输出控制电路,输入信号为峰值状态信号,输出信号包括驱动A、驱动B、驱动C和驱动D信号;DSP控制电路1的输出信号端和输入信号端均与CPLD可编程逻辑控制器2相连接; [0034] DSP control circuit of the present apparatus 1 the total input-output control circuit, the input signal peak state signal, the output signal includes a drive A, driven drive B, C and D drive signal; a control signal output circuit of the DSP 1 and the input 2 each signal terminal is connected to a programmable logic controller CPLD;

[0035] CPLD可编程逻辑控制器2接收DSP控制电路1发出的驱动A、B和驱动C、D信号,同时接收峰值限流比较电路3输出的峰值状态信号;CPLD可编程逻辑控制器2产生驱动输出A信号、驱动输出B信号、驱动输出C信号和驱动输出D信号,并把峰值状态信号经过整理后反馈给DSP控制电路1; 、 [0035] CPLD DSP programmable logic controller 2 receives the driving control circuit 1 issues A, B, and drive C, D signals, while the peak current limit state peak received signal output from the comparator circuit; CPLD, programmable logic controller 2 generates A drive signal output, the drive signal output B, output C of the drive signals and outputting the drive signal D, and the peak value of the status signal feedback to the DSP, after finishing the control circuit 1;,

[0036]峰值限流比较电路3为比较器电路,用于将峰值电流采样电路4输出的峰值电流信号与设定的峰值限流点进行比较,输出的峰值状态信号传送给CPLD可编程逻辑控制器2; 峰值状态彳目号为反应峰值电流状态的开关量信号。 [0036] The peak current limit comparator circuit is a comparator circuit 3, the peak current limit for peak current setting signal and the peak current sampling circuit 4 outputs are compared, the peak of the state of the output signal to a programmable logic control CPLD 2; head No. state peak left foot switch signal peak current state of the reaction. ^〇37]峰值电流采样电路4用于采集电源模块中DC/DC隔离变压器原边电流的峰值,并将采集到的峰值电流信号传送给峰值限流比较电路3;其输入端通过电流互感器与变压器原边相连接,输出端与峰值限流比较电路3连接。 ^ 〇37] peak current sampling circuit 4 for collecting the peak power module of the primary current DC / DC isolation transformer, and a peak current signal is transmitted to the collected peak current limit comparator circuit 3; its input through the current transformer is connected to the transformer primary side, the output of the peak current limit comparator circuit 3 is connected.

[0038] 所述的峰值电流采样电路4的采样信号取自变压器原边电流信号,经过取样变换变为电压信号,峰值电流比较电路3采用比较器的方法输出固定电平信号,提供给CPLD可编程逻辑控制器2和DSP控制电路1使用。 [0038] The peak current signal of the sampling circuit 4 samples the signal from the transformer primary current through the sample becomes converted voltage signal, the comparator Methods peak current comparison circuit 3 outputs a fixed level signal, may be supplied to the CPLD DSP programmable logic controllers 2 and the control circuit 1 used.

[0039] 所述的峰值电流采样电路4对应的输入电路所采集的信号为变压器原边电流信号。 [0039] The peak current signal of the sampling circuit 4 corresponding to the acquired input circuit transformer primary current signal.

[0040]所述的驱动A、驱动B、驱动C和驱动D信号为移相全桥开关管的驱动信号;其为DSP 控制电路1发出的一连串固定频率的占空比固定的脉冲信号。 [0040] The drive A, driven drive B, C and D drive signal is a drive signal phase-shifted full bridge switching transistor; duty cycle a series of fixed frequency which emits a DSP for a fixed pulse signal control circuit.

[0041]所述的CPLD可编程逻辑控制器2为可编程逻辑器件,其输入端包括:驱动A输入端、 驱动B输入端、驱动C输入端、驱动D输入端和峰值状态输入端,输出端包括:驱动输出A端、驱动输出B端、驱动输出C端、驱动输出D端和峰值状态输出端;其中:驱动A输入端、驱动B输入端、驱动C输入端和驱动D输入端与DSP控制电路1连接、峰值状态输入端与峰值限流比较电路3连接,驱动输出A端、驱动输出B端、驱动输出C端和驱动输出D端与移相全桥开关管的控制端直接连接,峰值状态输出端与DSP控制电路1连接。 [0041] The programmable logic controller of claim 2 CPLD is a programmable logic device, an input terminal comprising: a drive A input, the B input of the drive, the drive input terminal C, an input terminal D and the peak drive status input, output side comprising: a driver output terminal A to drive the output terminal B, the drive output of the C-terminus, the drive output of the D terminal and a peak state output terminal; wherein: the drive A input, the drive B input, the drive C input terminals and the drive D input and DSP control circuit connected to a peak-status input 3 is connected to the peak current limit comparator circuit to drive the output terminal a to drive the output terminal B, the drive output of the C-terminus and the drive output of the D terminal and phase shift control terminal of the full bridge switching tube is directly connected the peak output of the state control circuit 1 is connected with a DSP.

[0042] 如图2-图4所示,所述的CPLD可编程逻辑控制器2的内部逻辑结构组成包括:第一或门5、第二或门14、第三或门18、延时器9、第一触发器10、第二触发器6、第一与门7、第二与门8、第三与门12、第四与门13、第五与门16、第六与门17、第一非门11和第二非门15; [0042] The CPLD is a programmable logic controller internal logic structure 2 shown in FIG. 2 to FIG. 4 a composition comprising: a first OR gate 5, a second OR gate 14, a third OR gate 18, delay 9, a first flip-flop 10, a second flip-flop 6, 7 of the first aND gate, a second aND gate 8, and the third door 12 and fourth door 13, the door 16 and the fifth, the sixth aND gate 17, a first NAND gate 11 and a second NAND gate 15;

[0043]如图2所示,第一或门5的两个输入端分别与驱动A输入端和驱动B输入端连接、其输出端与延时器9的输入端连接,延时器9输出端与第一触发器10的第一输入端连接,第一触发器10的第二输入端与峰值状态输入端连接,第一触发器10输出延时信号19; [0043] 2, the two input terminals of a first OR gate 5 respectively drive the drive A input and the B input terminal, an input terminal and an output terminal connected to the delay 9, the output delay 9 a first end connected to the input of the first flip-flop 10, a second input terminal of the first flip-flop 10 is connected to the peak-status input of the first flip-flop 10 outputs the delayed signal 19;

[0044]如图3所示,第二触发器6的第一输入端与第一或门5的输出端连接、其第二输入端与峰值状态输入端连接,第二触发器6输出端同时与第一与门7的输入端和第二与门8的第一输入端连接,第一与门7的输出端与驱动输出A端连接,第二与门8的第二输入端与驱动B 输入端连接,第二与门8的输出端与驱动输出B端连接; [0044] 3, the second flip-flop 6 is connected to a first input terminal and the output terminal of the first OR gate 5, a second input terminal connected to an input terminal of the peak state, while the second flip-flop output terminal 6 connected to the input of the first aND gate 7 and the first input of the second aND gate 8, the drive output of the output terminal a of the first aND gate 7 is connected to a second input terminal B of the drive of the second aND gate 8 an input terminal connected to the output terminal of the second aND gate 8 is connected to the drive output terminal B;

[0045] 如图4所示,第一非门11的输入端接收延时信号I9、其输出端与第三与门12的第一输入端连接,第三与门12的第二输入端与驱动A输入端连接,第三与门12的输出端与第二或门14的第一输入端连接,第四与门I3的第一输入端与驱动C输入端连接、其第二输入端接收延时信号19,第四与门I3的输出端与第二或门14的第二输入端连接、第二或门14的输出端与驱动输出C端连接; [0045] As shown in FIG 4, a first input of NAND gate 11 receives the delayed signal I9, an output coupled to a first input of the third AND gate 12 is connected to a second input of the third AND gate 12 and the a drive input terminal, a first input of the third aND gate output terminal 12 of the second oR gate 14 is connected to a fourth input terminal connected to the first input of aND gate I3 C drive, and a second input receiving delayed signal 19, a fourth gate connected to the output of I3 with a second input of the second oR gate 14, the output of the second oR gate 14 is connected to the drive output terminal C;

[0046] 如图5所示,第二非门15的输入端接收延时信号19、其输出端与第五与门16的第一输入端连接,第五与门16的第二输入端与驱动D输入端连接,第五与门16的输出端与第三或门18的第一输入端连接,第六与门I7的输入端连接延时信号I9、其输出端与第三或门1S的第二输入端连接,第三或门18的输出端与驱动输出D端连接。 [0046], the input of the second NAND gate 15 receives the delayed signal as shown in 519, the output terminal of the first input terminal of the fifth AND gate 16 is connected to a second input of the fifth AND gate 16 and the drive D input terminal, a first input terminal and the output terminal of the fifth gate 16 and the oR gate 18 is connected to the third input terminal of the sixth gate I7 ​​and I9 is ​​connected to a delay signal, an output terminal of the third oR gate 1S a second input terminal, an output terminal and the D terminal of the third driving output of the oR gate 18 is connected.

[0047] 所述的第一触发器1〇和第二触发器6为D触发器,其第一输入端为触发器的时钟端,第二输入端为触发器的置1端。 [0047] said first and second flip-flop 6 is 1〇 D flip-flop, a first clock input terminal of the flip-flop, a second input terminal of the flipflop is set.

[0048] 如图6所示,本发明提供的基于DSP+CPLD控制的峰值电流限流装置所采用的控制方法包括按顺序进行的下列步骤: [0048] As shown in FIG. 6, the control method of the peak current limiting means based DSP + CPLD control employed in the present invention comprises the following steps in sequence:

[0049]步骤1)正常阶段:在装置正常控制过程中,峰值限流比较电路⑶输出高电平,即峰值状态信号为“高电平”,此时,DSP控制电路(1)的输出驱动信号为正常的移相全桥控制信号; Output drive means in the normal control process, the peak current limit ⑶ comparator circuit outputs a high level, i.e., the peak value state signal is "high", this time, the DSP control circuit (1) is: [0049] Step 1) normal stage signal is phase-shifted full bridge normal control signal;

[0050]步骤2)峰值限流阶段:当电源模块中的DC/DC隔离变压器原边电流信号过大,经过峰值电流采样电路4后,采样电流信号送入峰值限流比较电路3后输出低电平,即峰值状态信号为“低电平”,此时在CPLD可编程逻辑控制器2内部会瞬态封锁输入驱动,关闭移相全桥开关管;起到保护该开关管不受大电流冲击的作用; [0050] Step 2) peak limiting stages: When the power supply module, a DC / DC isolation transformer primary current signal is too large, a peak current after the sampling circuit 4, the sampling signal into the peak current limit comparator circuit 3 outputs a low level, i.e., the peak value state signal is "low", in this case 2 internally blocked transient CPLD programmable logic controller drives the input, closing the phase-shifted full bridge switching transistor; protect the switch from a large current the impact of the action;

[0051]步骤3) DSP控制阶段:DSP控制电路1检测到峰值限流比较电路3输出低电平时,关闭所有移相全桥开关管的驱动,然后等待2〇个开关周期后,即延时400微秒,DSP控制电路1 将以一定的比例缓慢放开输出驱动信号。 [0051] Step 3) DSP control stage: DSP control circuit 1 detects the peak current limit comparator circuit 3 outputs a low level, the drive off all phase-shifted full bridge switch, and then wait 2〇 switching cycles, i.e., delay 400 microseconds, DSP control circuit 1 will be a certain proportion of the slow release of the drive signal output.

[0052]在步骤2)中,所述的瞬态封锁输入驱动,关闭移相全桥开关管的操作即为输出控制操作,其方法包括按顺序进行的下列步骤: [0052] In step 2), said input drive transient blockade, closing the phase shifting operation is the operation of the full bridge output control switch tube, which method comprises the following steps in sequence:

[0053]步骤2.1)峰值电流信号采样阶段:峰值电流采样电路4采集变压器原边电流采样信号后传送给峰值限流比较电路3,当出现峰值限流时峰值限流比较电路3会输出低电平, 即峰值状态信号为低电平; [0053] Step 2.1) peak current acquisition phase: transmitting to the peak current limit comparator circuit 3, when there is a peak current limit peak current limit comparator circuit 3 output will be low after the peak current sampling circuit 4 acquisition transformer primary current sensing signal level, i.e., the peak value state signal is low;

[0054]步骤2.2)峰值限流硬件保护第一阶段:峰值状态信号(低电平信号)瞬态封锁第二触发器6,第二触发器6输出低电平经过第一与门7后输出给驱动输出A端;第二触发器6输出低电平与驱动B信号一起经过第二与门8后输出给驱动输出B端; [0054] Step 2.2) peak limiting hardware protection first stage: peak state signal (low level signal) 6 transient blockade second flip-flop, a second flip-flop 6 outputs a low level after the output of the first AND gate 7 A drive output to the terminal; a second flip-flop 6 outputs a low level and the drive signal B passes along the second aND gate 8 outputs to the drive output terminal B;

[0055]步骤2 • 3)峰值限流硬件保护第二阶段:峰值限流硬件保护第一阶段发生的同时, 峰值状态信号(低电平信号)瞬态封锁第一触发器10,第一触发器1〇的输出经过第一非门n 后与驱动A信号一起经过第三与门丨2输出;第一触发器10的输出与驱动C信号一起经过第四与门13输出;第三与门12输出和第四与门丨3输出一起经过第二或门14后输出到驱动输出C 端; [0055] Step 2 • 3) Peak current limit hardware protection second stage: hardware protection while the first peak current limiting phase occurs, the peak state signal (low level signal) blocked transient first flip-flop 10, a first trigger 1〇 output of the first NAND gate after n a of the drive signal with the second output through the third aND gate Shu; C outputs a drive signal of the first through the fourth flip-flop 10 together with the output of gate 13; third aND gate and with a fourth output 12 via the output 14 to the second oR gate drive output terminal C and an output gate 3 Shu;

[0056]步骤2 • 4)峰值限流硬件保护第三阶段:峰值限流硬件保护第一阶段发生的同时, 峰值状态信号(低电平信号)瞬态封锁第一触发器10,第一触发器10的输出经过第二非门15 后与驱动D信号一起经过第五与门16输出;第一触发器1〇的输出经过第六与门17输出;第五与门16的输出和第六与门17的输出一起经过第三或门18后输出到驱动输出D端; [0056] Step 2 • 4) peak current limit protection hardware third stage: hardware protection peak limiting occurs while the first stage 10, a first trigger state peak signal (low level signal) triggers a first transient blockade 10, after the output of the second NAND gate 15 and the drive signal D via the fifth aND gate 16 with the output; the output of the first flip-flop 1〇 sixth aND gate 17 via the output; the output of the fifth aND gate 16 and the sixth the output of aND gate 17 through the oR gate 18 together with the third output to the D terminal of the output driver;

[0057]步骤2.5)峰值限流控制软件保护阶段:峰值限流硬件保护第一阶段发生的同时, 峰值状态信号送给DSP控制电路1,DSP控制电路1检测到该低电平脉冲后,关闭所有移相全桥开关管的驱动,并延时400微秒,后逐次放开控制占空比,直至达到正常控制占空比。 [0057] Step 2.5) software to control the peak current limit protection phase: hardware protection after peak limiting occurs while the first phase, the peak signal to the DSP control circuit state 1, DSP control circuit 1 detects the low-level pulse, closing All the phase-shifted full bridge drive switch tube, and 400 microsecond delay, the duty ratio is controlled sequential release, the duty cycle until it reaches the normal control.

[0058]本发明提供的基于DSP+CPLD控制的峰值电流限流装置,其控制设备平台采用全电子化设计,现场控制信号全部来自于电源模块内部经过隔离后的信号,由于采用了可编程器件所以该控制方法具有占用的硬件电路少,可靠性高等特点。 [0058] The present invention provides a peak current limiting means based DSP + CPLD control, internet control device which fully electronic design, field control signals of all the internal power module after isolation from the signal, the use of programmable devices Therefore, the hardware control method less occupied with high reliability.

Claims (2)

  1. 1.一种基于DSP+CPLD控制的峰值电流限流装置,所述的基于DSP+CPLD控制的峰值电流限流$置包括:DSP控制电路(1)、CPLD可编程逻辑控制器(2)、峰值限流比较电路⑶和峰值电流采样电路(4);其中:DSP控制电路⑴与CPLD可编程逻辑控制器⑵连接,峰值电流采样电路⑷与峰值限流比较电路⑶连接,峰值限流比较电路⑶与CPLD可编程逻辑控制器⑵ 连接; 其特征在于:所述的CPLD可编程逻辑控制器(2)的内部逻辑结构组成包括:第一或门(5)、第二或门(14)、第三或门(18)、延时器(¾、第一触发器(1〇)、第二触发器(6)、第一与门⑺、第二与门⑻、第三与门(12)、第四与门(13)、第五与门(16)、第六与门(17)、第一非门(11)和第二非门(15); 第一或门(5)的两个输入端分别与驱动A输入端和驱动B输入端连接、其输出端与延时器(9)的输入端连接,延时器(9)输出端与第一触发器(1〇)的 A DSP + CPLD control peak current limiting device based on said peak current control based on DSP + CPLD $ limiting means comprises: DSP control circuit (1), CPLD programmable logic controller (2), ⑶ peak current limit comparator circuit and the peak current sampling circuit (4); wherein: DSP and CPLD control circuit ⑴ ⑵ programmable logic controller is connected, the peak current sampling circuit ⑷ ⑶ peak current limit comparator circuit connected to the peak current limit comparator circuit ⑶ ⑵ and CPLD programmable logic controller is connected; wherein: said CPLD programmable logic controller (2) is composed of internal logic structure comprising: a first oR gate (5), a second oR gate (14), third oR gate (18), delay (¾, a first flip-flop (1〇), second flip-flop (6), a first aND gate ⑺, ⑻ second aND gate, a third aND gate (12) fourth aND gate (13), a fifth aND gate (16), a sixth aND gate (17), a first NAND gate (11) and a second NAND gate (15); a first oR gate (5) of the two inputs respectively drive the drive a input and the B input terminal, an output terminal of the delay device (9) is connected to an input terminal, (9) and the output of the first delay flip-flop (1〇) of 一输入端连接,第一触发器(10)的第二输入端与峰值状态输入端连接,第一触发器(10)输出延时信号(19); 第二触发器(6)的第一输入端与第一或门(5)的输出端连接、其第二输入端与峰值状态输入端连接,第二触发器(6)输出端同时与第一与门(7)的输入端和第二与门(8)的第一输入端连接,第一与门(7)的输出端与驱动输出A端连接,第二与门(8)的第二输入端与驱动B 输入端连接,第二与门⑻的输出端与驱动输出B端连接; 第一非门(11)的输入端接收延时信号(19)、其输出端与第三与门(12)的第一输入端连接,第三与门(12)的第二输入端与驱动A输入端连接,第三与门(12)的输出端与第二或门(14)的第一输入端连接,第四与门(13)的第一输入端与驱动C输入端连接、其第二输入端接收延时信号(19),第四与门(13)的输出端与第二或门(14)的第二输入端连接、第 An input terminal, a first flip-flop (10) connected to a second input terminal of the peak-status input (10) the output signal of the first delay flip-flop (19); a first input of the second flip-flop (6) end of the first oR gate (5) connected to the output, its second input connected to the input terminal of the peak state, (6) simultaneously with the output of the second flip-flop of the first aND gate (7) and a second input terminal aND gate (8) connected to a first input terminal, a first aND gate (7) and the output terminal of the drive output terminal a is connected to a second aND gate (8) and a second input terminal of the drive B input terminal, a second ⑻ gate and the output terminal of the drive output terminal B is connected; a first NAND gate (11) receiving the delayed input signal (19) having an output connected to the first input of the third aND gate (12), the first three aND gate (12) and a second input terminal of the drive a input terminal, a third aND gate (12) and the output terminal of the second oR gate (14) connected to a first input terminal, a fourth aND gate (13) a first input terminal connected to the C input of the driver, a second input receiving the delayed signal (19), a second input of the fourth aND gate (13) and the output terminal of the second oR gate (14) is connected, The first 二或门(14)的输出端与驱动输出C端连接; 第二非门(15)的输入端接收延时信号(19)、其输出端与第五与门(16)的第一输入端连接,第五与门(16)的第二输入端与驱动D输入端连接,第五与门(16)的输出端与第三或门(18)的第一输入端连接,第六与门(17)的输入端连接延时信号(19)、其输出端与第三或门(18)的第二输入端连接,第三或门(18)的输出端与驱动输出D端连接。 Di- or gate (14) output terminal and the C drive output terminal; a second NAND gate (15) receiving the delayed input signal (19), an output terminal of the fifth AND gate (16) a first input terminal connection, the fifth aND gate (16) and a second input terminal connected to the D input terminal of the driving, the fifth aND gate (16) output terminal of the third oR gate (18) connected to a first input terminal, a sixth aND gate (17) connected to an input of a delay signal (19), a second input terminal and an output terminal of the third oR gate (18) is connected to a third oR gate (18) output terminal of the drive output terminal D is connected.
  2. 2.根据权利要求1所述的基于DSP+CPLD控制的峰值电流限流装置,其特征在于:所述的第一触发器(10)和第二触发器(6)为D触发器,其第一输入端为触发器的时钟端,第二输入端为触发器的置1端。 According to claim peak current limiting means based DSP + CPLD control, characterized in that said 1: said first flip-flop (10) and a second flip-flop (6) is a D flip-flop, which first a clock input terminal of flip-flop terminal, a second input terminal of the flipflop is set.
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JPH01103172A (en) * 1987-10-16 1989-04-20 Hitachi Medical Corp Inverter type x-ray device
CN100530926C (en) * 2003-07-31 2009-08-19 快捷韩国半导体有限公司 System and method for convertor
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