CN201402807Y - Integrated circuit encapsulated in double-surface and overlapping - Google Patents
Integrated circuit encapsulated in double-surface and overlapping Download PDFInfo
- Publication number
- CN201402807Y CN201402807Y CN 200920070496 CN200920070496U CN201402807Y CN 201402807 Y CN201402807 Y CN 201402807Y CN 200920070496 CN200920070496 CN 200920070496 CN 200920070496 U CN200920070496 U CN 200920070496U CN 201402807 Y CN201402807 Y CN 201402807Y
- Authority
- CN
- China
- Prior art keywords
- chip
- integrated circuit
- bonding wire
- slide holder
- stacked package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an integrated circuit encapsulated in double-surface and overlapping, wherein a plastic housing (1) is mounted with a slide holder (6) and a lead wire bonding wire (5), aplurality of chips (3) are piled and mounted on the both the front and back surfaces of the slide holder (6) respectively, a parting reject chip (2) is arranged between two neighboring chips on the same surface, a layer of insulation paste is arranged between the parting reject chip (2) and the chips (3), and the two ends of the chip are welded to the lead wire bonding wire (5) through a metal bonding wire (4). The utility model has the advantages of prior utilization of double-surface space through back-to-back encapsulating technology as well as effective utilization of chip perpendicular space through over-lapping encapsulation, therefore the cost can be effectively saved, the space utilization rate is improved, and the bonding wire connection is easy, which particularly suits the batchproduction of high-capacity storage.
Description
Technical field
The utility model relates to the components and parts encapsulation field in a kind of microelectronic packaging technology, relates in particular to a kind of stacked package integrated circuit.
Background technology
The integrated circuit of Plastic Package has its current normal structure and technological process at present, and this normal structure and technological process have been used decades in the world.In recent years, along with the promotion of many portable type electronic products (as: mobile phone, MP3 etc.) market demand, memory also develops to high power capacity, slimming direction.So microelectronics Packaging is had higher requirement,, as shown in Figure 1,, reduced packaging cost for chip-stack encapsulation (stacked die package) has improved packaging density as the main packing forms of memory.Simultaneously, the encapsulation technology of integrated circuit has also obtained development fast.The integrated circuit of the traditional standard profile of Plastic Package generally is by chip, encapsulated plastic, and gold thread or aluminum steel or copper cash, lead frames etc. assemble.NFME has back-to-back encapsulation patent as shown in Figure 2 at present, and patent No. ZL 200420054917.1, and it only is confined to the packing forms of two-sided single-chip at present.So need a kind of technology that back-to-back double-faced packaging is incorporated stacked package.
Summary of the invention
Technical problem to be solved in the utility model provides a kind of integrated circuit of two-sided stacked package, and is low with packaging density in the solution prior art, defect of high cost.
A kind of integrated circuit of two-sided stacked package, slide holder and lead-in wire bonding wire are housed in the plastic casing, the tow sides of described slide holder pile up respectively the polylith chip are housed, be provided with the useless sheet of interlayer between adjacent two chip blocks with one side, be furnished with one deck insulating cement between useless sheet of interlayer and the chip, described chip two ends are soldered to the lead-in wire bonding wire by the metal bonding wire.
Be provided with a glue-line between described chip and the slide holder.
The material of described plastic casing is an epoxy resin.
The tow sides of described slide holder symmetrical stack respectively have the polylith chip.
When welding, all is furnished with described each chip block a heat block and pressing plate.
Beneficial effect
The utility model has the advantage that back-to-back encapsulation technology can preferentially be utilized two-sided space concurrently, the advantage that has simultaneously stacked package chip vertical space effectively to utilize again, can effectively save cost, improve space availability ratio, and the bonding wire ease of connection is specially adapted to the batch process of high capacity memory.
Description of drawings
Fig. 1 is the stacked package schematic diagram of present encapsulation technology comparative maturity;
Fig. 2 is existing back-to-back encapsulation patent schematic diagram;
Fig. 3 is the schematic diagram of the two-sided stacked package circuit of the utility model.
Embodiment
Below in conjunction with specific embodiment, further set forth the utility model.Should be understood that these embodiment only to be used to the utility model is described and be not used in the restriction scope of the present utility model.Should be understood that in addition those skilled in the art can make various changes or modifications the utility model after the content of having read the utility model instruction, these equivalent form of values fall within the application's appended claims institute restricted portion equally.
Embodiment 1
As shown in Figure 3, a kind of integrated circuit of two-sided stacked package, slide holder 6 and lead-in wire bonding wire 5 are housed in the plastic casing 1 that epoxy resin is made, the tow sides of described slide holder 6 symmetrical stack respectively are equipped with polylith chip 3, be provided with a glue-line between chip 3 and the slide holder 6, be provided with the useless sheet 2 of interlayer between adjacent two chip blocks with one side, be furnished with one deck insulating cement between useless sheet 2 of interlayer and the chip 3, described chip two ends are soldered to lead-in wire bonding wire 5 by metal bonding wire 4, all are furnished with a heat block and pressing plate when described each chip block 3 welds.
The utility model adds man-hour in structure, need produce friction between the track to prevent that chip from following at the front and back track bed hedgehopping with loading device, destroys chip surface and reaches the intact bonding wire of bonding.The lead of secondary load framework will carry out pressure-sizing, destroys the silver coating of bonding region when preventing load, behind the bonding goods is returned load and carries out follow-up load, needs abundant curing after each load.The weld zone that do not coexist of the number of chips of piling up according to single face need add the heat block of respective numbers and pressing plate (carry out respectively tow sides bonding with), the effect of heat block and pressing plate is to prevent in bonding process, the coming off or peel off of the reverse side chip that the shake of framework may cause.And consider that the chip on the slide holder is unsettled, because of the reason of heat transmission causes the temperature of chip surface to cause the first solder joint failure welding inadequately.
Claims (5)
1. the integrated circuit of a two-sided stacked package, slide holder (6) and lead-in wire bonding wire (5) are housed in the plastic casing (1), it is characterized in that: the tow sides of described slide holder (6) pile up respectively polylith chip (3) are housed, be provided with the useless sheet (2) of interlayer between adjacent two chip blocks with one side, interlayer gives up and is furnished with one deck insulating cement between sheet (2) and the chip (3), and described chip two ends are soldered to lead-in wire bonding wire (5) by metal bonding wire (4).
2. the integrated circuit of two-sided stacked package as claimed in claim 1 is characterized in that: be provided with a glue-line between described chip (3) and the slide holder (6).
3. the integrated circuit of two-sided stacked package as claimed in claim 1 or 2, it is characterized in that: the material of described plastic casing (1) is an epoxy resin.
4. the integrated circuit of two-sided stacked package as claimed in claim 3, it is characterized in that: the tow sides of described slide holder (6) symmetrical stack respectively have polylith chip (3).
5. the integrated circuit of two-sided stacked package as claimed in claim 4 is characterized in that: all be furnished with a heat block and pressing plate during described each chip block (3) welding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920070496 CN201402807Y (en) | 2009-04-16 | 2009-04-16 | Integrated circuit encapsulated in double-surface and overlapping |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920070496 CN201402807Y (en) | 2009-04-16 | 2009-04-16 | Integrated circuit encapsulated in double-surface and overlapping |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201402807Y true CN201402807Y (en) | 2010-02-10 |
Family
ID=41662608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200920070496 Expired - Lifetime CN201402807Y (en) | 2009-04-16 | 2009-04-16 | Integrated circuit encapsulated in double-surface and overlapping |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201402807Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106419838A (en) * | 2016-08-30 | 2017-02-22 | 福州瑞芯微电子股份有限公司 | Integrated chip for intestinal tract detection and implementation method of integrated chip |
| CN110785898A (en) * | 2017-06-29 | 2020-02-11 | 派克泰克封装技术有限公司 | Method and device for producing a wire connection and component arrangement having a wire connection |
-
2009
- 2009-04-16 CN CN 200920070496 patent/CN201402807Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106419838A (en) * | 2016-08-30 | 2017-02-22 | 福州瑞芯微电子股份有限公司 | Integrated chip for intestinal tract detection and implementation method of integrated chip |
| CN110785898A (en) * | 2017-06-29 | 2020-02-11 | 派克泰克封装技术有限公司 | Method and device for producing a wire connection and component arrangement having a wire connection |
| US11217558B2 (en) | 2017-06-29 | 2022-01-04 | PAC Tech—Packaging Technologies GmbH | Method and device for establishing a wire connection as well as a component arrangement having a wire connection |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Jiangsu province Nantong City Chongchuan road 226001 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 30 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20100210 |