CN201226112Y - System for monitoring high speed clock of digital circuit board - Google Patents
System for monitoring high speed clock of digital circuit board Download PDFInfo
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- CN201226112Y CN201226112Y CNU2008200498144U CN200820049814U CN201226112Y CN 201226112 Y CN201226112 Y CN 201226112Y CN U2008200498144 U CNU2008200498144 U CN U2008200498144U CN 200820049814 U CN200820049814 U CN 200820049814U CN 201226112 Y CN201226112 Y CN 201226112Y
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Abstract
The utility model discloses a high-speed clock monitoring system for a digital circuit board, which is a single circuit clock monitoring system, comprising a stable and non-lost low-speed clock source and a pulse forming circuit, a decision level generator module, a clock lost treatments module which are in turn connected. The pulse forming circuit is connected with the monitored clock system on the digital circuit board. The stable and non-lost low speed clock source is respectively connected with the pulse forming circuit and the decision level generator module at the same time. The frequency of the stable and non-lost low speed clock source is less than or equal to the half of the lowest frequency of the monitored clock source on the digital circuit board. The utility model uses the judging to the correctness of the output level of the digital circuit board to monitor whether the system clock reference source should be lost or not. The problems in the traditional monitoring system that the traditional monitoring system is complicated, the stable and non-lost high speed clock source should be needed, the multiplex clock has frequency division circuit and the like, can be solved. The entire clock monitoring system is much easier to be realized, which has high reliability and has good expandability as well.
Description
Technical field
The utility model relates to the clock monitoring technology of circuit board, specifically is meant the high-frequency clock monitoring system of digital circuit board.
Background technology
Along with the continuous development of Digital Signal Processing, a lot of traditional analog signal processing technologies are all substituted by Digital Signal Processing, more and more the system integration mimic channel and digital circuit.All has digital circuit as mobile phone, base station, host computer, display etc.And the technology of digital circuit is just constantly development also, develops toward the high-speed digital circuit direction, and these digital circuits all need clock reference signal at a high speed, and a lot of chips need provide the timing reference input up to 500MHz.
And the required function that provides of digital circuit board in the future is more and more, and these functions often can't utilize a chip to realize, like this, will integrated various chips on the digital circuit board, need provide different clock sources for these chips.And some main chip has been lost clock signal, will realize circuit board function or infringement circuit board, so, job stability in order to ensure digital circuit board, need signal source of clock on the monitoring digital circuit board,, gather some measures losing under the state in clock source at circuit board, again work of restoring circuit plate or replacement digital circuit board etc. guarantee that system can continue operate as normal.
Since various chips that digital circuit board is general integrated, the clock source of a plurality of different frequencies of needs, so, need the circuit of monitoring multipath clock.On the basis of single channel clock observation circuit, can be extended to the multipath clock signal monitoring circuit.
As shown in Figure 2, when the clock source of monitoring has different frequencies, and the clock behind the frequency division in the time of also can't obtaining a unified frequency-dividing clock, is handled with regard to a plurality of frequency-dividing clock observation circuits of needs.Arbitrary observation circuit outputting alarm information just shows that case of clock loss has appearred in this digital circuit, needs the clock monitoring system in time to handle.When though the clock source of monitoring has different frequencies,, the clock after frequency division is handled can obtain a unified frequency-dividing clock, like this, just as long as a frequency-dividing clock observation circuit can be realized monitoring.Such clock observation circuit as shown in Figure 3.
For the multipath clock observation circuit, if adopt the mode of Fig. 3, can save the frequency-dividing clock observation circuit, but real system often is difficult to obtain a unified frequency-dividing clock, so, cause the application mode of Fig. 3 to be restricted.
For the multipath clock observation circuit, though can adopt the mode of Fig. 2, this processing mode needs more clock observation circuit, and making whole monitoring system more complicated needs the support of more hardware and software resource.
Adopt the cycle judge frequency-dividing clock whether correctly to carry out the circuit of clock monitoring, the system design more complicated, the clock observation circuit simplicity of design that output level is whether correct is judged in employing, but is unfavorable for the expansion of system.
The utility model content
The purpose of this utility model is to overcome the shortcoming of prior art, a kind of high-frequency clock monitoring system of digital circuit board has been proposed, the main employing judges whether the level of digital circuit board output pulse signal correctly comes the monitoring system timing reference input whether to lose, to solve the traditional monitoring system complex, need have stable and problems such as the high-speed clock source do not lost, multipath clock frequency dividing circuit, so that whole clock monitoring system is easier to realize, and has very high reliability, simultaneously, system has good expandability.
The purpose of this utility model is achieved through the following technical solutions: a kind of high-frequency clock monitoring system of digital circuit board, be single channel clock monitoring system, it comprises stable and low-speed clock source of not losing and pulse shaping circuit, decision level generation module, the loss of clock processing module that connects successively, described pulse shaping circuit is connected with monitored clock source on the digital circuit board, and described stable and low-speed clock source that do not lose is connected respectively with pulse shaping circuit, decision level generation module simultaneously; The described stable and frequency low-speed clock source of not losing is less than or equal to half of monitored clock source low-limit frequency on the digital circuit board.
Monitored clock source is needs the signal source of clock of monitoring on the digital circuit board, it can be any one the clock source that need monitor on the digital circuit board, its clock frequency requirement is more than or equal to 2 times stable and the low-speed clock source of not losing, otherwise, can't realize the monitoring function of clock.
The low-speed clock source of stablizing and not losing is mainly as the work clock source of pulse shaping circuit in the clock monitoring system and decision level generation module.The frequency requirement in this low-speed clock source is less than or equal to half of minimum clock frequency on the monitored digital circuit board.And this low-speed clock source must be stablized and is difficult for losing, because this clock source need provide reference clock for each module in the monitoring system, lose in this clock source, will make that monitoring system can't operate as normal.Because this clock source frequency of operation is generally less than 10MHz, so in actual design, this type of constant clock source ratio is easier to obtain, and guarantees that also the monitoring system that the utility model proposes has good feasibility, is easy to realize.
For realizing the utility model better, expand on the basis of the high-frequency clock monitoring system of above-mentioned digital circuit board, described stable and low-speed clock source that do not lose also is connected respectively with pulse shaping circuit, decision level generation module by low-speed clock source frequency dividing circuit.Thereby avoided the application limitations of the high-frequency clock monitoring system of above-mentioned digital circuit board, enlarged the range of application of clock monitoring system.
For realizing the utility model better, for the situation that adopts low-speed clock source frequency dividing circuit, realize that by described low-speed clock source frequency dividing circuit frequency division is carried out in the described clock source of stablizing and not losing to be handled, concrete frequency division multiple can be decided according to the minimum clock frequency on the described digital circuit board.
Because the clock monitoring system in the utility model mainly adopts the method for the monitoring of judging that output level is whether correct, is easy to carry out system extension, realization is to the monitoring of multipath clock, that is:
A kind of high-frequency clock monitoring system of digital circuit board, be the multipath clock monitoring system, it comprises low-speed clock source, decision level processing module, loss of clock processing module and a plurality of mutual corresponding pulse shaping circuit, decision level generation module that connects stable and that do not lose, each pulse shaping circuit respectively with digital circuit board on each corresponding connection of monitored clock source, described stable and low-speed clock source that do not lose is connected respectively with each pulse shaping circuit, decision level generation module simultaneously; Each decision level generation module is connected with described decision level processing module, loss of clock processing module respectively, and the described stable and frequency low-speed clock source of not losing is less than or equal to half of monitored clock source low-limit frequency on the digital circuit board.
Similar to single channel high-frequency clock monitoring system, the corresponding connection also distinguished by a plurality of low-speed clocks source frequency dividing circuit and each pulse shaping circuit, decision level generation module in the described low-speed clock source of stablizing and not losing.
The utility model compared with prior art has the following advantages and beneficial effect:
1. adopt low-frequency clock source as reference source in the monitoring system, economize on resources, feasibility is strong.For traditional clock detection circuit, all need a frequency-dividing clock circuit, and the frequency-dividing clock circuit is generally operational under the highest clock frequency of system, like this, system needs stable, as not lose a high-frequency clock reference source.This often is difficult to reach this requirement in real system.
2. mainly adopt based on judging whether the digital circuit board output level correctly comes the monitoring system timing reference input whether to lose, and system design is simple.Traditional circuit that whether correctly carries out the clock monitoring based on the cycle of judging frequency-dividing clock of comparing, the simple structure of native system is easy to realize.
Description of drawings
Fig. 1 is traditional single channel clock observation circuit reference diagram;
Fig. 2 is a kind of form of traditional multipath clock signal monitoring circuit;
Fig. 3 is the another kind of form of traditional multipath clock signal monitoring circuit;
Fig. 4 is the structural representation of the high-frequency clock monitoring system (single channel) of the utility model digital circuit board;
Fig. 5 is the pulse waveform synoptic diagram of the different in width of the generation of pulse shaping circuit described in the utility model;
Fig. 6 is the pulse waveform synoptic diagram of the out of phase of the generation of pulse shaping circuit described in the utility model;
Fig. 7 is the another kind of structural framing figure of the high-frequency clock monitoring system (single channel) of the utility model digital circuit board;
Fig. 8 is the structural representation of the high-frequency clock monitoring system (multichannel) of the utility model digital circuit board;
Fig. 9 is the another kind of structural representation of the high-frequency clock monitoring system (multichannel) of the utility model digital circuit board.
Embodiment
Below in conjunction with embodiment and accompanying drawing the utility model is described in further detail, but embodiment of the present utility model is not limited thereto.
Embodiment one
As shown in Figure 4, the high-frequency clock monitoring system of this digital circuit board, during for single channel clock monitoring system, it comprises stable and low-speed clock source of not losing and pulse shaping circuit, decision level generation module, the loss of clock processing module that connects successively, described pulse shaping circuit is connected with monitored clock source on the digital circuit board, and described stable and low-speed clock source that do not lose is connected respectively with pulse shaping circuit, decision level generation module simultaneously; The described stable and frequency low-speed clock source of not losing is less than or equal to half of monitored clock source low-limit frequency on the digital circuit board.
As shown in Figure 4, the course of work that adopts the high-frequency clock monitoring system of present embodiment one described digital circuit board to carry out the monitoring of single channel high-frequency clock is such:
(1) with the work clock source of the described low-speed clock source of stablizing and not losing as described pulse shaping circuit and decision level generation module;
(2) under the triggering in the described low-speed clock source of stablizing and not losing, if does not lose in monitored clock source, the width range of the cyclic pulse signal of then described pulse shaping circuit output is 0.5M～2M, wherein M is the pulsewidth (as shown in Figure 5) in the described low-speed clock source of stablizing and not losing, and the phase place of described cyclic pulse signal can arbitrarily be adjusted (as shown in Figure 6); If lose in monitored clock source, then determine the height of the corresponding level signal of described pulse shaping circuit output according to the alarm mode that native system adopted, also be, if adopt the high level alarm, the pulse shaping circuit output low level signal in the utility model then, if adopt the low level alarm, then the pulse shaping circuit in the utility model is exported high level signal;
(3) described decision level generation module is according to the output signal of described pulse shaping circuit, and under the triggering in the described low-speed clock source of stablizing and not losing, output high level or low level signal are as decision level;
(4) described loss of clock processing module is according to the output signal of decision level generation module, whether can differentiate monitored clock source loses: even system adopts low level alarm mode, when then the output signal of decision level generation module is high level signal, represent monitored clock source operate as normal, when the output signal of decision level generation module is low level signal, represent that then monitored clock source loses; If system adopts high level alarm mode, otherwise then;
(5) lose processing module when clock and realize that monitored clock source loses, then the warning information that will lose reports processing, and starts clock recovery and handle, or outputting alarm information, prompting to digital circuit board reset, processing such as detection, maintenance.
Embodiment two
As shown in Figure 7, the high-frequency clock monitoring system of the digital circuit board of present embodiment two is to expand on the basis of high-frequency clock monitoring system of embodiment one digital circuit board, adopted low-speed clock source frequency dividing circuit, promptly its low-speed clock source stable and that do not lose also is connected respectively with pulse shaping circuit, decision level generation module by low-speed clock source frequency dividing circuit; Other structures are identical with embodiment one.Thereby avoided the application limitations of the high-frequency clock monitoring system of above-mentioned digital circuit board, enlarged the range of application of clock monitoring system.
As shown in Figure 7, when the high-frequency clock monitoring system of employing present embodiment two described digital circuit boards is carried out the monitoring of single channel high-frequency clock, realize that by described low-speed clock source frequency dividing circuit frequency division is carried out in the described clock source of stablizing and not losing to be handled, concrete frequency division multiple can be decided according to the minimum clock frequency on the described digital circuit board; Other courses of work are identical with the course of work of the high-frequency clock monitoring system of embodiment one described digital circuit board.
Embodiment three
As shown in Figure 8, when the high-frequency clock monitoring system of the digital circuit board of embodiment one is expanded to the multipath clock monitoring system, it comprises low-speed clock source, decision level processing module, loss of clock processing module and a plurality of mutual corresponding pulse shaping circuit, decision level generation module that connects stable and that do not lose, each pulse shaping circuit respectively with digital circuit board on each corresponding connection of monitored clock source, described stable and low-speed clock source that do not lose is connected respectively with each pulse shaping circuit, decision level generation module simultaneously; Each decision level generation module is connected with described decision level processing module, loss of clock processing module respectively, and the described stable and frequency low-speed clock source of not losing is less than or equal to half of monitored clock source low-limit frequency on the digital circuit board.
As shown in Figure 8, with the single channel high-frequency clock monitoring similar process of embodiment one, it is such adopting the multipath high-speed clock monitoring process of the high-frequency clock monitoring system of present embodiment three described digital circuit boards:
(1) with the work clock source of the described low-speed clock source of stablizing and not losing as described pulse shaping circuit and decision level generation module;
(2) under the triggering in the described low-speed clock source of stablizing and not losing, if does not lose in monitored clock source, the width range of the cyclic pulse signal of then described pulse shaping circuit output is 0.5M～2M, wherein M is the pulsewidth (as shown in Figure 5) in the described low-speed clock source of stablizing and not losing, and the phase place of described cyclic pulse signal can arbitrarily be adjusted (as shown in Figure 6); If lose in monitored clock source, then determine the height of the corresponding level signal of described pulse shaping circuit output according to the alarm mode that native system adopted, also be, if adopt the high level alarm, the pulse shaping circuit output low level signal in the utility model then, if adopt the low level alarm, then the pulse shaping circuit in the utility model is exported high level signal;
(3) described decision level generation module is according to the output signal of described pulse shaping circuit, and under the triggering in the described low-speed clock source of stablizing and not losing, output high level or low level signal are as decision level;
(4) the decision level processing module receives the output signal from the decision level generation module, and carry out that burr is eliminated and the logic of level signal with or mutually or processing, total decision level signal of formation system;
(5) described loss of clock processing module is according to total decision level signal of decision level processing module output, whether can differentiate monitored clock source loses: even system adopts low level alarm mode, when then total decision level signal is high level signal, represent monitored clock source operate as normal, when total decision level signal is low level signal, represent that then monitored clock source loses; If system adopts high level alarm mode, otherwise then;
(6) lose processing module when clock and realize that lose in arbitrary monitored clock source on the digital circuit board, then the warning information that will lose reports processing, and the startup clock recovery is handled, or outputting alarm information, prompting resets, detects, safeguards processing to digital circuit board, thereby realizes the monitoring to total system multipath clock source.
Embodiment four
As shown in Figure 9, similar to single channel high-frequency clock monitoring system, the high-frequency clock monitoring system of the digital circuit board of present embodiment four is to expand on the basis of high-frequency clock monitoring system of embodiment three digital circuit boards, adopted low-speed clock source frequency dividing circuit, the corresponding connection also distinguished by a plurality of low-speed clocks source frequency dividing circuit and each pulse shaping circuit, decision level generation module in the described low-speed clock source of stablizing and not losing.
As shown in Figure 9, similar to the single channel high speed clock monitoring method, when the high-frequency clock monitoring system of employing present embodiment four described digital circuit boards is carried out the monitoring of multipath high-speed clock, realize that by each described low-speed clock source frequency dividing circuit frequency division is carried out in the described clock source of stablizing and not losing to be handled, concrete frequency division multiple can be decided according to the minimum clock frequency on the described digital circuit board; Other courses of work are identical with the course of work of the high-frequency clock monitoring system of embodiment three described digital circuit boards.
As mentioned above; just can realize the utility model preferably; the foregoing description is the utility model preferred implementation; but embodiment of the present utility model is not restricted to the described embodiments; other any do not deviate from change, the modification done under spirit of the present utility model and the principle, substitutes, combination, simplify; all should be the substitute mode of equivalence, be included within the protection domain of the present utility model.
Claims (4)
1, a kind of high-frequency clock monitoring system of digital circuit board, be single channel clock monitoring system, it is characterized in that: comprise stable and low-speed clock source of not losing and pulse shaping circuit, decision level generation module, the loss of clock processing module that connects successively, described pulse shaping circuit is connected with monitored clock source on the digital circuit board, and described stable and low-speed clock source that do not lose is connected respectively with pulse shaping circuit, decision level generation module simultaneously; The described stable and frequency low-speed clock source of not losing is less than or equal to half of monitored clock source low-limit frequency on the digital circuit board.
2, according to the high-frequency clock monitoring system of the described a kind of digital circuit board of claim 1, it is characterized in that: the described low-speed clock source of stablizing and not losing also is connected respectively with pulse shaping circuit, decision level generation module by low-speed clock source frequency dividing circuit.
3, a kind of high-frequency clock monitoring system of digital circuit board, be the multipath clock monitoring system, it is characterized in that: comprise low-speed clock source, decision level processing module, loss of clock processing module and a plurality of mutual corresponding pulse shaping circuit, decision level generation module that connects stable and that do not lose, each pulse shaping circuit respectively with digital circuit board on each corresponding connection of monitored clock source, described stable and low-speed clock source that do not lose is connected respectively with each pulse shaping circuit, decision level generation module simultaneously; Each decision level generation module is connected with described decision level processing module, loss of clock processing module respectively, and the described stable and frequency low-speed clock source of not losing is less than or equal to half of monitored clock source low-limit frequency on the digital circuit board.
4, according to the high-frequency clock monitoring system of the described a kind of digital circuit board of claim 3, it is characterized in that: the corresponding connection also distinguished by a plurality of low-speed clocks source frequency dividing circuit and each pulse shaping circuit, decision level generation module in the described low-speed clock source of stablizing and not losing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200498144U CN201226112Y (en) | 2008-06-27 | 2008-06-27 | System for monitoring high speed clock of digital circuit board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200498144U CN201226112Y (en) | 2008-06-27 | 2008-06-27 | System for monitoring high speed clock of digital circuit board |
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| Publication Number | Publication Date |
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| CN201226112Y true CN201226112Y (en) | 2009-04-22 |
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| CNU2008200498144U Expired - Fee Related CN201226112Y (en) | 2008-06-27 | 2008-06-27 | System for monitoring high speed clock of digital circuit board |
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- 2008-06-27 CN CNU2008200498144U patent/CN201226112Y/en not_active Expired - Fee Related
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090422 Termination date: 20130627 |