CN201191856Y - RS-485 data transceiving device - Google Patents
RS-485 data transceiving device Download PDFInfo
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- CN201191856Y CN201191856Y CNU2008200807190U CN200820080719U CN201191856Y CN 201191856 Y CN201191856 Y CN 201191856Y CN U2008200807190 U CNU2008200807190 U CN U2008200807190U CN 200820080719 U CN200820080719 U CN 200820080719U CN 201191856 Y CN201191856 Y CN 201191856Y
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Abstract
The utility model provides a receiving and transmitting device of RS-485 data, which comprises a first 485 interface unit, a first data flow direction control unit, a data receiving and transmitting control unit and a logic unit, wherein the data transmitting end and the data receiving end of the first 485 interface unit are respectively connected with the input ends of the data receiving and transmitting control unit and the first data flow direction control unit, the output ends of the first data flow direction control unit and the data receiving and transmitting control unit are respectively connected with two input ends of the logic unit, and the output end of the logic unit is connected with the output enable end of the 485 interface unit. With the receiving and transmitting device, the RS-485 bus competition adventure can be avoided in the RS-485 network with multiple host computers.
Description
Technical Field
The utility model relates to a RS-485 network technology field especially indicates a RS-485 data transceiver.
Background
RS-485 is a data transmission bus conforming to the industrial communication standard, and is a standard asynchronous serial bus established by the American Electronic Industry Association (EIA) for balanced transmission and differential reception. RS-485 is half duplex interface, adopts two-way single channel communication mode.
In the RS-485 network, a master computer and a slave computer controlled by the master computer are directly connected to the RS-485 network. When only one host controls a plurality of slave machines, because a master/slave communication mode is adopted, each communication is initiated from the host machine, and the slave machines do not actively transmit data, the situation that more than two machines simultaneously transmit data on a network can not occur all the time, and the RS-485 bus competition risk can not occur. However, when a plurality of hosts are arranged in the RS-485 network, it is inevitable that two or more hosts initiate communication at the same time, that is, two or more hosts send data to the RS-485 network at the same time, which will cause the RS-485 bus to compete and risk.
SUMMERY OF THE UTILITY MODEL
In view of the above, the present invention is directed to an RS-485 data transceiver, which avoids the risk of RS-485 bus contention in an RS-485 network with multiple hosts.
The utility model provides a RS-485 data transceiver, include: the data transmission device comprises a first 485 interface unit, a first data flow direction control unit, a data receiving and transmitting control unit and a logic and unit, wherein a data transmitting end and a data receiving end of the first 485 interface unit are respectively connected with the data receiving and transmitting control unit and an input end of the first data flow direction control unit, output ends of the first data flow direction control unit and the data receiving and transmitting control unit are respectively connected with two input ends of the logic and unit, and an output end of the logic and unit is connected with an output enabling end of the 485 interface unit.
Optionally, the system further comprises a second 485 interface unit and a second flow direction control unit; the data sending end and the data receiving end of the second 485 interface unit are respectively connected with the data receiving end and the data sending end of the first 485 interface unit, and the second data flow direction control unit is connected between the data receiving end and the output enabling end of the second 485 interface unit in series.
Optionally, the first and second 485 interface units are MAX485 chips, and the data sending end and the data receiving end of the 485 interface unit are the receiver output end RO and the driver input end DI of the MAX485 chip.
Optionally, the data transceiving control unit is a retriggerable monostable trigger.
The retriggerable monostable flip-flop is an 74123 chip, and the input and output ends of the data transceiving control unit IC2 are the negative trigger input end a and the negative pulse output end Q of the 74123 chip.
Therefore, the RS-485 data transceiver of the utility model allows the data of the host to be transmitted to the RS-485 bus only when the RS-485 bus is idle, so that the RS-485 bus competition risk can be avoided in the RS-485 network with multiple hosts.
Moreover, the two ends of the RS-485 data transceiver can be set as 485 interfaces, and the RS-485 data transceiver can be conveniently installed between the equipment to be accessed to the RS-485 network and the RS-485 network.
The utility model discloses can adopt MAX485 chip and monostable trigger to be 74123 chips among the RS-485 data transceiver, the cost is lower.
Drawings
FIG. 1 is a schematic diagram of an RS-485 data transceiver;
FIG. 2 is a schematic diagram of 74123 chips;
FIG. 3 is a logic diagram of various interfaces of 74123 chips;
FIG. 4 is a schematic diagram of an RS-485 data transceiver device with RS-485 interfaces at both ends;
fig. 5 is a schematic diagram of the RS-485 data transceiver applied between the RS-485 network and the RS-485 network.
Detailed Description
The RS-485 data transceiver of the utility model is arranged between each host and the RS-485 bus, and is used for monitoring the RS-485 bus and controlling the data transmission and reception of the connected host, when the RS-485 bus is idle, the data from the host can be controlled to be output to the RS-485 bus through the RS-485 data transceiver; when the RS-485 bus has data, the RS-485 data transceiver shields the data transmitted by the connected host, so that only one host can transmit the data to the RS-485 bus when a plurality of hosts transmit the data at the same time on the RS-485 bus, and the RS-485 bus competition risk is avoided. The following describes the RS-485 data transceiver in detail.
Fig. 1 is the utility model discloses RS-485 data transceiver schematic diagram, including data receiving and dispatching the control unit IC2, 485 interface unit, data flow direction the control unit IC1, logic and unit IC3, wherein, first 485 interface unit's data sending end and data receiving terminal respectively with data receiving and dispatching the control unit, first data flow direction the control unit's input is connected, first data flow direction the control unit and data receiving and dispatching the control unit output are connected with logic and unit two inputs respectively, logic and unit output and 485 interface unit output enable end link to each other. The following first describes each unit of the present invention in detail:
the data transceiving control unit IC2 may be implemented by a dual triggerable monostable flip-flop, in this example, the IC2 employs 74123 chip, fig. 2 shows a schematic diagram of 74123 chip, and the meaning of each interface is as follows: CEXT is an external capacitor end; q is a positive pulse output end;is a negative pulse output end;
clear (active low); a1 and A2 are negative trigger input ends; b1 and B2 are positive trigger input ends. Fig. 3 shows a logic relationship diagram of each port of the input end and the output end, wherein H represents high level, L represents low level, X represents arbitrary level, upper and lower arrows represent transition from low level to high level and from high level to low level respectively, and convex and concave pulses represent high and low level pulses, as can be seen from fig. 3, when a1 inputs transition from high level to low level,
and outputting a low level. Here the 74123 chip uses a1 as an input,
as an output end, when a 74123 chip A1 end receives a high-to-low level jump signal of a DataO pin connected with an RO end of a MAX485 chip, the 74123 chip
And outputting a low level.
The 485 interface unit can adopt MAX485 chip, which comprises a receiver output enable end
And a driver output enable DE, which may be collectively referred to as an output enable. Wherein
Active low and active high DE.And DE short circuit, the MAX485 chip is controlled to receive or send two states according to the received control signal:
when DE is '1', data is input through a driver input end DI and output to an RS-485 bus through a receiver non-inverting input end/a driver non-inverting output end A and a receiver inverting input end/a driver inverting output end B;
and DE is "0", if there is data on the RS-485 bus, then input via A, B and output via receiver output RO. In this example, the RO and DI terminals of the MAX485 chip are used as the data transmitting terminal and the data receiving terminal of the 485 interface unit.
The data flow to control unit IC1 is connected between DI andbetween the terminals, signals are collected from a DataI pin connected with a DI terminal of the MAX485 chip and control signals are output. When DataI remains high, it is considered to be idle or receiving state and IC1 outputs low; when there is data on DataI, IC1 outputs a high level. The data flow control unit IC1 can adopt an automatic flow control circuit provided in chinese patent ZL200720005122.5, and the principle thereof is not described herein.
The working principle of the present invention is explained in detail below:
when the RS-485 bus is in an idle state, no data (shown in the condition that an A interface receives a signal of '1' and a B interface receives a signal of '0') exists on the RS-485 bus connected with the A, B interface, a DataI connected with the DI keeps high level, at the moment, the IC1 outputs low level, and therefore the logic AND unit IC3 outputs low level to the MAX485 chip
And a DE terminal for maintaining the MAX485 chip in receiving state, the DataO pin is consistent with the A port signal, and maintains high level, and a negative pulse output terminal of IC2And outputting a high level.
When data are input into the MAX485 chip on the RS-485 bus and the DataI connected with the DI is idle (the DataI keeps high level), the MAX485 chip is in a receiving state, the DataO connected with the output end RO of the receiver has data, the IC2 circuit is triggered, and the negative pulse output end
And a low level is output, the IC3 continuously outputs the low level, and the MAX485 chip keeps in a receiving state. The IC2 will be continuously triggered before the transmission of the continuous data packet on the RS-485 bus is finished, and the negative pulse output end
And a low level is always output, and the MAX485 chip always keeps a receiving state.
In the process, when data is input into the MAX485 chip, the MAX485 chip is kept in a receiving state, so that the data of the DataI is shielded and cannot be sent to the RS-485 bus, and therefore competition hazards cannot occur on the RS-485 bus, and the integrity of the bus data is guaranteed. When the continuous data packet of the RS-485 bus is sent, the negative pulse output end of the IC2
When the low level pulse is ended, the high level is recovered, the output end of the IC3 changes along with the output signal of the IC1, namely, the receiving and sending of the MAX485 chip are directly controlled by the IC1, and at the moment, when data exists in the DataI, the data can be transmitted to the RS-485 bus through the MAX485 chip.
When the RS-485 bus has no data and the DataI has data to be input into the DI port of the MAX485 chip, the DataO keeps high level, the IC1 collects a level signal from the DataI and outputs a control signal to switch on the output end of the MAX485 chip, and the DataI data is output to the RS-485 bus. The MAX485 chip is in a transmitting state until the end of the data I continuous data packet transmission. Because DataO remains high, the negative pulse output of IC2Output enable terminal for MAX485 chip capable of keeping high level
And DE is directly controlled by the IC1 output. When the DataI continuous data packet is over, the IC1 outputs a low level, and the MAX485 chip is switched to the receive state.
Wherein, the R and C values of the IC2 circuit can be controlled by adjusting
The pulse width tW of the output negative pulse. When C is not less than 1000pF, tW may be set to K · R · C, where K is a constant selected from 0.2 to 0.6 depending on the external temperature and the external capacitor C. When C ≦ 1000pF, tW may be set to 6+0.05C +0.45RC +11.6R, where the capacitance C is in pF and the resistance R is in k Ω in this equation.
FIG. 4 is an RS-485 data transceiver with 485 interfaces at both ends, as shown in FIG. 4, which is installed between the 485 interface and RS-485 bus of the host, and is different from the previous figure, and is further provided with a MAX485 chip connected with the DataI and DataO interfaces, wherein the MAX485 chip is packaged in standard, and the RO and DI thereof are connected with the DataI and DataO,And the DE interface is also connected with an automatic flow control unit, and the other end of the automatic flow control unit is connected with the DI of the MAX485 chip.
The utility model is shown in fig. 5, which shows an RS-485 network consisting of two master machines and two slave machines. The host computer and the RS-485 bus are connected through the RS-485 data receiving and transmitting device in the figure 4. The slave does not actively send data, and each communication is initiated from the master. At the beginning, the RS-485 bus is idle, namely, the two hosts and the two slaves do not transmit data, and at the moment, the RS-485 data transceiver I, the RS-485 data transceiver II and the 485 interface chips of the two slaves are in a receiving state.
At a certain moment, the host I starts to send data, the two slave machines receive the data, and the RS-485 data transceiver II receives the data at the same time, so that the sending end of the host II is shielded. And before the data of the host I is not sent, the RS-485 data transceiver II always receives the RS-485 bus data and continuously shields the sending end of the host II. And the RS-485 data transceiver II automatically removes the shielding of the sending end of the host II until the data sending of the host I is finished. In the process of sending data by the host I, the two slave machines return data after waiting for the end of data sending, so that the two slave machines do not send data; the host II can send data at any time, and the RS-485 data transceiver II detects that data shields the sending end of the host II on the RS-485 bus, so that only one station on the RS-485 bus, namely the host I sends the data, thereby avoiding competition hazards and ensuring the integrity of the data sent by the host I. And similarly, when the RS-485 bus is idle, in the primary communication process initiated by the host II, the RS-485 data transceiver I automatically shields the sending end of the host I, thereby avoiding the occurrence of competition hazards and ensuring the integrity of the data sent by the host II.
And after the slave computer receives the command of the host computer and returns data, the RS-485 data transceiver I and the RS-485 data transceiver II automatically shield the transmitting end. After the slave computer finishes transmitting, the RS-485 bus is idle, and the RS-485 data receiving and transmitting device I and the RS-485 data receiving and transmitting device II automatically remove the shielding of the transmitting end and wait for the next communication.
In fig. 5, the RS-485 data transceiver is connected only between the master and the RS-485 bus, and if the number of slaves is large, the RS-485 data transceiver is connected between the slaves and the RS-485 bus to prevent more than two slaves from transmitting data (for example, multiple slaves respond to the data of the master) at the same time, so that only one station on the RS-485 bus transmits data at the same time and other stations are in a receiving state.
It is from top to bottom visible, the utility model discloses when can realizing that the 485 network has many hosts, under idle state, do not shield the first host computer of sending data to before this host computer sending data finishes, shield the data that other host computers sent, thereby avoid appearing bus competition adventure.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. An RS-485 data transceiver device, comprising: a first 485 interface unit, a first data flow direction control unit, a data receiving and transmitting control unit, and a logic and unit,
the data sending end and the data receiving end of the first 485 interface unit are respectively connected with the input ends of the data receiving and sending control unit and the first data flow direction control unit, the output ends of the first data flow direction control unit and the data receiving and sending control unit are respectively connected with the two input ends of the logic and unit, and the output end of the logic and unit is connected with the output enabling end of the 485 interface unit.
2. The RS-485 data transceiver device according to claim 1, further comprising a second 485 interface unit and a second streaming control unit; wherein,
the data transmitting end and the data receiving end of the second 485 interface unit are respectively connected with the data receiving end and the data transmitting end of the first 485 interface unit, and the second data flow direction control unit is connected between the data receiving end and the output enabling end of the second 485 interface unit in series.
3. The RS-485 data transceiver of claim 1 or 2, wherein the first and second 485 interface units are MAX485 chips, and the data transmitting end and the data receiving end of the 485 interface unit are respectively the receiver output end RO and the driver input end DI of the MAX485 chip.
4. The RS-485 data transceiver of claim 3, wherein the data transceiver control unit is a retriggerable monostable trigger.
5. The RS-485 data transceiver of claim 4, wherein the retriggerable monostable flip-flop is 74123 chip, and the input and output of the data transceiver control unit IC2 are the negative trigger input A and the negative pulse output Q of 74123 chip, respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2008200807190U CN201191856Y (en) | 2008-05-21 | 2008-05-21 | RS-485 data transceiving device |
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| CNU2008200807190U CN201191856Y (en) | 2008-05-21 | 2008-05-21 | RS-485 data transceiving device |
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| CN201191856Y true CN201191856Y (en) | 2009-02-04 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102647268A (en) * | 2012-04-10 | 2012-08-22 | 河南汉威电子股份有限公司 | Semi-duplex communication transmitting-receiving control device and method thereof |
| CN103067202A (en) * | 2012-12-25 | 2013-04-24 | 卡斯柯信号有限公司 | Security arbitration voting system applicable to different calculation links |
| CN103746890A (en) * | 2013-06-09 | 2014-04-23 | 国家电网公司 | Competition model RS-485 bus multimaster communication system and working method thereof |
| CN103746889A (en) * | 2013-06-09 | 2014-04-23 | 国家电网公司 | Half-competition model RS-485 bus multimaster communication system and working method thereof |
| CN103869731A (en) * | 2014-02-26 | 2014-06-18 | 成都信息工程学院 | Asynchronous serial communication-based multi-master nondestructive bus contention circuit |
| CN105743581A (en) * | 2016-04-15 | 2016-07-06 | 中国人民解放军65711部队 | Anti-interference high-speed differential isolation data asynchronous communication module |
| CN110855316A (en) * | 2019-10-25 | 2020-02-28 | 天津航空机电有限公司 | RS485 automatic receiving and transmitting isolation circuit |
| CN110943900A (en) * | 2019-10-25 | 2020-03-31 | 福建和盛高科技产业有限公司 | Carrier monitoring multi-access RS485 bus circuit with collision detection and method |
| CN111324559A (en) * | 2020-02-27 | 2020-06-23 | 南通琅润达大数据科技有限公司 | Serial port shunting device with independent request |
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2008
- 2008-05-21 CN CNU2008200807190U patent/CN201191856Y/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102647268B (en) * | 2012-04-10 | 2015-08-12 | 河南汉威电子股份有限公司 | Semi-duplex communication transmitting-receivicontrol control device and method thereof |
| CN102647268A (en) * | 2012-04-10 | 2012-08-22 | 河南汉威电子股份有限公司 | Semi-duplex communication transmitting-receiving control device and method thereof |
| CN103067202A (en) * | 2012-12-25 | 2013-04-24 | 卡斯柯信号有限公司 | Security arbitration voting system applicable to different calculation links |
| CN103067202B (en) * | 2012-12-25 | 2016-05-04 | 卡斯柯信号有限公司 | Be applicable to the safety arbitration voting system between nonidentity operation link |
| CN103746889A (en) * | 2013-06-09 | 2014-04-23 | 国家电网公司 | Half-competition model RS-485 bus multimaster communication system and working method thereof |
| CN103746890A (en) * | 2013-06-09 | 2014-04-23 | 国家电网公司 | Competition model RS-485 bus multimaster communication system and working method thereof |
| CN103746890B (en) * | 2013-06-09 | 2018-05-18 | 国家电网公司 | Competitive mode RS-485 bus multi-master communication systems and its method of work |
| CN103746889B (en) * | 2013-06-09 | 2018-11-16 | 国家电网公司 | Half competitive mode RS-485 bus multi-master communication system and its working method |
| CN103869731A (en) * | 2014-02-26 | 2014-06-18 | 成都信息工程学院 | Asynchronous serial communication-based multi-master nondestructive bus contention circuit |
| CN105743581A (en) * | 2016-04-15 | 2016-07-06 | 中国人民解放军65711部队 | Anti-interference high-speed differential isolation data asynchronous communication module |
| CN110855316A (en) * | 2019-10-25 | 2020-02-28 | 天津航空机电有限公司 | RS485 automatic receiving and transmitting isolation circuit |
| CN110943900A (en) * | 2019-10-25 | 2020-03-31 | 福建和盛高科技产业有限公司 | Carrier monitoring multi-access RS485 bus circuit with collision detection and method |
| CN110855316B (en) * | 2019-10-25 | 2021-07-16 | 天津航空机电有限公司 | RS485 automatic receiving and transmitting isolation circuit |
| CN110943900B (en) * | 2019-10-25 | 2021-12-17 | 福建和盛高科技产业有限公司 | Carrier monitoring multi-access RS485 bus circuit with collision detection and method |
| CN111324559A (en) * | 2020-02-27 | 2020-06-23 | 南通琅润达大数据科技有限公司 | Serial port shunting device with independent request |
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