CN103746889A - Half-competition model RS-485 bus multimaster communication system and working method thereof - Google Patents
Half-competition model RS-485 bus multimaster communication system and working method thereof Download PDFInfo
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Abstract
A half-competition model RS-485 bus multimaster communication system relates to a communication system. According to an RS-485 bus scheme at present, once a conflict occurs, competition needs to be carried out again. The half-competition mode RS-485 bus multimaster communication system of the present invention is characterized in that a master node is connected with a bus via a first interface chip, and each slave node is connected with the bus via a second interface chip and is equipped with an XNOR gate circuit, a double-path D-type rising edge trigger and an XOR gate circuit; the output end of the XOR gate circuit and a slave node receiving signal end are connected with the second interface chip, a first resistor is arranged between the second interface chip and the anode of a power supply, and a second resistor is arranged between the second interface chip and a grounding end; a sending signal end and a receiving signal end of the master node are connected with the first interface chip directly, and the first interface chip is connected with the power supply via a pull-up resistor and is grounded via a pull-down resistor. The half-competition mode RS-485 bus multimaster communication system and the working method thereof of the present invention are based on the hardware, monitor and receive the sent data, and are stable in work, high in reliability and faster in speed.
Description
Technical field
The present invention relates to a communication system.
Background technology
In traditional RS-485 bus, there is a host node, and multiple from node.Its course of work as shown in Figure 1, always initiated by host node by communication, from node receives orders, obtains bus control right, then to transmission information in bus.After transmission finishes, bus control right returns to again host node.From node, only when the host node inquiry, could send data, therefore can not transmit the emergency datas such as alarm; From can not intercommunication between node, can only pass through host node transfer, affect speed; For improving the speed from node, the real-time of raising system, automation scientific and engineering institute of Guangzhou South China Science & Engineering University has proposed a kind of scheme of the how main RS-485 bus that realizes the access/collision detection of carrier sense multiple spot, and by software mode, its workflow as shown in Figure 2, the corresponding data transmission bauds that improved, but it can only detect bus collision, can not initiatively dodge, once there is conflict, Communications failure, need compete again.
Summary of the invention
The technical assignment of the technical problem to be solved in the present invention and proposition is that prior art scheme is improved and improved, half competitive mode RS-485 bus multi-master communication system and method for work thereof is provided, to realize the information mutual communication that gets final product between many host nodes, improve the object of communication speed.For this reason, the present invention takes following technical scheme.
Half competitive mode RS-485 bus multi-master communication system, comprise the host node be located in bus and multiple from node, it is characterized in that: described host node is connected with bus by first interface chip, described is connected with bus by the second interface chip from node, described is provided with input and receives from node transmitted signal end and from node the same OR circuit that signal end is connected from node, the two-way D type rising edge trigger being connected with same OR circuit output, input and two-way D type rising edge trigger output and the OR circuit being connected from node transmitted signal end, OR circuit output, from node, receiving signal end is connected with the second interface chip, between the cathode output end of the second interface chip and positive source, establish the first resistance, between the cathode output end of the second interface chip and earth terminal, establish the second resistance, transmitted signal end, the reception signal end of described host node are directly connected with first interface chip, the reception signal pins of first interface chip is joined by pull-up resistor and power supply, and the reception of first interface chip and transmission Enable Pin pin are by pull down resistor ground connection.From the transmitted signal end of node with receive the signal end signal consequential signal of competing through same OR circuit after, when identical, competition results signal be high, represents to send successfully, during difference, competition results signal is low, expression sends unsuccessfully; When competition results signal is while being low, the output of two-way D type rising edge trigger is set to 1, is output as 1, the second interface chip and stops sending data after OR circuit; When bus is during in idle condition, from node transmitted signal end and reception signal end, be height, competition results signal is high, processor sends data from the transmitted signal end of node, at first trailing edge, two-way D type rising edge trigger is output as 0, now or door output by transmitted signal end signal, determined, when transmitted signal end signal is 0, the second interface chip is to bus output 0, when transmitted signal end signal is 1, the second interface chip is in accepting state, and bus is maintained 1 state by the first resistance and the second resistance.In bus contention process, due to multiple, from node, to bus, send data simultaneously, when having " 0 ", " 1 " simultaneously, can produce conflict, can cause from node interface and damage, when serious, can cause bus paralysis, for avoiding bus collision, adopt the similar Lou mode of output of opening when node interface designs, from node interface, only to bus, export " 0 " signal, " 1 " signal keeps by first, second resistance mating in bus, with this, avoids from internodal data collision.Pull down resistor guarantee first interface chip when idle condition in accepting state, discharge bus control right, can receive data from bus, simultaneously when needs send data to bus, by first interface chip enable end is drawn high, make first interface chip in transmission state, can send data to bus, now, first interface chip does not receive the data in bus, pull-up resistor is guaranteed to receive signal and is always high level, for without data mode.When host node with from node, send while conflict, each node has the retransmission mechanism of makeing mistakes, and detects to conflict exit transmission from node, host node sends because detecting conflict always, until send successfully.Owing to thering is monitor function from node, host node is had precedence over from node, and adopt competition mechanism between node.Guaranteeing, under the preferential prerequisite of host node, to improve the transmission speed from node.The present invention sets about from hardware, and sent data are carried out to monitoring reception, and working stability, reliability are high, and speed is faster.
As the further of technique scheme improved and supplemented, the present invention also comprises following additional technical feature.
From node transmitted signal end, after not circuit, be connected with the CLK pin of two-way D type rising edge trigger.
Half competitive mode RS-485 bus multi-master communication system works method, is characterized in that comprising the following steps:
1) allly in bus from node, monitor all the time bus, when data in bus exceed break period, set the byte transmission time, think that bus is in idle condition, what now need to send data starts competition bus from node; When bus is busy, the node that need to send data was waited for until the bus free time;
2) during competition bus, what send data first sends address information to bus from node, and and take position as unit carries out hardware conflicts detection, if when synchronization has " 1 " " 0 " to send conflict, bus only sends " 0 " signal, what send data monitors from node the data that bus is transmitted, if different from sent data,, for to compete unsuccessfully, exit competition, stop sending;
3) competition successfully obtains general line control from node, can start to send data, if the Transmission time exceedes the byte of setting, discharges bus;
4) when host node with from node, send while conflict, from node, have the retransmission mechanism of makeing mistakes, from node, detect that conflict exits transmission, host node sends because detecting conflict always, until send successfully, assurance host node preferentially sends data, without time delay, retransmits.And in native system, adopt hardware conflicts detection mode, and take position, be unit, once produce conflict, a side of failure exits automatically, a side of controlled power can continue to send data, guarantees that this secondary data correctly sends.Therefore, native system has more direct collision detection and escape mechanism, and guarantees that host node can preferentially send data simultaneously, without delayed retransmission.
Beneficial effect: the technical program is by the improvement to RS-485 control mode, realized information mutual communication instant between many host nodes, control mode is simple and reliable, avoided from internodal bus collision, having very high practical is worth, guaranteeing, under the preferential prerequisite of host node, to improve the transmission speed from node.
Accompanying drawing explanation
Fig. 1 is existing RS-485 communication flow figure.
Fig. 2 is existing tool monitor function RS-485 workflow diagram.
Fig. 3 is bus structures figure of the present invention.
Fig. 4 is that the present invention is from node circuit principle assumption diagram.
Fig. 5 is host node circuit principle structure figure of the present invention.
Embodiment
Below in conjunction with Figure of description, technical scheme of the present invention is described in further detail.
As Fig. 3, 4, shown in 5, the present invention includes the host node be located in bus and multiple from node, described host node is connected with bus by first interface chip U0, described is connected with bus by the second interface chip U2 from node, described is provided with input and receives from node transmitted signal end TXD and from node the same OR circuit U4 that signal end RXD is connected from node, the two-way D type rising edge trigger U3A being connected with same OR circuit U4 output, the OR circuit U1 that input is connected with two-way D type rising edge trigger U3A output and from node transmitted signal end TXD, OR circuit U1 output, from node, receiving signal end RXD is connected with the second interface chip U2, between the cathode output end of the second interface chip U2 and positive source, establish the first resistance R 2, between the cathode output end of the second interface chip U2 and earth terminal, establish the second resistance R 3, transmitted signal end TXD, the reception signal end RXD of described host node are directly connected with first interface chip U0, the reception signal pins RO of first interface chip joins by pull-up resistor R1 and power supply, and Enable Pin pin/RE, the DE of the reception of first interface chip and transmission is by pull down resistor R0 ground connection.From node transmitted signal end TXD, after not circuit U5, be connected with the CLK pin of two-way D type rising edge trigger U3A.From the transmitted signal end TXD and reception signal and the consequential signal FAIL that competes after same OR circuit U4 of node, when identical, competition results signal FAIL is high, represents to send successfully, and when different, competition results signal FAIL is low, and expression sends unsuccessfully, when competition results signal FAIL is while being low, two-way D type rising edge trigger U3A output is set to 1, is output as 1, the second interface chip U2 and stops sending data after OR circuit U1, when bus is during in idle condition, from node transmitted signal end TXD and reception signal end RXD, be height, competition results signal FAIL is high, processor sends data from the transmitted signal end TXD of node, at first trailing edge, two-way D type rising edge trigger U3A is output as 0, now or door output by transmitted signal end TXD signal deciding, when transmitted signal end TXD signal is 0, the second interface chip U2 is to bus output 0, when transmitted signal end TXD signal is 1, the second interface chip U2 is in accepting state, bus maintains 1 by the first resistance R 2 and the second resistance R 3.Pull down resistor R2 guarantee first interface chip U1 when idle condition in accepting state, discharge bus control right, simultaneously can receive data from bus.When needs send data to bus, by DIR is drawn high, make first interface chip U1 in transmission state, can send data to bus.Now, first interface chip U1 does not receive the data in bus, and pull-up resistor R1 guarantees to receive signal RXD and is always high level, for without data mode.
Half competitive mode RS-485 bus multi-master communication system control method, comprises the following steps:
1) allly in bus from node, monitor all the time bus, when data in bus exceed break period, set the byte transmission time, think that bus is in idle condition, what now need to send data starts competition bus from node; When bus is busy, the node that need to send data was waited for until the bus free time;
2) during competition bus, what send data first sends address information to bus from node, and and take position as unit carries out hardware conflicts detection, if synchronization has " 1 " " 0 " to send when conflict, bus only sends " 0 " signal, what send data monitors from node the data that bus is transmitted, if, different from sent data, for to compete unsuccessfully, exit competition, stop sending;
3) competition successfully obtains general line control from node, can start to send data, if the Transmission time exceedes the byte of setting, discharges bus;
4) when host node with from node, send while conflict, from node, have the retransmission mechanism of makeing mistakes, from node, detect to conflict and exit transmission, host node sends because detecting conflict always, until send successfully, guarantee that host node preferentially sends data, without time delay, retransmit.
Half competitive mode RS-485 bus multi-master communication system and method for work thereof shown in above Fig. 3,4,5 are specific embodiments of the invention; the outstanding substantive distinguishing features of the present invention and marked improvement have been embodied; can be according to actual use needs; under enlightenment of the present invention; it is carried out to the equivalent modifications of the aspects such as shape, structure, all at the row of the protection range of this programme.
Claims (4)
1. half competitive mode RS-485 bus multi-master communication system, comprise the host node be located in bus and multiple from node, it is characterized in that: described host node is connected with bus by first interface chip U0, described is connected with bus by the second interface chip (U2) from node, described is provided with input and receives from node transmitted signal end (TXD) and from node the same OR circuit (U4) that signal end (RXD) is connected from node, the two-way D type rising edge trigger (U3A) being connected with same OR circuit (U4) output, input and two-way D type rising edge trigger (U3A) output and the OR circuit (U1) being connected from node transmitted signal end (TXD), OR circuit (U1) output, from node, receiving signal end (RXD) is connected with the second interface chip (U2), between the cathode output end of the second interface chip (U2) and positive source, establish the first resistance (R2), between the cathode output end of the second interface chip (U2) and earth terminal, establish the second resistance (R3), transmitted signal end (TXD), the reception signal end (RXD) of described host node are directly connected with first interface chip (U0), the reception signal pins (RO) of first interface chip is joined by pull-up resistor (R1) and power supply, and the reception of first interface chip (U1) and transmission Enable Pin pin (/RE, DE) are by pull down resistor (R0) ground connection.
2. half competitive mode RS-485 bus multi-master communication system according to claim 1, is characterized in that: from node transmitted signal end (TXD), after not circuit (U5), be connected with the CLK pin of two-way D type rising edge trigger (U3A).
3. the half competitive mode RS-485 bus multi-master communication method of work that adopts half competitive mode RS-485 bus multi-master communication system claimed in claim 1, is characterized in that comprising the following steps:
1) allly in bus from node, monitor all the time bus, when data in bus exceed break period, set the byte transmission time, think that bus is in idle condition, what now need to send data starts competition bus from node; When bus is busy, the node that need to send data was waited for until the bus free time;
2) during competition bus, what send data first sends address information to bus from node, and and take position as unit carries out hardware conflicts detection, if synchronization has " 1 " " 0 " to send when conflict, bus only sends " 0 " signal, what send data monitors from node the data that bus is transmitted, if, different from sent data, for to compete unsuccessfully, exit competition, stop sending;
3) competition successfully obtains general line control from node, can start to send data, if the Transmission time exceedes the byte of setting, discharges bus;
4) when host node with from node, send while conflict, from node, have the retransmission mechanism of makeing mistakes, from node, detect that conflict exits transmission, host node sends because detecting conflict always, until send successfully, assurance host node preferentially sends data, without time delay, retransmits.
4. half competitive mode RS-485 bus multi-master communication method of work according to claim 3, it is characterized in that: from the transmitted signal end (TXD) of node with receive signal end (RXD) the signal consequential signal (FAIL) of competing after same OR circuit (U4), when identical, competition results signal (FAIL) is high, represent to send successfully, when different, competition results signal (FAIL) is low, represents to send unsuccessfully, when competition results signal (FAIL) is while being low, two-way D type rising edge trigger (U3A) output is set to 1, is output as 1, the second interface chip (U2) and stops sending data after OR circuit (U1), when bus is during in idle condition, from node transmitted signal end (TXD) and reception signal end (RXD), be height, competition results signal (FAIL) is high, processor sends data from the transmitted signal end (TXD) of node, at first trailing edge, two-way D type rising edge trigger (U3A) is output as 0, now or door output by transmitted signal end (TXD) signal deciding, when transmitted signal end (TXD) signal is 0, the second interface chip (U2) is to bus output 0, when transmitted signal end (TXD) signal is 1, the second interface chip (U2) is in accepting state, bus maintains 1 state by the first resistance (R2) and the second resistance (R3).
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| CN104135411A (en) * | 2014-07-08 | 2014-11-05 | 深圳市瑞艾特科技有限公司 | Device and method of implementing multi-node communication based on RS232 interface |
| CN104184638A (en) * | 2014-09-15 | 2014-12-03 | 万高(杭州)科技有限公司 | Conflict prevention method, interface chip and communication network of RS-485 bus |
| CN105354159A (en) * | 2015-09-28 | 2016-02-24 | 上海海视电子有限公司 | RS485 distributed bus system based control method |
| CN107171917A (en) * | 2017-04-07 | 2017-09-15 | 惠州市天泽盈丰物联网科技股份有限公司 | A kind of network based on RS485 bus dilatations |
| CN107171921A (en) * | 2017-04-07 | 2017-09-15 | 惠州市天泽盈丰物联网科技股份有限公司 | A kind of real-time communication method based on RS485 networks |
| CN113395187A (en) * | 2021-05-27 | 2021-09-14 | 深圳市常工电子计算机有限公司 | 485 bus based communication enhancement method and system |
| CN114124613A (en) * | 2021-11-22 | 2022-03-01 | 江苏科技大学 | Anti-competition industrial 485 networking system and control method thereof |
| CN114374579A (en) * | 2022-01-14 | 2022-04-19 | 宁波迦南智能电气股份有限公司 | RS485 bus competition type communication method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104135411A (en) * | 2014-07-08 | 2014-11-05 | 深圳市瑞艾特科技有限公司 | Device and method of implementing multi-node communication based on RS232 interface |
| CN104184638A (en) * | 2014-09-15 | 2014-12-03 | 万高(杭州)科技有限公司 | Conflict prevention method, interface chip and communication network of RS-485 bus |
| CN104184638B (en) * | 2014-09-15 | 2018-02-13 | 杭州万高科技股份有限公司 | The bus anti-collision methods of RS 485, interface chip and its communication network |
| CN105354159A (en) * | 2015-09-28 | 2016-02-24 | 上海海视电子有限公司 | RS485 distributed bus system based control method |
| CN107171917A (en) * | 2017-04-07 | 2017-09-15 | 惠州市天泽盈丰物联网科技股份有限公司 | A kind of network based on RS485 bus dilatations |
| CN107171921A (en) * | 2017-04-07 | 2017-09-15 | 惠州市天泽盈丰物联网科技股份有限公司 | A kind of real-time communication method based on RS485 networks |
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| CN107171917B (en) * | 2017-04-07 | 2020-11-03 | 惠州市天泽盈丰物联网科技股份有限公司 | RS485 bus capacity expansion-based network |
| CN113395187A (en) * | 2021-05-27 | 2021-09-14 | 深圳市常工电子计算机有限公司 | 485 bus based communication enhancement method and system |
| CN114124613A (en) * | 2021-11-22 | 2022-03-01 | 江苏科技大学 | Anti-competition industrial 485 networking system and control method thereof |
| CN114124613B (en) * | 2021-11-22 | 2023-11-21 | 江苏科技大学 | Industrial 485 networking system capable of preventing competition and control method thereof |
| CN114374579A (en) * | 2022-01-14 | 2022-04-19 | 宁波迦南智能电气股份有限公司 | RS485 bus competition type communication method |
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