CN201134025Y - Impact measurement control instrument adopting DSP - Google Patents
Impact measurement control instrument adopting DSP Download PDFInfo
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- CN201134025Y CN201134025Y CNU200720303320XU CN200720303320U CN201134025Y CN 201134025 Y CN201134025 Y CN 201134025Y CN U200720303320X U CNU200720303320X U CN U200720303320XU CN 200720303320 U CN200720303320 U CN 200720303320U CN 201134025 Y CN201134025 Y CN 201134025Y
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Abstract
The utility model discloses an impulse measurement controller which uses DSP. A PC interface processing circuit is connected with a PC by an interface; a DSP data processing circuit is respectively connected with the PC interface processing circuit and a programmed logic circuit by corresponding data buses; a programmed logic processing circuit is connected with an analog to digital conversion circuit and a digital I / O circuit by corresponding digital signal lead wires; the analog to digital conversion circuit is connected with an analog input conditioning circuit by analog signal input lead wires; and a power supply circuit provides direct current power supply for each circuit module. The impulse measurement controller provided by the utility model has powerful processing ability, high precision, strong realtime control and is easy for realizing hardware expansion. Based on shared bus resources, information calculation treatment and hardware control resources can be optimized through coordination treatment processed on a digital processor DSP and a programmable logic device by a DSP external bus. The impulse measurement controller of the utility model is particularly used for such fields as impulse measurement control, impact and collision experiments, transient impulse measurement analysis and bounce machine and collision platform control, etc.
Description
Technical field
The utility model relates to the shock measurement controller, especially relates to the shock measurement controller of a kind of DSP of employing.
Background technology
Along with improving constantly to the requirements such as dynamic property, reliability and environmental suitability of structure and product, promoted the development of shock measurement control, impact experiment, transient impact Measurement and analysis and art such as shock testing machine and collision stage control greatly, also the performance of impact Measurement and analysis equipment has proposed more and more higher requirement simultaneously: except the good precision of impact signal Measurement and analysis; Impact is measured the response speed of handling, and real-time is also had higher requirement; Simultaneously, because traditional impact signal is measured and the control of shock testing machine realizes jointly by two separate equipment of shock measurement analytical equipment and impact opertaing device, cooperation between its equipment, coordination have had a strong impact on the operability of total system, for this reason, under the prerequisite of integrated at instrument, the intelligent trend that has become development, people are impact Measurement and analysis equipment and the design integration that impacts opertaing device and intelligently proposed urgent requirement also.
At the aspect of performance that shock measurement is analyzed, at present, be that basic framework is realized with microcomputer, D/A converting circuit and software mainly with embedded processor, D/A converting circuit and software or employing.
In two kinds of above-mentioned frameworks, the function of system---computing of impact information and realization are to comprising other peripheral circuit hardware controls management of D/A converting circuit---all realizes via embedded processor or microcomputer.Obviously, for the former, internal resource that embedded processor is limited and hardware controls resource will limit the room for promotion of performances such as its computational accuracy and speed greatly, this hardware structure of event can not fully satisfy the application requirements in each field of shock measurement, especially fast, the high fields of response processing requirements of this impacts such as impact experiment and transient impact Measurement and analysis.Simultaneously, owing to have the unified relation of contradiction in the resources allocation of computing and hardware controls management, distributing rationally of its resource also has influence on the raising of impact signal handling property and the extensibility of hardware to a certain extent.Though, improve the performance of embedded processor in theory, can improve the handling property of system to a certain extent,, being practically limited to design and manufacturing technology of embedded processor own and cost performance, this lifting also is very limited.For the latter, though the resource of microcomputer is relatively sufficient, can realize the high processing precision, it is very limited that but the running characteristic of microsystem improves its performance on the shock response processing speed, can not fully satisfy the application requirements in fields such as impact experiment and transient impact Measurement and analysis.
And the shock measurement control instrument integrated and intelligent aspect, development along with manufacturing technology such as electronics is integrated, people have begun integrated, the control intelligentized design of impact Measurement and analysis equipment and impact opertaing device and have attempted, but also do not have comparatively ripe scheme.
Summary of the invention
Big in order to solve the existing impact signal measuring relative errors of background technology, it is not strong to handle real-time, and hardware controls lacks in ability, and is difficult to fully satisfy the application requirements in fields such as shock measurement control, impact experiment and transient impact Measurement and analysis; The purpose of this utility model is to provide very strength reason ability, and the precision height is real-time, is easy to realize the shock measurement controller of a kind of DSP of employing of high-performance of hardware expanding.
The technical scheme that its technical matters that solves the utility model adopts is:
The utility model comprises PC interface treatment circuit, DSP data processing circuit, FPGA (Field Programmable Gate Array) treatment circuit, analog to digital conversion circuit, digital I/O circuit, analog input modulate circuit and feed circuit.Wherein PC interface treatment circuit is connected with PC by interface, the DSP data processing circuit is connected by corresponding data bus respectively with PC interface treatment circuit, Programmable Logic Device, the FPGA (Field Programmable Gate Array) treatment circuit is connected with digital I/O circuit with analog to digital conversion circuit respectively by the digital signal corresponding extension line, analog to digital conversion circuit is connected with the analog input modulate circuit by simulating signal input extension line, and feed circuit provide direct supply for each circuit module.
The data bus that the DSP data processing circuit is connected with PC interface treatment circuit is the HPI data bus; The DSP data processing chip that described DSP data processing circuit adopts is 32 floating type DSP data processing chips.
The data bus that the FPGA (Field Programmable Gate Array) treatment circuit is connected with the DSP data processing circuit is an external data bus, and the programmable logic chip that described FPGA (Field Programmable Gate Array) treatment circuit adopts is the SPARTAN3E family chip of XILIINX.
The modulus conversion chip that described analog to digital conversion circuit adopts is the modulus conversion chip of the highest 1.25MHz of resolution 16Bit, inversion frequency.
The digital signal extension line that described digital I/O circuit is connected with the FPGA (Field Programmable Gate Array) treatment circuit is the I/O control line.
The interface that described PC interface treatment circuit is connected with PC is the USB2.0 interface.
Described analog input modulate circuit comprises analog differential input signal conditioning circuit, voltage follower circuit, single-ended signal slip sub-signal circuit and anti-aliasing filter circuit, and it is low noise, high-precision OPA132 and TLE072 series that the conditioning chip is amplified in its computing of adopting.
Described feed circuit (8) comprise+1V produce circuit ,+1.2V produce circuit ,+1.4V produce circuit ,+2.5V produce circuit ,+3.3V produce circuit ,+4V produce circuit ,+5V produce circuit ,+12V produce circuit ,-5V produce circuit and-12V produces circuit; Its conversion chip that adopts is TPS54310, TPS70302, TPS5430, OPA2343, LP3962-2.5, LM340T-12, LM7905 and LM7912.
The utility model is used to realize the PC interface treatment circuit with the PC message exchange, the DSP data processing circuit that is used for digital information processing, be used to produce logic control signal and realize the pretreated FPGA (Field Programmable Gate Array) treatment circuit of information calculations, analog information is realized the analog to digital conversion circuit of numerical information conversion, carry out the digital I/O circuit of interface with external impact platform or collision stage, analog input signal is carried out the simulating signal of simulation process and import modulate circuit, the feed circuit of providing power supply to support for each circuit module.Wherein, the DSP data processing circuit is connected by external bus respectively with Programmable Logic Device, and the DSP data processing chip of employing is 32 floating type DSP data processing chips; The FPGA (Field Programmable Gate Array) treatment circuit is connected with analog to digital conversion circuit by the digital signal extension line, and the modulus conversion chip that analog to digital conversion circuit adopts is the modulus conversion chip of the highest 1.25MHz of resolution 16Bit, inversion frequency; The FPGA (Field Programmable Gate Array) treatment circuit also is connected with digital I/O circuit by the I/O control line.
The utility model creatively adopts DSP data processing circuit and Programmable Logic Device to realize the hard core control of shock measurement jointly: Programmable Logic Device can directly realize control of peripheral hardware resource and information calculations pre-service, make data processor DSP can bring into play the ability of its processing data information more fully, DSP data processing circuit and program logic circuit are carried out Coordination Treatment via the external bus of DSP, make control information computing and hardware controls resources allocation optimization.Simultaneously, configuration resolution 16bit, conversion ratio are up to the analog to digital conversion circuit of 1.25MHZ, simulating signal can be imported the analog information of modulate circuit input and carry out accurately instant conversion, calculate and control and treatment to offer DSP data processing circuit and Programmable Logic Device, its precision of information and processing real-time significantly improve.
The Programmable Technology of programmable logic device (PLD) that also creatively adopts the utility model realizes that shock measurement, control are integrated, intelligent: the digital I/O circuit that carries out interface with external impact platform or collision stage with the various digital state information feedback of external impact testing equipment to Programmable Logic Device, utilize the Programmable Technology of Programmable Logic Device, realization is to the processing of the status information of outside impact test equipment, again via digital I/O circuit to the controlling of outside impact test equipment, thereby realize that shock measurement, control are integrated and intelligent.
In addition, the utility model under the support of software, thereby can realize that field-programmable is controlled and the real-time demonstration of external impact information also by the management of PC interface treatment circuit realization to message exchange between DSP data processing circuit and the PC.
As preferably, the data bus that the FPGA (Field Programmable Gate Array) treatment circuit is connected on the DSP data processing circuit is an external bus.
Compared with prior art, the beneficial effect that the utlity model has:
1. combine digital processing unit DSP, programmable logic device (PLD) and high speed and precision modulus conversion chip.On the basis of the hardware controls of programmable logic device (PLD), by modulus conversion chip external information is gathered immediately accurately, carry out Signal Pretreatment via programmable logic device (PLD), cooperate the powerful data in real time processing power of digital processing unit DSP, the precision of information and the real-time of processing have been improved greatly, by the software algorithm support, can fully satisfy the application requirements in fields such as impact experiment and transient impact Measurement and analysis.
2. made full use of the Programmable Technology of programmable logic device (PLD).On the online programmable basis of programmable logic device (PLD), by control and treatment to the various digital state information of outside impact test equipment, the impact testing equipment carries out Based Intelligent Control, thereby realize shock measurement, impact the integrated and intelligent of control, fully satisfied the application requirements in shock measurement control field.The hardware controls ability of programmable logic device (PLD) is strong simultaneously, is easy to realize the expansion of hardware.
3. on the basis of shared bus resource, digital processing unit DSP and programmable logic device (PLD) are carried out Coordination Treatment, information calculations is handled and the hardware controls resources optimization by the DSP external bus.
4. rational in infrastructure, low cost of manufacture.
The utility model is specially adapted to shock measurement control, impact experiment, transient impact Measurement and analysis and fields such as shock testing machine and collision stage control
Description of drawings
Fig. 1 is a theory structure block diagram of the present utility model;
Fig. 2 is the structural drawing of the PC interface treatment circuit in the utility model.
Fig. 3 is the structural drawing of the DSP data processing circuit in the utility model;
Fig. 4 is the structural drawing of the FPGA (Field Programmable Gate Array) treatment circuit in the utility model;
Fig. 5 is the structural drawing of the analog to digital conversion circuit in the utility model;
Fig. 6 is the structural drawing of the digital I/O circuit in the utility model;
Fig. 7 is the structural drawing of the analog input modulate circuit in the utility model
Fig. 8 is the structural drawing of the feed circuit in the utility model;
Embodiment
Below by embodiment, and in conjunction with the accompanying drawings, the technical solution of the utility model is described in further detail.
As shown in Figure 1, a kind of shock measurement controller that adopts DSP comprises PC interface treatment circuit 1, DSP data processing circuit 2, FPGA (Field Programmable Gate Array) treatment circuit 3, analog to digital conversion circuit 4, digital I/O circuit 5, analog input modulate circuit 6 and feed circuit 7.The DSP data processing circuit is connected by HPI data bus, external bus respectively with PC interface treatment circuit, Programmable Logic Device, the FPGA (Field Programmable Gate Array) treatment circuit is connected with analog to digital conversion circuit, digital I/O circuit respectively by digital signal extension line, I/O control line, analog to digital conversion circuit is connected with the analog input modulate circuit by simulating signal input extension line, and feed circuit provide direct supply for each circuit module.
The course of work: under the hardware controls management of FPGA (Field Programmable Gate Array) treatment circuit, the analog input modulate circuit
Outside shock simulation information is gathered, nursed one's health, simulating signal is realized the digital signal conversion, and offer the FPGA (Field Programmable Gate Array) treatment circuit and carry out pre-service by analog to digital conversion circuit; The digital I/O circuit that carries out interface with external impact platform or collision stage then directly feeds back to Programmable Logic Device with the various digital state information of external impact testing equipment, and utilize its Programmable Technology, realize processing to the status information of outside impact test equipment.In the data message after handling through Programmable Logic Device, the data message of its outer external impact is transferred to the DSP data processing circuit by external bus, carries out the further computing of shock measurement; The status information of external impact testing equipment is then directly exported outside impact test equipment via digital I/O circuit, realizes its control.Simultaneously, under the management of PC interface treatment circuit, realize the message exchange between DSP data processing circuit and the PC, be aided with the support of software, thereby realize the real-time demonstration of field-programmable control and external impact information.
As shown in Figure 2, PC interface treatment circuit 1: comprise interface management chip U302, active crystal oscillator Z300.The interface management chip is mainly realized data message under the HPI data bus protocol framework and the USB2.0 of PC are communicated.Wherein active crystal oscillator provides clock frequency to managing chip.
The signal wire that PC interface treatment circuit 1 links to each other with DSP data processing circuit 2 has:
1.HPI data bus: HD[0:15]
2.HPI control line: HCNT[0:1], HCS, HDS, HRDY, HRW, HHWIL;
3.HPI interrupt line: HINT;
4.DSPREST, provide dsp processor to reset;
As shown in Figure 3, DSP data processing circuit 2: comprise 32 floating type dsp processor chips, active crystal oscillator, SDRAM storer.This part circuit realizes that dsp processor carries out the workbench of digital signal processing.Wherein active crystal oscillator provides clock frequency for the dsp processor chip; The SDRAM storer provides external memory resource for the dsp processor chip.
DSP data processing circuit 2 has with the signal wire that PC interface treatment circuit 1 links to each other:
1.HPI data bus: HD[0:15];
2.HPI control line: HCNT[0:1], HCS, HDS, HRDY, HRW, HHWIL;
3.HPI interrupt line: HINT;
4.DSPREST, provide dsp processor to reset;
DSP data processing circuit 2 has with the signal wire that FPGA (Field Programmable Gate Array) treatment circuit 3 links to each other:
1. external bus address wire: 1EA[21:0], the parallel transmission address;
2. external bus data line: 1ED[31:0], the parallel transmission data;
3. external bus control line: 1AWE, 1AOE, 1CE2,1ARE, 1ECLKO, ADINT and 1INT4 provide reading and writing data to handle.
As shown in Figure 4, FPGA (Field Programmable Gate Array) treatment circuit 3: comprise programmable logic chip U400, active crystal oscillator Z401.This part circuit is mainly realized the pre-service of external impact data message, and communicates by external bus and DSP data processing circuit 2; Utilize online programmable simultaneously, realize the control and management of peripheral hardware and external impact testing equipments such as external impact platform or collision stage.Active crystal oscillator is given provides clock frequency.
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the signal wire that DSP data processing circuit 2 links to each other:
1. external bus address wire: 1EA[21:0], the parallel transmission address;
2. external bus data line: 1ED[31:0], the parallel transmission data;
3. external bus control line: 1AWE, 1AOE, 1CE2,1ARE, 1ECLKO, ADINT and 1INT4 provide reading and writing data to handle.
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the data signal line that analog to digital conversion circuit 4 is connected:
1. control line: SCLK1, MCLK1, FSO1, PD1, OTR1 and SYNC1;
2. data line: DOUT1;
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the I/O control signal wire that digital I/O circuit 5 is connected:
Control line: OUTA[1:5], IOA[1:8], INA[1:4]
As shown in Figure 5, analog to digital conversion circuit 4: comprise that resolution 16bit, conversion ratio are up to the modulus conversion chip U5 of 1.25MHz.This part circuit is realized the Analog signals'digital conversion.
Analog to digital conversion circuit 4 has with the data signal line that FPGA (Field Programmable Gate Array) treatment circuit 3 is connected:
1. control line: SCLK1, MCLK1, FSO1, PD1, OTR1 and SYNC1;
2. data line: DOUT1;
Analog to digital conversion circuit 4 has with the signal wire that analog input modulate circuit 5 links to each other:
Analog difference signal line: CHAIN+, CHAIN-; Provide analog input to modulus conversion chip;
As shown in Figure 6, digital I/O circuit 5: comprise level transferring chip U301, I/O interface device JP301 and J309.This part circuit is realized carrying out interface with external impact platform or collision stage.Level transferring chip realizes the Different Logic level conversion of digital signal, and the I/O interface device is realized and being connected of the impact test equipment of outside.
The I/O control signal wire that numeral I/O circuit 5 is connected with FPGA (Field Programmable Gate Array) treatment circuit 3 has:
Control line: OUTA[1:5], IOA[1:8], INA[1:4]
As shown in Figure 7, analog input modulate circuit 6: the main conditioning that realizes outside vibration information, it comprises analog differential input signal conditioning circuit, voltage follower circuit, single-ended signal slip sub-signal circuit and anti-aliasing filter circuit, has adopted the double operational chip U2 of a slice OPA132 series and double operational chip U3, the U4 of two TLE072 series altogether.Wherein U2 constitutes an analog differential input signal conditioning circuit and voltage follower circuit respectively, conditioning with the signal of realizing prime, U3 and U4 constitute three see-saw circuits and an in-phase amplification circuit respectively, convert single-ended signal to differential signal, to satisfy the difference input of modulus conversion chip, R22, R23 and C19, C21, C22 form an anti-aliasing filter circuit, and differential signal is carried out anti-aliasing filter.
Analog to digital conversion circuit 4 has with the signal wire that analog input modulate circuit 5 links to each other:
Analog difference signal line: CHAIN+, CHAIN-; Provide analog input to modulus conversion chip;
As shown in Figure 8, feed circuit 8: mainly be generation+12V ,+5V ,+4V ,+3.3V ,+2.5V ,+1.4V ,+1.2V ,+1V ,-5V and-12V, power supply is provided for other circuit module, comprise+1.2V produce circuit ,+1V produce circuit ,+1.4V produce circuit ,+3.3V produce circuit ,+4V produce circuit ,+5V produce circuit ,+12V produce circuit ,-5V produce circuit and-12V produces circuit; Its conversion chip that adopts is TPS54310, TPS70302, TPS5430, OPA2343, LP3962-2.5, LM340T-12, LM7905 and LM7912.Wherein TPS54310 and interlock circuit generation+1.4V thereof; TPS70302 and interlock circuit generation+3.3V thereof and+1.2V; TPS5430 and interlock circuit generation+5V thereof; OPA2343 and interlock circuit generation+1V thereof and+4V; LP3962 and interlock circuit generation+2.5V thereof; LM340T-12 and interlock circuit generation+12V thereof; LM7905 and interlock circuit generation-5V thereof; LM7912 and interlock circuit generation-12V thereof.
Specific embodiment described herein only is that the utility model spirit is illustrated.The utility model person of ordinary skill in the field can make various modifications or replenishes or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present utility model or surmount the defined scope of appended claims.
Although the utility model has used terms such as DSP data processing circuit 2, FPGA (Field Programmable Gate Array) treatment circuit 3, analog to digital conversion circuit 4, digital I/O circuit 5, HPI bus, external bus morely, do not get rid of the possibility of using other term.Using these terms only is in order to describe and explain essence of the present utility model more easily; They are construed to any additional restriction all is contrary with the utility model spirit.
Claims (8)
1. a shock measurement controller that adopts DSP is characterized in that: comprise PC interface treatment circuit (1), DSP data processing circuit (2), FPGA (Field Programmable Gate Array) treatment circuit (3), analog to digital conversion circuit (4), digital I/O circuit (5), analog input modulate circuit (6) and feed circuit (7); Wherein PC interface treatment circuit (1) is connected with PC by interface, DSP data processing circuit (2) is connected by corresponding data bus respectively with PC interface treatment circuit (1), Programmable Logic Device (3), FPGA (Field Programmable Gate Array) treatment circuit (3) is connected with digital I/O circuit (5) with analog to digital conversion circuit (4) respectively by the digital signal corresponding extension line, analog to digital conversion circuit (4) is connected with analog input modulate circuit (6) by simulating signal input extension line, and feed circuit (7) provide direct supply for each circuit module.
2. a kind of shock measurement controller that adopts DSP according to claim 1 is characterized in that: the data bus that DSP data processing circuit (2) is connected with PC interface treatment circuit (1) is the HPI data bus; The DSP data processing chip that described DSP data processing circuit (2) adopts is 32 floating type DSP data processing chips.
3. a kind of shock measurement controller that adopts DSP according to claim 1, it is characterized in that: the data bus that FPGA (Field Programmable Gate Array) treatment circuit (3) is connected with DSP data processing circuit (2) is an external data bus, and the programmable logic chip that described FPGA (Field Programmable Gate Array) treatment circuit (3) adopts is the SPARTAN3E family chip of XILIINX.
4. a kind of shock measurement controller that adopts DSP according to claim 1 is characterized in that: the modulus conversion chip that described analog to digital conversion circuit (4) adopts is the modulus conversion chip of the highest 1.25MHz of resolution 16Bit, inversion frequency.
5. a kind of shock measurement controller that adopts DSP according to claim 1 is characterized in that: the digital signal extension line that described digital I/O circuit (5) is connected with FPGA (Field Programmable Gate Array) treatment circuit (3) is the I/O control line.
6. a kind of shock measurement controller that adopts DSP according to claim 1, it is characterized in that: the interface that described PC interface treatment circuit (1) is connected with PC is the USB2.0 interface.
7. a kind of shock measurement controller that adopts DSP according to claim 1, it is characterized in that: described analog input modulate circuit (5) comprises analog differential input signal conditioning circuit, voltage follower circuit, single-ended signal slip sub-signal circuit and anti-aliasing filter circuit, and it is low noise, high-precision OPA132 and TLE072 series that the conditioning chip is amplified in its computing of adopting.
8. a kind of shock measurement controller that adopts DSP according to claim 1 is characterized in that: described feed circuit (8) comprise+1V produce circuit ,+1.2V produce circuit ,+1.4V produce circuit ,+2.5V produce circuit ,+3.3V produce circuit ,+4V produce circuit ,+5V produce circuit ,+12V produce circuit ,-5V produce circuit and-12V produces circuit; Its conversion chip that adopts is TPS54310, TPS70302, TPS5430, OPA2343, LP3962-2.5, LM340T-12, LM7905 and LM7912.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720303320XU CN201134025Y (en) | 2007-12-25 | 2007-12-25 | Impact measurement control instrument adopting DSP |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720303320XU CN201134025Y (en) | 2007-12-25 | 2007-12-25 | Impact measurement control instrument adopting DSP |
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| CN201134025Y true CN201134025Y (en) | 2008-10-15 |
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| CNU200720303320XU Expired - Fee Related CN201134025Y (en) | 2007-12-25 | 2007-12-25 | Impact measurement control instrument adopting DSP |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102183350A (en) * | 2011-03-10 | 2011-09-14 | 南京航空航天大学 | Real-time impact monitoring instrument and method of large-scale aviation structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102183350A (en) * | 2011-03-10 | 2011-09-14 | 南京航空航天大学 | Real-time impact monitoring instrument and method of large-scale aviation structure |
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