CN201134024Y - Vibration controller based on DSP - Google Patents
Vibration controller based on DSP Download PDFInfo
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- CN201134024Y CN201134024Y CNU200720303313XU CN200720303313U CN201134024Y CN 201134024 Y CN201134024 Y CN 201134024Y CN U200720303313X U CNU200720303313X U CN U200720303313XU CN 200720303313 U CN200720303313 U CN 200720303313U CN 201134024 Y CN201134024 Y CN 201134024Y
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Abstract
The utility model discloses a vibration controller based on DSP. A PC interface processing circuit is connected with a PC by an interface, a DSP data processing circuit is respectively connected with the PC interface processing circuit and a programmed logic circuit by corresponding data buses, a programmed logic processing circuit is connected with an analog to digital conversion circuit and a figure model conversion circuit by digital signal lead wires, the analog to digital conversion circuit is connected with an analog input conditioning circuit by analog signal input lead wires, the figure model conversion circuit is connected with an analog output conditioning circuit by analog signal output lead wires, and a power supply circuit provides direct current power supply for each circuit module. The vibration controller provided by the utility model has powerful information processing ability, high control precision, strong realtime control and is easy for realizing hardware expansion; furthermore, based on shared bus resources, information calculation treatment and hardware control resources can be optimized through coordination treatment processed on a digital processor DSP and a programmable logic device by a DSP external bus.
Description
Technical field
The utility model relates to vibrating controller, especially relates to a kind of vibrating controller based on DSP.
Background technology
Along with improving constantly to the requirements such as dynamic property, reliability and environmental suitability of structure and product, promote the development of art such as vibration test and vibration control greatly, also the vibration rig of analog vibration environment and the vibration control performance of control system have been proposed more and more higher requirement simultaneously: except the linearity and relative error of good control; Phase place has also been proposed comparatively strict requirement, i.e. it is fast that system vibration control response speed is wanted, and control will have very strong real-time.Traditional vibration rig and control system are difficult to meet the demands, and force people further to seek new solution route.
At present, the control performance that improves control system mainly is by embedded processor on the hardware or to adopt with microcomputer, D/A converting circuit and software be that the virtual instrument of basic framework is realized.
In above-mentioned two kinds of schemes, the The whole control system major function---the one, the control computing of information comprises the computing of vibration control algorithm of information and the computing of external vibration status information; The 2nd, realize hardware controls management to other circuit that comprises analog to digital conversion circuit and D/A converting circuit etc.---all realize by embedded processor or microcomputer, obviously, for the former, internal resource that embedded processor is limited and hardware controls resource will limit the room for promotion of performances such as its control accuracy and control response speed greatly, so this hardware structure can not fully satisfy the application requirements in fields such as vibration test technology and vibration control technology, especially carry out the application facet of the hardware expanding of complicated control algolithm calculating or multiple spot external vibration status information capture at needs.Simultaneously owing to have the unified relation of contradiction in the resources allocation that control computing and hardware controls are managed, its resource distribute the extensibility that also has influence on control performance and hardware to a certain extent rationally.Though, improve the performance of embedded processor in theory, can improve the control performance of system to a certain extent,, being practically limited to design and manufacturing technology of embedded processor own and cost performance, this lifting also is very limited.For the latter, though the resource of microcomputer is relatively sufficient, can realize the high processing precision, but it is very limited that the running characteristic of microsystem improves its performance of handling in real time in control information, can not fully satisfy the vibration applications that dynamic property is had relatively high expectations in the fields such as vibration test technology and vibration control technology.
Summary of the invention
Big for solving the existing control relative error of background technology, the control real-time is not strong, and hardware controls lacks in ability, and is difficult to adapt to vibration test technology and vibration control field higher requirement; The purpose of this utility model is to provide very strong information processing capability, and the control accuracy height is controlled real-timely, is easy to realize a kind of vibrating controller based on DSP of hardware expanding.
The technical scheme that its technical matters that solves the utility model adopts is:
Comprise PC interface treatment circuit, DSP data processing circuit, FPGA (Field Programmable Gate Array) treatment circuit, analog to digital conversion circuit, analog input modulate circuit, D/A converting circuit, simulation output modulate circuit and feed circuit; Wherein PC interface treatment circuit is connected with PC by interface, the DSP data processing circuit is connected by corresponding data bus respectively with PC interface treatment circuit, Programmable Logic Device, the FPGA (Field Programmable Gate Array) treatment circuit is connected with D/A converting circuit with analog to digital conversion circuit by the digital signal extension line, analog to digital conversion circuit is connected with the analog input modulate circuit by simulating signal input extension line, D/A converting circuit is connected with simulation output modulate circuit by simulating signal output extension line, and feed circuit provide direct supply for each circuit module.
The data bus that described DSP data processing circuit is connected with PC interface treatment circuit is the HPI data bus, and the DSP data processing chip that the DSP data processing circuit adopts is 32 floating type DSP data processing chips.
The data bus that described FPGA (Field Programmable Gate Array) treatment circuit is connected with the DSP data processing circuit is an external data bus, and the programmable logic chip that described FPGA (Field Programmable Gate Array) treatment circuit adopts is the SPARTAN2E family chip of XILIINX.
The modulus conversion chip that described analog to digital conversion circuit adopts is the modulus conversion chip of the highest 192KHz of resolution 24Bit, inversion frequency.
The analog-digital chip that described D/A converting circuit adopts is the analog-digital chip of the highest 192KHz of resolution 24Bit, inversion frequency.
The interface that PC interface treatment circuit is connected with PC is the USB2.0 interface.
Described analog input modulate circuit comprises analog differential input signal conditioning circuit, voltage follower circuit, single-ended signal slip sub-signal circuit and anti-aliasing filter circuit, and it is low noise, high-precision OPA132 series that the conditioning chip is amplified in its computing of adopting.
Described simulation output modulate circuit comprises differential amplifier circuit and filtering circuit; Its amplification of adopting conditioning chip is low noise, high-precision OPA132 series.
Described feed circuit comprise+1.2V produce circuit ,+1.8V produce circuit ,+3.3V produce circuit ,+12V produce circuit and-12V produces circuit; Its conversion chip that adopts is TPS54310, TPS70302, LM7812 and LM7912.
The utility model is used to realize the PC interface treatment circuit with the PC message exchange, the DSP data processing circuit that is used for digital information processing, be used to produce logic control signal and realize the pretreated FPGA (Field Programmable Gate Array) treatment circuit of information calculations, analog information is realized the analog to digital conversion circuit of numerical information conversion, analog input signal is carried out the simulating signal input modulate circuit of simulation process, realize that digital signal is converted to the D/A converting circuit of simulating signal, simulating signal is provided by the simulation output modulate circuit of output, the feed circuit of providing power supply to support for each circuit module.Wherein, the DSP data processing circuit is connected by external bus respectively with Programmable Logic Device, and the DSP data processing chip that it adopts is 32 floating type DSP data processing chips; The FPGA (Field Programmable Gate Array) treatment circuit is connected with D/A converting circuit with analog to digital conversion circuit by the digital signal extension line, and the modulus conversion chip that analog to digital conversion circuit adopts is the modulus conversion chip of the highest 192KHz of resolution 24Bit, inversion frequency; The analog-digital chip that D/A converting circuit adopts is the modulus conversion chip of the highest 192KHz of resolution 24Bit, inversion frequency.
Creatively adopt the utility model DSP data processing circuit and Programmable Logic Device realize the core control and treatment of vibration control jointly: Programmable Logic Device can directly realize control of peripheral hardware resource and information calculations pre-service, make data processor DSP can bring into play the ability of its processing data information more fully, DSP data processing circuit and program logic circuit are carried out Coordination Treatment via the external bus of DSP, make control information computing and hardware controls resources allocation optimization.Simultaneously, configuration resolution 24bit, conversion ratio is up to the analog to digital conversion circuit of 192KHZ, simulating signal can be imported the analog information of modulate circuit input and carry out accurately instant conversion, calculate and control and treatment to offer DSP data processing circuit and Programmable Logic Device, its precision of information and processing real-time significantly improve, and by resolution 24bit, conversion ratio is up to D/A converting circuit and the simulation output modulate circuit of 192KHz, can be instant will accurately export and the correction vibration control via the control information that the DSP data processing circuit draws by the computing to input information, thus realize high precision, real-time closed loop vibration control.
In addition, by PC interface treatment circuit, the DSP data processing circuit can carry out message exchange with PC, by the software support, thus the real-time demonstration of realization vibration control field-programmable and external vibration information.
Compared with prior art, the beneficial effect that the utlity model has:
1. combine digital processing unit DSP, programmable logic device (PLD), high speed and precision modulus conversion chip and high speed and precision analog-digital chip.On the basis of the hardware controls of programmable logic device (PLD), immediately accurately outside vibrational state information is gathered by modulus conversion chip, the data in real time processing power that cooperates digital processing unit DSP, via analog-digital chip DSP is handled the digital control information that draws in real time and carry out accurate high-speed transitions output, improved the precision and the real-time of control greatly.
2. combine the data-handling capacity of digital processing unit DSP and the Programmable Technology of programmable logic device (PLD).Programmable Technology by programmed logic device, can directly realize control of peripheral hardware resource and information calculations pre-service, can bring into play the data-handling capacity of digital processing unit DSP more fully, the hardware controls ability is strong simultaneously, be easy to realize hardware expanding, by the software algorithm support, can fully satisfy the requirement in vibration control field.
3. on the basis of shared bus resource, digital processing unit DSP and programmable logic device (PLD) are carried out Coordination Treatment, information calculations is handled and the hardware controls resources optimization by the DSP external bus.
4. rational in infrastructure, low cost of manufacture.
Description of drawings
Fig. 1 is a theory structure block diagram of the present utility model.
Fig. 2 is the structural drawing of the PC interface treatment circuit in the utility model.
Fig. 3 is the structural drawing of the DSP data processing circuit in the utility model.
Fig. 4 is the structural drawing of the FPGA (Field Programmable Gate Array) treatment circuit in the utility model.
Fig. 5 is the structural drawing of the analog to digital conversion circuit in the utility model.
Fig. 6 is the structural drawing of the analog input modulate circuit in the utility model.
Fig. 7 is the structural drawing of the D/A converting circuit in the utility model.
Fig. 8 is the structural drawing of the simulation output modulate circuit in the utility model.
Fig. 9 is the structural drawing of the feed circuit in the utility model.
Embodiment
Below by embodiment, and in conjunction with the accompanying drawings, the technical solution of the utility model is described in further detail.
As shown in Figure 1, a kind of vibrating controller based on DSP comprises PC interface treatment circuit 1, DSP data processing circuit 2, FPGA (Field Programmable Gate Array) treatment circuit 3, analog to digital conversion circuit 4, analog input modulate circuit 5, D/A converting circuit 6, simulation output modulate circuit 7 and feed circuit 8.The DSP data processing circuit is connected by HPI data bus, external bus respectively with PC interface treatment circuit, Programmable Logic Device, the FPGA (Field Programmable Gate Array) treatment circuit is connected with D/A converting circuit with analog to digital conversion circuit by the digital signal extension line, analog to digital conversion circuit is connected with the analog input modulate circuit by simulating signal input extension line, D/A converting circuit is connected with simulation output modulate circuit by simulating signal output extension line, and feed circuit provide direct supply for each circuit module.
The course of work is as follows: the hardware controls management of the FPGA (Field Programmable Gate Array) treatment circuit that passes through, the analog input modulate circuit is gathered outside vibration simulation information, conditioning, by analog to digital conversion circuit simulating signal is realized the digital signal conversion, and offer the FPGA (Field Programmable Gate Array) treatment circuit and calculate pre-service, its data are by external bus transmission DSP data processing circuit, carry out after control strategy etc. handles at it, the output digital control information, and be converted to analog information via D/A converting circuit, nurse one's health the outside actuator of output control by simulation output modulate circuit, thereby can realize closed-loop control; Simultaneously, by PC interface treatment circuit, the DSP data processing circuit can carry out message exchange with PC, by the software support, thus the real-time demonstration of realization vibration control field-programmable and external vibration information.
As shown in Figure 2, PC interface treatment circuit 1: comprise interface management chip U12, active crystal oscillator Z3.The interface management chip is mainly realized data message under the HPI data bus protocol framework and the USB2.0 of PC are communicated.Wherein active crystal oscillator provides clock frequency to managing chip.
The signal wire that PC interface treatment circuit 1 links to each other with DSP data processing circuit 2 has:
1.HPI data bus: HD[0:15]
2.HPI control line: HCNT[0:1], HCS, HDS, HRDY, HRW, HHWIL;
3.HPI interrupt line: HINT;
4.DSPREST, provide dsp processor to reset;
As shown in Figure 3, DSP data processing circuit 2: comprise 32 floating type dsp processor chip U5, active crystal oscillator Z1, SDRAM storer U8.This part circuit realizes that dsp processor carries out the workbench of digital signal processing.Wherein active crystal oscillator provides clock frequency for the dsp processor chip; The SDRAM storer provides external memory resource for the dsp processor chip.
The signal wire that PC interface treatment circuit 1 links to each other with DSP data processing circuit 2 has:
1.HPI data bus: HD[0:15]
2.HPI control line: HCNT[0:1], HCS, HDS, HRDY, HRW, HHWIL;
3.HPI interrupt line: HINT;
4.DSPREST, provide dsp processor to reset;
DSP data processing circuit 2 has with the signal wire that FPGA (Field Programmable Gate Array) treatment circuit 3 links to each other:
1. external bus address wire: 1EA[21:0], the parallel transmission address;
2. external bus data line: 1ED[31:0], the parallel transmission data;
3. external bus control line: AWE, AOE, CE2 and ECLK, INT provide data read-write control.
As shown in Figure 4, FPGA (Field Programmable Gate Array) treatment circuit 3: comprise programmable logic chip U14, active crystal oscillator Z5.This part circuit communicates by external bus and DSP data processing circuit 2, realizes the pre-service of data message, the control and management and the online programmable of peripheral hardware.Active crystal oscillator is given provides clock frequency.
DSP data processing circuit 2 has with the signal wire that FPGA (Field Programmable Gate Array) treatment circuit 3 links to each other:
1. external bus address wire: 1EA[21:0], the parallel transmission address;
2. external bus data line: 1ED[31:0], the parallel transmission data;
3. external bus control line: AWE, AOE, CE2 and ECLK, INT provides data read-write control.
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the signal wire that analog to digital conversion circuit 4 links to each other:
1. control line: ADSCLK, ADLRCK, ADMCLK, ADCKS[1:0], ADDFS[1:0] and ADHPFE;
2. data line: ADSDATA[1:0];
3. reset line :/ADRST provides modulus conversion chip to reset;
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the signal wire that D/A converting circuit 6 links to each other:
1. control line: DASCLK, DALRCK, DAMCLK ,/DAMUTEC ,/DAMUTE and DASMC;
2. data line: DASDATA, digital incoming line;
3. reset line :/DARST provides analog-digital chip to reset.
As shown in Figure 5, analog to digital conversion circuit 4: comprise that resolution 24bit, conversion ratio are up to the modulus conversion chip U17 of 192KHz.This part circuit is realized the Analog signals'digital conversion.
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the signal wire that analog to digital conversion circuit 4 links to each other:
1. control line: DSCLK, ADLRCK, ADMCLK, ADCKS[1:0], ADDFS[1:0] and ADHPFE;
2. data line: ADSDATA[1:0];
3. reset line :/ADRST provides modulus conversion chip to reset.
Analog to digital conversion circuit 4 has with the signal wire that the analog input modulate circuit links to each other:
Analog difference signal line: CHAINL+, CHAINL-, CHAINR+, CHAINR-provides analog input to modulus conversion chip;
As shown in Figure 6, analog input modulate circuit 5: the main conditioning that realizes outside vibration information, it comprises analog differential input signal conditioning circuit, voltage follower circuit, single-ended signal slip sub-signal circuit and anti-aliasing filter circuit, has adopted the double operational chip of three OPA132 series altogether.Wherein U2 constitutes an analog differential input signal conditioning circuit and voltage follower circuit respectively, conditioning with the signal of realizing prime, U3 and U4 constitute three see-saw circuits respectively, convert single-ended signal to differential signal, to satisfy the difference input of modulus conversion chip, R22, R23 and C19 form an anti-aliasing filter circuit, and differential signal is carried out anti-aliasing filter.
Analog to digital conversion circuit 4 has with the signal wire that analog input modulate circuit 5 links to each other:
Analog difference signal line: CHAINL+, CHAINL-, CHAINR+, CHAINR-; Provide analog input to modulus conversion chip;
As shown in Figure 7, D/A converting circuit 6: comprise that resolution 24bit, conversion ratio are up to the analog-digital chip U16 of 192KHz.This part circuit is realized the analog-converted of digital signal.
FPGA (Field Programmable Gate Array) treatment circuit 3 has with the signal wire that D/A converting circuit 6 links to each other:
1. control line: DASCLK, DALRCK, DAMCLK ,/DAMUTEC ,/DAMUTE and DASMC;
2. data line: DASDATA, digital incoming line;
3. reset line :/DARST provides analog-digital chip to reset.
D/A converting circuit 6 has with the signal wire that simulation output modulate circuit 7 links to each other:
Analog difference signal line: CHOUTL+, CHOUTL-, CHOUTR+, CHOUTR-provides simulation output;
As shown in Figure 8, simulation output modulate circuit 7: the analog information of this part circuit realization logarithmic mode conversion chip output is nursed one's health, and comprises differential amplifier circuit and filtering circuit, has adopted the double operational chip U9 of a slice OPA132 series altogether.Wherein R252 and C172, R258 and C175 constitute the RC filtering circuit respectively, and differential input signal is carried out Filtering Processing, and amplifier U9 constitutes a differential amplifier circuit, with the conditioning output of the signal realized.
D/A converting circuit 6 has with the signal wire that simulation output modulate circuit 7 links to each other:
Analog difference signal line: CHOUTL+, CHOUTL-, CHOUTR+, CHOUTR-provides simulation output;
As shown in Figure 9, feed circuit 8 mainly be generation+12V ,+3.3V ,+1.8V ,+1.2V and-12V, power supply is provided for other circuit module, comprise+1.2V produce circuit ,+1.8V produce circuit ,+3.3V produce circuit ,+12V produce circuit and-12V produces circuit; Its conversion chip that adopts is TPS54310, TPS70302, LM7812 and LM7912.Wherein LM7812 and interlock circuit generation+12V, LM7912 and interlock circuit generation-12V, TPS54310 and interlock circuit generation+1.2V, TPS70302 and interlock circuit generation+3.3V thereof and+1.8V.+ 12V and-12V provides power supply to analog input modulate circuit 5 and simulation output modulate circuit 7; + 3.3V ,+1.8V and+1.2V provides power supply for all the other modules.
Specific embodiment described herein only is that the utility model spirit is illustrated.The utility model person of ordinary skill in the field can make various modifications or replenishes or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present utility model or surmount the defined scope of appended claims.
Although this paper has used terms such as DSP data processing circuit 2, FPGA (Field Programmable Gate Array) treatment circuit 3, analog to digital conversion circuit 4, D/A converting circuit 6, HPI bus, external bus and digital signal line morely, do not get rid of the possibility of using other term.Using these terms only is in order to describe and explain essence of the present utility model more easily; They are construed to any additional restriction all is contrary with the utility model spirit.
Claims (9)
1. vibrating controller based on DSP, it is characterized in that: comprise PC interface treatment circuit (1), DSP data processing circuit (2), FPGA (Field Programmable Gate Array) treatment circuit (3), analog to digital conversion circuit (4), analog input modulate circuit (5), D/A converting circuit (6), simulation output modulate circuit (7) and feed circuit (8); Wherein PC interface treatment circuit (1) is connected with PC by interface, DSP data processing circuit (2) and PC interface treatment circuit (1), Programmable Logic Device (3) is connected by corresponding data bus respectively, FPGA (Field Programmable Gate Array) treatment circuit (3) is connected with D/A converting circuit (6) with analog to digital conversion circuit (4) by the digital signal extension line, analog to digital conversion circuit (4) is connected with analog input modulate circuit (5) by simulating signal input extension line, D/A converting circuit (6) is connected with simulation output modulate circuit (7) by simulating signal output extension line, and feed circuit (8) provide direct supply for each circuit module.
2. a kind of vibrating controller according to claim 1 based on DSP, it is characterized in that: the data bus that described DSP data processing circuit (2) is connected with PC interface treatment circuit (1) is the HPI data bus, and the DSP data processing chip that DSP data processing circuit (2) adopts is 32 floating type DSP data processing chips.
3. a kind of vibrating controller according to claim 1 based on DSP, it is characterized in that: the data bus that described FPGA (Field Programmable Gate Array) treatment circuit (3) is connected with DSP data processing circuit (2) is an external data bus, and the programmable logic chip that described FPGA (Field Programmable Gate Array) treatment circuit (3) adopts is the SPARTAN2E family chip of XILIINX.
4. a kind of vibrating controller based on DSP according to claim 1 is characterized in that: the modulus conversion chip that described analog to digital conversion circuit (4) adopts is the modulus conversion chip of the highest 192KHz of resolution 24Bit, inversion frequency.
5. a kind of vibrating controller based on DSP according to claim 1 is characterized in that: the analog-digital chip that described D/A converting circuit (6) adopts is the analog-digital chip of the highest 192KHz of resolution 24Bit, inversion frequency.
6. a kind of vibrating controller based on DSP according to claim 1 is characterized in that: the interface that PC interface treatment circuit (1) is connected with PC is the USB2.0 interface.
7. a kind of vibrating controller according to claim 1 based on DSP, it is characterized in that: described analog input modulate circuit (5) comprises analog differential input signal conditioning circuit, voltage follower circuit, single-ended signal slip sub-signal circuit and anti-aliasing filter circuit, and it is low noise, high-precision OPA132 series that the conditioning chip is amplified in its computing of adopting.
8. a kind of vibrating controller based on DSP according to claim 1 is characterized in that: described simulation output modulate circuit (7) comprises differential amplifier circuit and filtering circuit; Its amplification of adopting conditioning chip is low noise, high-precision OPA132 series.
9. a kind of vibrating controller based on DSP according to claim 1 is characterized in that: described feed circuit (8) comprise+1.2V produce circuit ,+1.8V produce circuit ,+3.3V produce circuit ,+12V produce circuit and-12V produces circuit; Its conversion chip that adopts is TPS54310, TPS70302, LM7812 and LM7912.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720303313XU CN201134024Y (en) | 2007-12-25 | 2007-12-25 | Vibration controller based on DSP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU200720303313XU CN201134024Y (en) | 2007-12-25 | 2007-12-25 | Vibration controller based on DSP |
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| CN201134024Y true CN201134024Y (en) | 2008-10-15 |
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| CNU200720303313XU Expired - Fee Related CN201134024Y (en) | 2007-12-25 | 2007-12-25 | Vibration controller based on DSP |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104155551A (en) * | 2014-08-08 | 2014-11-19 | 杭州亿恒科技有限公司 | Power device noise test device |
| CN104181418A (en) * | 2014-08-19 | 2014-12-03 | 杭州亿恒科技有限公司 | Electric device noise testing device based on DSP and testing method thereof |
-
2007
- 2007-12-25 CN CNU200720303313XU patent/CN201134024Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104155551A (en) * | 2014-08-08 | 2014-11-19 | 杭州亿恒科技有限公司 | Power device noise test device |
| CN104155551B (en) * | 2014-08-08 | 2018-03-30 | 杭州亿恒科技有限公司 | A kind of electrical device noise fest device |
| CN104181418A (en) * | 2014-08-19 | 2014-12-03 | 杭州亿恒科技有限公司 | Electric device noise testing device based on DSP and testing method thereof |
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Granted publication date: 20081015 Termination date: 20161225 |