CN201084727Y - 半导体器件无脚封装结构 - Google Patents

半导体器件无脚封装结构 Download PDF

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CN201084727Y
CN201084727Y CN 200720046078 CN200720046078U CN201084727Y CN 201084727 Y CN201084727 Y CN 201084727Y CN 200720046078 CN200720046078 CN 200720046078 CN 200720046078 U CN200720046078 U CN 200720046078U CN 201084727 Y CN201084727 Y CN 201084727Y
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chip
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王新潮
于燮康
梁志忠
谢洁人
陶玉娟
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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Abstract

本实用新型涉及一种半导体器件无脚封装结构，所述结构包括芯片承载底座(1)、打线引脚承载底座(2)、芯片(3)、金属线(4)以及塑封体(5)，所述芯片承载底座(1)和打线引脚承载底座(2)的底部凸出于塑封体(5)的底部，芯片承载底座(1)由两部分组成，一部分置于塑封体内，另一部分置于塑封体外，置于塑封体内的部分由多个独立的金属凸块(1.1)构成，多个独立的金属凸块(1.1)延伸至塑封体(5)外部时则共同连接在一片完整的金属片(1.2)上，外露的金属片(1.2)呈托盘状承载住塑封体内的多个独立的金属凸块(1.1)并凸出于塑封体(5)底部，构成芯片承载底座的另一部分；所述芯片置于芯片承载底座的金属凸块(1.1)上。本实用新型封装产品不会产生分层、芯片承载底座不会脱落、可以适用于大功率、高散热产品需求。

Description

半导体器件无脚封装结构
技术领域
本发明涉及一种半导体器件无脚封装结构及其封装工艺属于半导体封装技术领域。
背景技术
传统的半导体器件芯片承载底座外露式无脚封装结构在设计时采用整片/整块金属片作为芯片承载底座(如图1)
这种芯片承载底座结构存在以下不足：
1、封装产品内易产生大量应力残留进而影响产品可靠性——封装体内的材质可以分为三大类：金属(铜、铁、镍等)、芯片(硅材质)以及塑封料。从材质的热膨胀系数角度看，芯片与塑封料热膨胀率相近，而金属的热膨胀率则远远高于芯片和塑封料。在高温环境下这种差异会加剧塑封体内的应力残留。而金属所占的比例越高，所需形变量就越大，大片金属块因受制于塑封体而无法产生较大的形变进而积累更多的应力，芯片表面所受应力也就越大，最终导致产品分层或功能失效。大片金属构成的芯片承载底座则正是增加了封装体内的金属比例。
2、芯片承载底座容易脱落，进而导致产品失效——这种整片而大块的金属结构与塑封料之间的结合面有限，因而结构强度较低；产品在进行表面反复贴装时，整块的芯片承载底座很容易因受力而被拔出塑封体，造成芯片承载底座脱落。
3、芯片承载底座的灵活性较低，难以适用于多种不同大小芯片的需求——这种块状的芯片承载底座尺寸固定，遇到相对较长、较宽或接近芯片承载底座尺寸的芯片时就必须更改框架的设计来配合，耗费成本和时间。
发明内容
本发明的目的在于克服上述不足，提供一种封装产品不会产生分层、芯片承载底座不会脱落、可以适用于大功率、高散热产品需求的半导体器件无脚封装结构。
本发明的目的是这样实现的：一种半导体器件无脚封装结构，包括芯片承载底座、打线引脚承载底座、芯片、金属线以及塑封体，所述芯片承载底座、打线引脚承载底座、芯片和金属线被塑封体包覆，并使芯片承载底座和打线引脚承载底座的底部凸出于塑封体的底部，其特征在于：
所述芯片承载底座由两部分组成，一部分置于塑封体内，另一部分置于塑封体外，置于塑封体内的部分由多个独立的金属凸块构成，多个独立的金属凸块延伸至塑封体外部时则共同连接在一片完整的金属片上，外露的金属片呈托盘状承载住塑封体内的多个独立的金属凸块并凸出于塑封体底部，构成芯片承载底座的另一部分；
所述芯片置于芯片承载底座的金属凸块上。
本发明半导体器件无脚封装结构，所述凸出于塑封体底部的芯片承载底座的表面和打线引脚承载底座的表面均被金属层I包覆。
本发明半导体器件无脚封装结构，所述打线引脚承载底座的正面覆有金属层II。
本发明半导体器件无脚封装结构，所述芯片承载底座的多个独立的金属凸块中，部分或全部金属凸块的顶部覆有金属层III。
本发明半导体器件无脚封装体与传统的半导体器件芯片承载底座外露式无脚封装结构相比，本发明具有如下优点：
1、更好地释放封装体内的应力，改善产品的可靠性——封装体内的芯片承载底座部分为多个独立的金属凸块，相对于传统的整块大金属块，一方面是降低了金属所占比例，另一方面单个小金属块所需的形变量小，大大降低了塑封料对其细微形变的限制，而单个小金属块这种细微的形变则可以更好的释放封装体内因不同材质而产生的应力，降低了芯片表面所受的应力，在确保产品性能的同时也避免了分层的风险。
2、封装体内的芯片承载底座的多个独立的金属凸块与塑封料之间的结合面积大大增加，结合力也随之提升，不会产生芯片承载底座掉出的问题。
3、芯片承载底座的灵活性高，即使面对尺寸较大的芯片，芯片承载底座外部的整片金属也可以发挥托盘效应方式封装工艺过程中银胶外露的问题，进而增加了框架的活用性，节省了开发成本。
4、这种多个独立金属块构成的芯片承载底座增加了金属的表面积，进而提高了产品的散热面积，可以满足大功率、高散热产品的需求。
附图说明
图1为传统的半导体器件芯片承载底座外露式无脚封装结构方式一示意图。
图2为本发明半导体器件无脚封装结构断面示意图。
图中：芯片承载底座1、打线引脚承载底座2、芯片3、金属线4以及塑封体5、金属层I6、金属层II7、金属层III8。
具体实施方式
参见图2，本发明涉及一种半导体器件无脚封装结构，它主要由芯片承载底座1、打线引脚承载底座2、芯片3、金属线4以及塑封体5组成。所述打线引脚承载底座2置于芯片承载底座1外围，芯片3置于芯片承载底座1顶端，金属线4连接于芯片3与芯片承载底座1和打线引脚承载底座2之间，或金属线4连接于芯片3与打线引脚承载底座2之间，塑封体5包覆于芯片承载底座1、打线引脚承载底座2、芯片3和金属线4外，并使芯片承载底座1和打线引脚承载底座2底部凸出于塑封体5底部。
所述芯片承载底座1由两部分组成，一部分置于塑封体5内，另一部分置于塑封体5外，置于塑封体5内的部分由多个独立的金属凸块1.1构成，多个独立的金属凸块1.1延伸至塑封体5外部时则共同连接在一片完整的金属片1.2上，外露的金属片1.2呈托盘状承载住塑封体内的多个独立的金属凸块1.1并凸出于塑封体5底部，构成芯片承载底座1的另一部分。
所述芯片3置于芯片承载底座的金属凸块1.1上。
所述凸出塑封体5底部的芯片承载底座1的表面和打线引脚承载底座2的表面均被金属层I6包覆。
本发明半导体器件无脚封装结构，所述打线引脚承载底座2的正面覆有金属层II7。
本发明半导体器件无脚封装结构，所述芯片承载底座的多个独立的金属凸块1.1中，部分或全部金属凸块1.1的顶部覆有金属层III8。

Claims (5)

1.一种半导体器件无脚封装结构，包括芯片承载底座(1)、打线引脚承载底座(2)、芯片(3)、金属线(4)以及塑封体(5)，所述芯片承载底座(1)、打线引脚承载底座(2)、芯片(3)和金属线(4)被塑封体(5)包覆，并使芯片承载底座(1)和打线引脚承载底座(2)的底部凸出于塑封体(5)的底部，其特征在于：
所述芯片承载底座(1)由两部分组成，一部分置于塑封体(5)内，另一部分置于塑封体(5)外，置于塑封体(5)内的部分由多个独立的金属凸块(1.1)构成，多个独立的金属凸块(1.1)延伸至塑封体(5)外部时则共同连接在一片完整的金属片(1.2)上，外露的金属片(1.2)呈托盘状承载住塑封体内的多个独立的金属凸块(1.1)并凸出于塑封体(5)底部，构成芯片承载底座(1)的另一部分；
所述芯片(3)置于芯片承载底座的金属凸块(1.1)上。
2.根据权利要求1所述的一种半导体器件无脚封装结构，其特征在于：所述凸出于塑封体(5)底部的芯片承载底座(1)的表面和打线引脚承载底座(2)的表面均被金属层I(6)包覆。
3.根据权利要求1或2所述的一种半导体器件无脚封装结构，其特征在于：所述打线引脚承载底座(2)的正面覆有金属层II(7)。
4.根据权利要求1或2所述的一种半导体器件无脚封装结构，其特征在于：所述芯片承载底座的多个独立的金属凸块(1.1)中，部分或全部金属凸块(1.1)的顶部覆有金属层III(8)。
5.根据权利要求3所述的一种半导体器件无脚封装结构，其特征在于：所述芯片承载底座的多个独立的金属凸块(1.1)中，部分或全部金属凸块(1.1)的顶部覆有金属层III(8)。
CN 200720046078 2007-09-13 2007-09-13 半导体器件无脚封装结构 Expired - Lifetime CN201084727Y (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100464415C (zh) * 2007-09-13 2009-02-25 江苏长电科技股份有限公司 半导体器件无脚封装结构及其封装工艺
CN109261927A (zh) * 2018-11-19 2019-01-25 吉林省众慧广博科技有限公司 一种高压铸铝合金工件迅速固化定型设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100464415C (zh) * 2007-09-13 2009-02-25 江苏长电科技股份有限公司 半导体器件无脚封装结构及其封装工艺
CN109261927A (zh) * 2018-11-19 2019-01-25 吉林省众慧广博科技有限公司 一种高压铸铝合金工件迅速固化定型设备

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