CN201039006Y

CN201039006Y - High performance and high integration DC/DC voltage ascending machine

Info

Publication number: CN201039006Y
Application number: CNU2007201088890U
Authority: CN
Inventors: 陈妙萍; 马成炎; 章可循
Original assignee: HANGZHOU ZHONGKE MICROELECTRONIC CO Ltd
Current assignee: HANGZHOU ZHONGKE MICROELECTRONIC CO Ltd
Priority date: 2007-05-09
Filing date: 2007-05-09
Publication date: 2008-03-19
Anticipated expiration: 2017-05-09

Abstract

The utility model relates to a DC/DC booster with high performance and high integration, which comprises a clock generation circuit, a non-coincident clock signal generation circuit, and a switch-typed boosting circuit. The input terminal of the clock generation circuit is connected to a starting signal Start of the whole booster; the output signal of the clock generation circuit is the CLK which is connected with the input terminal of the non-coincident clock signal generation circuit which converts the CLK signal into the clock signal CLK1 and the clock signal CLK2 which are mutually complementary but not coincident and which are respectively connected with two control terminals of the switch-typed boosting circuit; the input voltage Vin is connected with the input terminal of the switch-typed boosting circuit; the input voltage Vin is boosted into the Vout by the switch-typed boosting circuit under the control of two clock signals which are not coincident, and the required boosting voltage value and current are output. The utility model has the advantages of good circuit independence, high integration level, high boosting efficiency, thus meeting the requirement of high performance power supply management of portable electronic products.

Description

High-performance, high integration DC/DC stepup transformer

Technical field

The utility model belongs to the field of power management of electronic technology, relates to a kind of stepup transformer, relates in particular to a kind of high-performance, high integration DC/DC stepup transformer.

Background technology

Power supply is the important component part of electronic equipment, and its quality directly influences the reliability of electronic equipment.Modern high density, it has been the development trend of integrated system that low power consumption integrated circuit is pursued low supply voltage, especially portable or portable type electronic product, as walkman, CD Player, MP3 player etc., generally adopt 1.5V or 3V powered battery, but the kernel processor chip of this class of electronic devices, as MPU, devices such as DSP, mostly still adopt the powered battery of 3.3V or 3V or 2.7V voltage, must be converted to operating voltage by the DC/DC change-over circuit, and the energy consumption of battery can increase along with service time, therefore input voltage is constantly reduced, cause the chip cisco unity malfunction, need to adopt stepup transformer the input voltage processing of boosting.And battery powered portable equipment as handheld instrument, mobile communication, microprocessor system, Medical Instruments and personal digital assistant (PDA) etc., all has very high requirement to the performances such as volume, weight and power consumption of stepup transformer.Stepup transformer belongs to power module, for the chip of entire equipment provides power supply, so require this module to be independent of other non-power modules, is that clock or power supply all can not be public with other modules.

The powered battery module of prior art can be divided into DC/DC charge pump type and two kinds of stepup transformers of inductance type (claiming voltage regulator again).The inductance type regulator adopts the inductor storage power, for the low power consumption integrated circuit system, has following defective: 1. power supply noise is big and the switch radiated noise is big; 2. the inductance of storage power can't be inner integrated, need be external, and the corresponding treatment circuits such as extra decoupling, special ground wire, shielding of wanting; 3. need the plate space bigger, these all cause circuit level variation, installation cost to improve.The charge pump type stepup transformer adopts the capacitor stores energy, known Dickson DC/DC charge pump type booster circuit schematic diagram as shown in Figure 1, it comprises that an input layer, 4 draw high layer, an output layer, also need an external clock crystal oscillator provide the nonoverlapping complementary clock of two-phase (Φ ,-Φ), each draws high layer all a nmos switch pipe and an external charge storaging capacitor.There is following defective in its voltage owing to order draws high layer by layer: 1. be subjected to last one to draw high layer influence of switching tube starting voltage, limited each and drawn high the maximum voltage gain of layer; 2. each drain and gate that draws high layer switching tube links to each other and works in the saturation region, can produce matrix effect and reduces the efficient of stepup transformer; 3. poor, the installation cost height of booster circuit complex structure, circuit level, circuit independence are poor.

Summary of the invention

The utility model solves mainly that present booster circuit complex structure, circuit level are poor, installation cost height, circuit independence is poor, boosting efficiency is low technical problem.A kind of circuit structure is simple, circuit level is high, installation cost is low, circuit independence is good, boosting efficiency is high high-performance, high integration DC/DC stepup transformer are provided.

Above-mentioned technical problem of the present utility model is mainly solved by following technical proposals: the utility model comprises a clock generation circuit, not overlapping clock signal generating circuit and a switching mode booster circuit; The clock generation circuit input inserts the enabling signal Start of whole stepup transformer, the output of clock generation circuit connects the not input of overlapping clock signal generating circuit, the two-way output of overlapping clock signal generating circuit does not connect the two-way control end of switching mode booster circuit respectively, input voltage vin connects the input of switching mode booster circuit, and the output of switching mode booster circuit is output voltage V out; The output signal of clock generation circuit is CLK, and not overlapping clock signal generating circuit is the complementary nonoverlapping clock signal clk 1 of two-phase, CLK2 with the CLK signal transition; The switching mode booster circuit is the switching mode stepup transformer of not overlapping clock signal control, and it boosts input voltage vin under the not overlapping clock signal control of two-phase and is Vout, exports required booster voltage value and electric current.The clock generation circuit design is saved clock crystal oscillator in stepup transformer inside, reduces external circuits, thereby reduces cost, and improves the circuit independence of whole stepup transformer.This booster circuit is simple in structure, the integrated level height, and boosting efficiency is good.Satisfy battery powered portable equipment volume high performance requirements little, in light weight, low in energy consumption.

As preferably, described clock generation circuit comprises one two input nand gate L1 and end to end even number of inverters, the enabling signal of clock generation circuit connects the input of two input nand gate L1, the input of the output termination first order inverter of two input nand gate L1, another input of the output termination two input nand gate L1 of afterbody inverter, this end are the output of a phase clock signal CLK of clock generation circuit generation; The output of the output of each grade inverter and two input nand gate L1 all is connected with a load capacitance Cd, the other end ground connection of load capacitance Cd.The enabling signal of clock generation circuit is that step signal is prolonged in a rising.Two input nand gates and end to end even number of inverters constitute the toroidal oscillation link of a closed loop.Each load capacitance is used for strengthening the time of delay of each grade signal output, guarantees that the clock frequency signal CLK of last output reaches desired clock frequency, and this clock frequency is decided by the number of inverter and the capacitance size of load capacitance.

As preferably, described not overlapping clock signal generating circuit comprises two two input nand gate L2, a L3 and 2n+1 inverter, the clock signal one tunnel that described clock generation circuit produces connects the input of two input nand gate L2, another Lu Jingyi inverter connects the input of two input nand gate L3, two two input nand gate L2, the output of L3 connects the series circuit of n inverter respectively, form two n level inverters, the output signal of two n level inverters is respectively CLK1, CLK2, CLK1 links to each other with another input of L3 again, CLK2 links to each other CLK1 with another input of L2 again, CLK2 is not two not overlapping clock signal outputs of overlapping clock signal generating circuit.The clock signal that clock generation circuit produces changes the clock signal of two complementations into by inverter.First clock signal output CLK1 and second clock signal output CLK2 are complimentary to one another not overlapping, as the not overlapping clock signal of the needed two-phase of switching mode booster circuit operate as normal.

As preferably, the pipe sizing of described n level inverter increases step by step in the geometric ratio mode.Make n level inverter play the effect of drive circuit simultaneously, save and drive link.Simplify circuit, save cost, improve integrated level.

As preferably, described n equals 4.

As preferably, described switching mode booster circuit comprises by three PMOS pipe M1, M2, M3 and the four-way switch that NMOS pipe M4 forms, the source electrode of M1 links to each other with the drain electrode of M2 and links to each other with the end of capacitor C s, the source electrode of M3 links to each other with the drain electrode of M4 and links to each other with the other end of capacitor C s, M1, M2, the substrate of M3 meets metal capacitance C1 respectively, C2, the positive pole of C3, metal capacitance C1, C2, the negative pole of C3 and M1, the drain electrode of M3 all links to each other with input voltage vin, M2, be connected with the parallel circuits of capacitor C L and resistance R L between the source electrode of M4, and the source ground of M4, the grid of M1 connects a phase clock signal of described not overlapping clock signal generating circuit, M2, M3, the grid of M4 all connects another phase clock signal of described not overlapping clock signal generating circuit, and the source electrode of M2 is the voltage output end Vout of described switching mode booster circuit.M1 and M4 form one group of switch that conducting is simultaneously turn-offed simultaneously, and M2 and M3 form the switch that another group conducting is simultaneously turn-offed simultaneously, these two groups of switches the two-phase complementation not under the control of overlapping clock signal alternate conduction alternately turn-off.When a phase clock that links to each other with the grid of M1 was low level, another phase clock was a high level, at this moment M1, M4 conducting, M2, M3 turn-off, by charging, (influence in the pressure drop of loss and charging interval when not considering the pipe conducting) in the ideal case, the terminal voltage of capacitor C s is Vin; When the phase clock upset that links to each other with the grid of M1 was high level, another phase clock was a low level, and this moment, M1, M4 turn-offed, M2, M3 conducting are by charging, in the ideal case, the terminal voltage of Cs becomes 2Vin, and connects output with voltage output end Vout, thereby realizes boosting.The substrate terminal that while three PMOS manage M1, M2, M3 does not link to each other with power end, all connect a metal capacitance, the other end of metal capacitance links to each other with input voltage vin, and is partially anti-all the time to guarantee PMOS pipe PN junction of source electrode and substrate when the work, avoid occurring matrix effect, improve boosting efficiency.

The beneficial effects of the utility model are: establish clock generation circuit in the utility model, to be independent of other non-power modules, circuit independence is good, and cost is low; Three PMOS pipe M1, M2 in the switching mode booster circuit, the substrate terminal of M3 all link to each other with input voltage vin through metal capacitance, guarantee that PMOS pipe PN junction of source electrode and substrate when work is anti-all the time inclined to one side, avoid occurring matrix effect, have improved boosting efficiency.And entire circuit is simple in structure, and it is convenient to realize, the integrated level height.Satisfy the needs of the high-performance power management of portable, portable type electronic product.

Description of drawings

Fig. 1 is known Dickson DC/DC charge pump type booster circuit schematic diagram.

Fig. 2 is the switching mode booster circuit block diagram of a kind of not overlapping clock of the present utility model.

Fig. 3 is a kind of clock generation circuit schematic diagram of the utility model embodiment.

Fig. 4 is a kind of not overlapping clock signal generating circuit schematic diagram of the utility model embodiment.

Fig. 5 is a kind of switching mode booster circuit schematic diagram of the utility model embodiment.

1-clock generation circuit, 2 among the figure-not overlapping clock signal generating circuit, 3-switching mode booster circuit, 4-inverter, 5-inverter, 6-n level inverter.

Embodiment

Below by embodiment, and in conjunction with the accompanying drawings, the technical solution of the utility model is described in further detail.

Embodiment 1: the circuit block diagram of the utility model high-performance, high integration DC/DC stepup transformer comprises clock generation circuit 1, not overlapping clock signal generating circuit 2, switching mode booster circuit 3 as shown in Figure 2.The enabling signal Start of the whole stepup transformer of input termination of clock generation circuit 1, when the output signal of clock generation circuit 1 is CLK, this output is as the input signal of not overlapping clock signal generating circuit 2, not overlapping clock signal generating circuit 2 is the CLK signal transition that the complementary nonoverlapping clock signal clk 1 of two-phase, CLK2 output to switching mode booster circuit 3, as the control signal of switching tube in the switching mode booster circuit 3.Switching mode booster circuit 3 boosts input voltage vin and is Vout, exports required booster voltage value and current value.

Concrete clock generation circuit 1 comprises one two input nand gate L1 and end to end even number of inverters 4 as shown in Figure 3, and in the present embodiment, the inverter number gets 18.Enabling signal Start connects the input of two input nand gate L1, the input of the output termination first order inverter of two input nand gate L1, another input of the output termination two input nand gate L1 of the 18th grade of inverter, this end are the output of a phase clock signal CLK of clock generation circuit generation; The output of the output of each grade inverter 4 and two input nand gate L1 all is connected with a load capacitance Cd, the other end ground connection of load capacitance Cd.

Concrete not overlapping clock signal generating circuit 2 as shown in Figure 4, comprise two two input nand gate L2, L3 and nine inverters 5, the clock signal clk one tunnel that clock generation circuit 1 produces connects the input of two input nand gate L2, another Lu Jingyi inverter 5 connects the input of two input nand gate L3, two two input nand gate L2, the output of L3 connects the series circuit of four inverters 5 respectively, form two level Four inverters 6, the pipe sizing of each level Four inverter 6 increases step by step in the geometric ratio mode, the output signal of two fourth stage inverters 5 is respectively CLK1, CLK2, CLK1, CLK2 intersects mutually, CLK1 links to each other with another input of L3, CLK2 links to each other CLK1 with another input of L2, CLK2 is two not overlapping clock signal outputs of not overlapping clock signal generating circuit 2.

Concrete switching mode booster circuit 3 as Fig. 5 as showing, comprise by three PMOS pipe M1, M2, M3 and the four-way switch that NMOS pipe M4 forms, the source electrode of M1 links to each other with the drain electrode of M2 and links to each other with the end of capacitor C s, the source electrode of M3 links to each other with the drain electrode of M4 and links to each other with the other end of capacitor C s, M1, M2, the substrate of M3 meets metal capacitance C1 respectively, C2, the positive pole of C3, metal capacitance C1, C2, the negative pole of C3 and M1, the drain electrode of M3 all links to each other with input voltage vin, M2, be connected with the parallel circuits of capacitor C L and resistance R L between the source electrode of M4, and the source ground of M4, the grid of M1 meets a phase clock signal CLK1 of not overlapping clock signal generating circuit 2, M2, M3, the grid of M4 all meets another phase clock signal CLK2, and the source electrode of M2 is the voltage output end Vout of switching mode booster circuit 3.When CLK1 was low level, CLK2 was a high level, switching tube M1, M4 conducting at this moment, and switching tube M2, M3 turn-off, by charging, (influence in the pressure drop of loss and charging interval when not considering the pipe conducting) in the ideal case, Cs one terminal voltage is Vin; When CLK1 upset during for high level, CLK2 is a low level, and this moment, switching tube M1, M4 turn-offed, switching tube M2, M3 conducting, and by charging, in the ideal case, Cs one terminal voltage becomes and is 2Vin, and connects output with Vout, thereby reaches the purpose of boosting.

Present embodiment is applied in the GPS radio-frequency front-end system, and chip is selected tsmc.25 technology for use, and Start signal, two input nand gates and inverter, its maximum level all are input voltage vin, and PMOS pipe, NMOS pipe are all selected the channel length of minimum dimension for use.When input voltage vin changes, to export clock rate C LK and change with input voltage vin, the CLK scope of designing is 500KHz～1MHz.When Vin=1.7V, CLK=500KHz; During Vin=2.7V, CLK=1MHz.Minimum input voltage is Vin=1.7V in the present embodiment, and output voltage V out=2.7V, output current are 40 mA.

Claims

1. a high-performance, high integration DC/DC stepup transformer is characterized in that comprising: a clock generation circuit (1), not overlapping clock signal generating circuit (2) and a switching mode booster circuit (3); Clock generation circuit (1) input inserts the enabling signal Start of whole stepup transformer, the output of clock generation circuit (1) connects the input of not overlapping clock signal generating circuit (2), the two-way output of not overlapping clock signal generating circuit (2) connects the two-way control end of switching mode booster circuit (3) respectively, input voltage vin connects the input of switching mode booster circuit (3), and the output of switching mode booster circuit (3) is output voltage V out;

The output signal of clock generation circuit (1) is CLK, and not overlapping clock signal generating circuit (2) is the complementary nonoverlapping clock signal clk 1 of two-phase, CLK2 with the CLK signal transition

Switching mode booster circuit (3) is the switching mode stepup transformer of not overlapping clock signal control, and it boosts input voltage vin under the not overlapping clock signal control of two-phase and is Vout, exports required booster voltage value and electric current.

2. high-performance according to claim 1, high integration DC/DC stepup transformer, it is characterized in that described clock generation circuit (1) comprises one two input nand gate L1 and end to end even number of inverters (4), the enabling signal Start of clock generation circuit (1) connects the input of two input nand gate L1, the input of the output termination first order inverter of two input nand gate L1, another input of the output termination two input nand gate L1 of afterbody inverter, this end are the output of a phase clock signal CLK of clock generation circuit generation; The output of each grade inverter (4) and the output of two input nand gate L1 all are connected with a load capacitance Cd, the other end ground connection of load capacitance Cd.

3. high-performance according to claim 1, high integration DC/DC stepup transformer, it is characterized in that described not overlapping clock signal generating circuit (2) comprises two two input nand gate L2, a L3 and 2n+1 inverter (5), the clock signal one tunnel that described clock generation circuit (1) produces connects the input of two input nand gate L2, another Lu Jingyi inverter (5) connects the input of two input nand gate L3, two two input nand gate L2, the output of L3 connects the series circuit of n inverter (5) respectively, form two n level inverters (6), the output signal of two n level inverters (5) is respectively CLK1, CLK2, CLK1 links to each other with another input of L3 again, CLK2 links to each other CLK1 with another input of L2 again, CLK2 is two not overlapping clock signal outputs of not overlapping clock signal generating circuit (2).

4. high-performance according to claim 3, high integration DC/DC stepup transformer is characterized in that the pipe sizing of described n level inverter (6) increases step by step in the geometric ratio mode.

5. high-performance according to claim 3, high integration DC/DC stepup transformer is characterized in that described n equals 4.

6. high-performance according to claim 1, high integration DC/DC stepup transformer, it is characterized in that described switching mode booster circuit (3) comprises by three PMOS pipe M1, M2, M3 and the four-way switch that NMOS pipe M4 forms, the source electrode of M1 links to each other with the drain electrode of M2 and links to each other with the end of capacitor C s, the source electrode of M3 links to each other with the drain electrode of M4 and links to each other with the other end of capacitor C s, M1, M2, the substrate of M3 meets metal capacitance C1 respectively, C2, the positive pole of C3, metal capacitance C1, C2, the negative pole of C3 and M1, the drain electrode of M3 all links to each other with input voltage vin, M2, be connected with the parallel circuits of capacitor C L and resistance R L between the source electrode of M4, and the source ground of M4, the grid of M1 connects a phase clock signal of described not overlapping clock signal generating circuit (2), M2, M3, the grid of M4 all connects another phase clock signal of described not overlapping clock signal generating circuit (2), and the source electrode of M2 is the voltage output end Vout of described switching mode booster circuit (3).