CN101814835B - Control circuit suitable for DCM mode of Buck DC-DC converter - Google Patents
Control circuit suitable for DCM mode of Buck DC-DC converter Download PDFInfo
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- CN101814835B CN101814835B CN 201010141733 CN201010141733A CN101814835B CN 101814835 B CN101814835 B CN 101814835B CN 201010141733 CN201010141733 CN 201010141733 CN 201010141733 A CN201010141733 A CN 201010141733A CN 101814835 B CN101814835 B CN 101814835B
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Abstract
The invention belongs to the technical field of integrated circuits, in particular relates to a control circuit suitable for a discontinuous current mode (DCM) of a Buck DC-DC converter. The control circuit comprises a comparator, a D trigger provided with a direct-set terminal, an AND gate and an XOR gate. The comparator checks whether an inductive current of the Buck DC-DC converter has a negative value, and if an inductive current of the Buck DC-DC converter has a negative value, a pull-down tube of the Buck DC-DC converter is switched off by using the D trigger and the XOR gate so that a path from inductive current of the Buck DC-DC converter to the ground is cut off, and the efficiency of the Buck DC-DC converter is improved. The function of the AND gate is to determine whether the control circuit adopts a DCM mode. Compared with other DCM control circuits, the DCM control circuit of the invention has the characteristics of simple structure, low power consumption, reliable function and good application prospect.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to the control circuit of a kind of Buck of being applicable to (the step-down switching power circuit of non-isolation) DC-DC Converter in DCM pattern.
Background technology
Now, the consumer electronics technology is in high-speed development period.People are to consumption electronic product, and particularly the demand of portable, battery powered class consumption electronic product grows with each passing day.Along with the progress at full speed of semiconductor process techniques and the consumer continuous reinforcement to the product function demand, the scale of product chips is also in continuous expansion.This must cause the increase of chip power-consumption, thereby greatly reduces the service time of product battery.For handheld device, be one of problem of being concerned about the most of consumer the service time of battery.Owing to the variation along with service time of the output voltage of battery changes, therefore need power management chip to provide stable supply voltage to inner circuit, so the efficient of power management chip becomes a very important problem.Low-power consumption has become one of factor that power management chip must consider.
Power management chip is one of chip necessary in the battery supply set, in battery supply set, such as mobile phone, PDAs etc., they are to be in standby mode the most of the time, that is to say, load current at this time is lower, battery does not need for internal circuit provides too many electric current, so the efficient of power management chip is particularly important in this case.Cell voltage generally is to change to 4.2V from 2.7V, and the supply voltage of device interior integrated circuit is generally 1.8V, even lower, so the power management chip that needs generally is Buck DC-DC converter.And Buck DC-DC converter mainly is comprised of integrated circuit control section and external inductance and electric capacity.
For Buck DC-DC converter, in the situation that low current load, if be in continuous current mode (CCM always, continuous current mode), when inductive current when negative, inductive current will directly be moved ground to by the lower trombone slide of power management chip the inside, and the load of not flowing through, a greatly waste to the efficient of power management chip like this, so the situation of inductive current for bearing occurring, just adopt DCM pattern (cutout pattern), cut off inductive current to the path on ground, electric current in the inductance is stored on inductance and the electric capacity rather than by dischargeing in vain, so just can greatly improves the efficient of power management chip under the low load current condition.The present invention proposes a kind of novel DCM control circuit, have simple in structurely, be easy to realize to have stronger application potential.
Summary of the invention
The object of the invention is to propose a kind of new control circuit that is applicable to Buck DC-DC Converter in DCM pattern, to improve the efficient of Buck DC-DC converter, cater to the trend of current low consumption circuit design to satisfy the demand for development of following electronic product.
The power stage topological structure of BuckDC-DC converter as shown in Figure 4, the power tube Mp among Fig. 4, Mn be respectively by two non-overlapping clock Vp, Vn control.Avoided like this Mp, the situation of simultaneously conducting of Mn reduces unnecessary power consumption, raises the efficiency.When upper trombone slide conducting, provide electric current by upper trombone slide for load, as shown in Figure 5; During instantly trombone slide conducting, the energy that is stored by inductance and electric capacity provides electric current for load, and this moment, the SW point voltage was negative value, as shown in Figure 6; If load current is less, the electric current that flows through inductance after a period of time will be reverse, and the electric charge on the electric capacity provides energy for load on one side, on one side through inductance, lower trombone slide releases energy, at this moment the SW point voltage be on the occasion of, as shown in Figure 7, this is a greatly waste for efficient.
A kind of new control circuit that is applicable to Buck DC-DC Converter in DCM pattern that the present invention proposes by comparator, with the d type flip flop of set end, forms with door and XOR gate, and physical circuit as shown in Figure 1.Wherein: comparator 1 is to use the metal-oxide-semiconductor source as input, and its advantage is to compare generating positive and negative voltage.Two power tube Mp, Mn drain terminal signal SW and ground Vss connect respectively the positive and negative terminal of comparator, and the output voltage V c of comparator is as the clock input of d type flip flop 2, and the set end of d type flip flop is controlled by not calibrated original clock Vn, and data input pin meets high level Vdd; The output of d type flip flop and DCM control end are input to and door 3, and Output rusults and not calibrated original clock Vn be input to two input XOR gate 4, so just can obtain the clock control signal Vnn of trombone slide Mn under the Buck DC-DC converter, trombone slide Mp clock signal Vp and not calibrated original clock Vn non-overlapping clock signal each other on the converter.
Comparator adopts the input of MOS source, and afterbody is that inverter is to improve driving force.
With the d type flip flop of set end, use the output Vc of comparator as clock control signal, high level Vdd inputs as data, and not calibrated original clock Vn is as asserts signal.
Utilize the control signal that realizes whether adopting the DCM pattern with door, with an input signal of door be enable signal En, decide the output signal Vc of comparator whether effective, thereby judge whether to adopt the DCM pattern.
Among the present invention, draw power tube Mp source to connect input voltage vin on the Buck DC-DC inverter power level, drain terminal links to each other with drop-down power tube Mn drain terminal, drop-down power tube Mn pipe source ground signalling Vss.Inductance L one end and Mp, Mn pipe drain terminal links to each other, and the inductance L other end links to each other with load capacitance C and load current Iload, and the other end ground signalling Vss of load capacitance C, load current Iload also flow to ground Vss.In lower trombone slide Mn conducting phase, comparator is SW point voltage and Vss point voltage relatively, when in lower trombone slide Mn conducting phase, the SW point voltage occur from negative value on the occasion of upset, a saltus step from low to high will appear in comparator output Vc so, this saltus step is input to the clock end of d type flip flop, and the set end of d type flip flop is to be controlled by the disjoint signals Vn with upper trombone slide Mp, trombone slide conducting phase on non-, d type flip flop set end are high, the d type flip flop normal operation.The data input pin of d type flip flop connects high level, in this stage, also is the stage of lower trombone slide Mn conducting, if there is the SW voltage of ordering by negative value become on the occasion of, output will become height so, when asserts signal Vn was low level, output was set to low level.So in lower trombone slide conducting phase, if the SW point occur on the occasion of, namely inductive current becomes negative value, and within this stage, the output of d type flip flop will be high level so, the non-overlapping clock of it and upper trombone slide clock Vc is input to XOR gate, output signal Vnn is input to the lower trombone slide Mn of BuckDC-DC converter, just can realize when inductive current is negative value, and lower trombone slide turn-offs, and the energy on the electric capacity is wasted by lower trombone slide, thereby improve the efficient of Buck DC-DC converter.Utilize simultaneously one and door, control and whether make the DCM circuit effective, when En signal when being high, the output of d type flip flop can enter XOR gate, and when the En signal when low, be output as low so with door, the output of d type flip flop does not enter XOR gate, this moment, the output of XOR gate only was exactly the non-overlapping clock Vn of upper trombone slide, that realize by its control is CCM but not DCM, so the effect of En signal is to select to make Buck DC-DC converter be operated in CCM or DCM, realizes the configurable of circuit.
Comparator adopts the signal input of metal-oxide-semiconductor source among the present invention, as shown in Figure 2, so just can realize input signal be on the occasion of with the comparison of negative value, afterbody employing inverter is with the driving force of raising circuit.
Description of drawings
Fig. 1 .DCM control circuit and Buck DC-DC inverter power level integrated circuit figure.
Comparator circuit figure in Fig. 2 .DCM control circuit.
Non-overlapping clock timing diagram in Fig. 3 .DCM control circuit.
The power stage topological structure of Fig. 4 .Buck DC-DC converter.
Current conditions on Fig. 5 .Buck DC-DC converter during the trombone slide conducting.
Under Fig. 6 .Buck DC-DC converter during the trombone slide conducting, situation during the inductive current forward flow.
Under Fig. 7 .Buck DC-DC converter during the trombone slide conducting, situation during the inductive current forward flow.
Embodiment
Below in conjunction with accompanying drawing the present invention is further detailed.
As shown in Figure 1, the Buck DC-DC Converter in DCM control circuit of mentioning among the present invention, it comprises comparator, with the d type flip flop of set end, with door and two input XOR gate.Draw power tube Mp source to connect input voltage vin on the Buck DC-DC inverter power level, drain terminal links to each other with drop-down power tube Mn drain terminal, Mn pipe source ground signalling Vss.Inductance L one end and Mp, Mn pipe drain terminal links to each other, and the inductance L other end links to each other with load capacitance C and load current Iload, and the other end ground signalling Vss of load capacitance C, load current Iload also flow to ground Vss.
In the control circuit: the positive and negative terminal input of comparator is respectively two power tube Mp, Mn drain terminal signal SW and earth signal Vss, the output voltage V c of comparator is as the input of the clock end CLK of d type flip flop, the set end S of d type flip flop is controlled by not calibrated original clock Vn, and data input pin D meets high level Vdd.The output Q of d type flip flop and DCM control enable signal En are input to and door, and Output rusults and not calibrated original clock Vn be input to two input XOR gate, so just can obtain the clock control signal Vnn of trombone slide Mn under the Buck DC-DC inverter power level, trombone slide Mp clock signal Vp and not calibrated original clock Vn non-overlapping clock signal each other on the converter.
As shown in Figure 2, provided a kind of implementation method of comparator among Fig. 1.M1～M9 forms by the NMOS pipe.Comparator is to manage M3 with NMOS, and the source of M2 is as positive-negative input end, and its advantage is to compare generating positive and negative voltage.Bias current I1 flows to the drain terminal of M1 pipe, and the drain terminal of M1 pipe and grid end short circuit produce bias voltage, and bias voltage is received the M2 pipe from the grid of M1 pipe, the grid of M3 pipe and M7 pipe, the source ground connection of M1 pipe; M2 pipe, the drain terminal of M3 pipe connect respectively load M4 pipe, and the drain terminal of M5 pipe, M4 pipe, the grid of M5 pipe are connected together and link to each other with M4 pipe drain terminal, the M4 pipe, and the source electrode of M5 pipe meets supply voltage Vdd; M3 pipe and M5 pipe drain terminal connect the grid of M6 pipe, and the drain electrode of the drain electrode of M6 pipe and M7 pipe is connected together, M6, and the source electrode of M7 pipe meets respectively Vdd and Vss; M6, the drain electrode of M7 pipe and M8 pipe, the M9 tube grid connects together, the M8 pipe, M9 pipe source electrode meets respectively Vdd and Vss, the M8 pipe, M9 manages the as a comparison output Vout of device that is connected together that drains, and afterbody is the driving force that can be increased comparator by the inverter that M8 pipe and M9 pipe consist of.
As shown in Figure 3, provided non-overlapping clock signal Vp among Fig. 1, the sequential chart of Vn.The t1 that delays time among the figure, t2 has guaranteed upper trombone slide Mp and the not simultaneously conducting of Mn of Buck DC-DC inverter power level.
As shown in Figure 4, be the power stage topological structure of Buck DC-DC converter, on draw power tube Mp source to connect input voltage vin, drain terminal links to each other with drop-down power tube Mn drain terminal, Mn pipe source ground signalling Vss.Inductance L one end and Mp, Mn pipe drain terminal links to each other, and the inductance L other end links to each other with load capacitance C and load current Iload, and the other end ground signalling Vss of load capacitance C, load current Iload also flow to ground Vss.In the situation that there is not the DCM control circuit, this moment Mp, the grid control signal of Mn pipe meets respectively non-overlapping clock Vp, Vn.When upper trombone slide conducting, provide electric current by upper trombone slide for load, as shown in Figure 5; During instantly trombone slide conducting, the energy that is stored by inductance and electric capacity provides electric current for load, and this moment, the SW point voltage was negative value, as shown in Figure 6; If load current is less, the electric current that flows through inductance after a period of time will be reverse, and the electric charge on the electric capacity provides energy for load on one side, on one side through inductance, lower trombone slide releases energy, at this moment the SW point voltage be on the occasion of, as shown in Figure 7, this is a greatly waste for efficient.
If DCM control circuit shown in employing Fig. 1, then when load current is larger, as shown in Figure 6, when inductive current be on the occasion of, the SW voltage of ordering is negative value so, the d type flip flop of DCM control circuit is output as low level, so the control signal Vnn of the lower trombone slide of BuckDC-DC converter is identical with Vn, when inductive current reverse, as shown in Figure 7 current flowing situation will appear in a certain moment of lower trombone slide conducting, so the SW voltage of ordering will become on the occasion of, so at this moment, the comparator of control circuit will be exported high level among Fig. 1.When the set end S of d type flip flop is input as when low, d type flip flop is output as low level, and set end S is input as when high, the d type flip flop normal operation, and rising edge triggers.Because at this moment Vn is in high level, so the input signal Vdd of d type flip flop will be sent to output, output Q end becomes high level by low level, until that set end S is input as is low, output Q end signal becomes low signal again.If En is high, this section high level will be imported into XOR gate so, carry out XOR with the Vn signal, so at this moment, output low level, turn-off the lower trombone slide Mn of Buck DC-DC converter, thereby realized DCM, the electric charge on the electric capacity can't be lost by lower trombone slide, thereby improved the efficient of Buck DC-DC converter.
The En signal to add fashionable realization configurable, when the En signal when low, the control signal Vnn of lower trombone slide is identical during just with Vn, form non-overlapping clock with Vp exactly, the purpose of non-overlapping clock is in order to prevent two power tube Mp, and simultaneously conducting of Mn is to reduce unnecessary power consumption.The operating state of this moment is exactly the operating state of CCM (continuous current mode) so, so control by a digital signal En, just can realize that Buck DC-DC converter is gone up in working order configurable, can better save power consumption to compare the DCM state, raise the efficiency.
The DCM control circuit of the Buck DC-DC converter that the present invention proposes, simple in structure, low in energy consumption, area is little, has good application prospect.
Claims (5)
1. control circuit that is applicable to Buck DC-DC Converter in DCM pattern, it is characterized in that: this control circuit comprises comparator (1), with the d type flip flop (2) of set end, with door (3) and two input XOR gate (4);
Wherein: comparator (1) is as input with the metal-oxide-semiconductor source; Signal SW is the points of common connection signal of the drain terminal of the drain terminal of power tube Mp and power tube Mn, signal SW and ground Vss connect respectively the positive and negative terminal of comparator (1), the output voltage V c of comparator (1) is as the clock input of d type flip flop (2), the set end of d type flip flop is controlled by not calibrated original clock Vn, and data input pin meets supply voltage Vdd; The output of d type flip flop and DCM control end are input to and door (3), be input to two input XOR gate (4) with door (3) Output rusults and not calibrated original clock Vn, obtain the clock control signal Vnn as the power tube Mn of trombone slide under the BuckDC-DC converter, as the power tube Mp clock signal Vp of trombone slide on the converter and not calibrated original clock Vn non-overlapping clock signal each other.
2. the control circuit that is applicable to Buck DC-DC Converter in DCM pattern according to claim 1 is characterized in that: comparator adopts the input of metal-oxide-semiconductor source, and afterbody is inverter.
3. the control circuit that is applicable to Buck DC-DC Converter in DCM pattern according to claim 1, it is characterized in that: with the d type flip flop of set end, with the output voltage V c of comparator as clock control signal, high level Vdd inputs as data, and not calibrated original clock Vn is as asserts signal.
4. the control circuit that is applicable to Buck DC-DC Converter in DCM pattern according to claim 1, it is characterized in that: utilize the control signal that realizes whether adopting the DCM pattern with door, with an input signal of door be enable signal En, decide the output voltage V c of comparator whether effective, thereby judge whether to adopt the DCM pattern.
5. the control circuit that is applicable to Buck DC-DC Converter in DCM pattern according to claim 1, it is characterized in that described comparator is comprised of 9 NMOS pipe M1～M9, wherein, bias current I1 flows to the drain terminal of NMOS pipe M1, drain terminal and the grid end short circuit of NMOS pipe M1 produce bias voltage, bias voltage terminates to the grid of NMOS pipe M2, NMOS pipe M3 and NMOS pipe M7, the source ground connection of NMOS pipe M1 from the grid of NMOS pipe M1; The drain terminal of NMOS pipe M2, NMOS pipe M3 connects respectively the drain terminal of NMOS pipe M4, NMOS pipe M5, and the grid of NMOS pipe M4, NMOS pipe M5 is connected together and links to each other with NMOS pipe M4 drain terminal, and the source electrode of NMOS pipe M4, NMOS pipe M5 meets supply voltage Vdd; NMOS pipe M3 and NMOS pipe M5 drain terminal connect the grid of NMOS pipe M6, and the drain electrode of the drain electrode of NMOS pipe M6 and NMOS pipe M7 is connected together, and the source electrode of NMOS pipe M6, NMOS pipe M7 meets respectively Vdd and Vss; NMOS pipe M6 drain electrode, NMOS pipe M7 drain electrode, NMOS pipe M8 grid and NMOS pipe M9 grid connect together, NMOS pipe M8, NMOS pipe M9 source electrode meets respectively Vdd and Vss, NMOS pipe M8, the NMOS pipe M9 drain electrode as a comparison output voltage V c of device that is connected together, afterbody is the inverter that is made of NMOS pipe M8 and NMOS pipe M9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010141733 CN101814835B (en) | 2010-04-08 | 2010-04-08 | Control circuit suitable for DCM mode of Buck DC-DC converter |
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| CN 201010141733 CN101814835B (en) | 2010-04-08 | 2010-04-08 | Control circuit suitable for DCM mode of Buck DC-DC converter |
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| CN101814835B true CN101814835B (en) | 2013-04-10 |
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| CN104105267A (en) * | 2014-07-28 | 2014-10-15 | 鹰星精密工业（深圳）有限公司 | High-efficiency and low-cost non-isolated light-emitting diode (LED) constant current driver |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540548A (en) * | 2008-03-19 | 2009-09-23 | 斯沃奇集团研究和开发有限公司 | Method of controlling a dc-dc converter in discontinuous mode |
| US20100001706A1 (en) * | 2008-07-01 | 2010-01-07 | International Rectifier Corporation | Converter having pwm ramp adjustable in discontinuous mode operation |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4621636B2 (en) * | 2005-07-14 | 2011-01-26 | 株式会社東芝 | Power supply device and control method thereof |
| US7911193B2 (en) * | 2008-06-30 | 2011-03-22 | Infineon Technologies Austria Ag | Discontinuous conduction mode control circuit and method for synchronous converter |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540548A (en) * | 2008-03-19 | 2009-09-23 | 斯沃奇集团研究和开发有限公司 | Method of controlling a dc-dc converter in discontinuous mode |
| US20100001706A1 (en) * | 2008-07-01 | 2010-01-07 | International Rectifier Corporation | Converter having pwm ramp adjustable in discontinuous mode operation |
Non-Patent Citations (1)
| Title |
|---|
| 邹雪城等.一款新颖的适用于Buck型芯片的反转保护电路.《计算机与数字工程》.2007,第35卷(第10期), * |
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