CN103208862A - Timing control circuit for switching capacitor dynamic switch and control method thereof - Google Patents
Timing control circuit for switching capacitor dynamic switch and control method thereof Download PDFInfo
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Abstract
A timing control circuit for a switching capacitor dynamic switch includes a first time generator and a second time generator. The first generator includes a first capacitor. The first time generator determines a first time by charging to the first capacitor. The second time generator includes a second capacitor. The first time generator is connected to the second time generator. When the first time ends, the second time generator determines a second time by discharging to the second capacitor.
Description
Technical field
Embodiment is open about a kind of switching type capacitor dynamic switch time control circuit.
Background technology
The utilization of power management chip (Power Management IC) on portable type electronic product at present more and more widely, from mobile phone, personal digital assistant (Personal Digital Assistant, PDA) or even mobile computer, power management all is a very big and important problem.In power management chip, the DC-DC electric pressure converter is the most common circuit.In the operation of DC-DC electric pressure converter, be that power transistor (Power MOS) the do switching of bridge about utilizing provides stable output voltage, yet output current can be because the relation of the continuous switching of Power MOS can produce ripple (ripple).
And control mode has quite a lot of different mode at different operating modes and demand.General common control method has two kinds of pulse duration adjustment (pulse width modulation) and pulse frequency adjustment (pulse frequency modulation), the former fixed frequency and the responsibility cycle of adjusting pulse change the control switch signal, the latter then opens or the time of closing fixing, but the mode of adjustment switch periods frequency is carried out the responsibility cycle change of equivalence.
DC-DC electric pressure converter for low-power consumption, in the design of controller, because so the low discontinuous conduction mode (discontinuous conduction mode) that often adopts of average output current is operated, therefore can require to reduce power consumption in operation as far as possible, so adopt non-control (PFM) the replacement frequency of deciding frequently of deciding commonly used to control (PWM) to reduce unnecessary switch periods, the switch cost that reduces on the whole DC-DC converter circuit reaches whole efficiency lifting or the purpose of lower input energy usable range.
When the DC-DC electric pressure converter was operated at discontinuous conduction mode, inductive current can be down to zero level and be cut with output or input when discharge, make the discontinuous event of output current be called discontinuous conducting.And when inductive current reaches zero level, can be because the situation of inductive current adverse current might take place in the relation of inductive current ripple (inductor current ripple), this moment, the energy of inductive current adverse current was to be provided by output capacitance, current path is to flow to the waste that zero potential (VSS) further can form energy by output, or the mode that causes electric current must pass through diode current flow owing to switching time is inaccurate flow to output, so the conversion efficiency of DC-DC electric pressure converter will reduce.Generation for fear of this problem, in general DC-DC electric pressure converter, all can add the zero current detection circuit, when inductive current is about to adverse current takes place, can be by the rapid reporting system circuit of zero current detection circuit, the transistor that meeting forms on the counter-current path is closed, avoid the generation of adverse current, to keep high conversion rate.Therefore closing switch accurately just becomes most important parts in the control.
And making on switching time accurately, have and use zero current detection circuit (zero currentdetection), or utilize the input and output voltage relation and calculate the mode of bridge switch time up and down.
Summary of the invention
Embodiment proposes a kind of switching type capacitor dynamic switch time control circuit.
A kind of switching type capacitor dynamic switch time control circuit according to embodiment comprises very first time generator and second time generator; Wherein, very first time generator has been drawn together one first electric capacity, and the charging of very first time generator by first electric capacity is to determine a very first time; Second time generator includes one second electric capacity, and second time generator is connected with very first time generator, when the very first time finishes, second time generator by second capacitance discharges to determine for one second time.
A kind of switching type capacitor dynamic switch duration control method according to embodiment includes: one first electric capacity responds first electric current and charges; Judge the charged state of this first electric capacity, stop charging when the charging voltage of this first electric capacity surpasses a threshold value, it is a very first time that this first electric capacity begins to charge to the timing definition that stops to charge; Produce an end that was pressed on one second electric capacity in a minute, one second electric current that this second electric capacity responds this second current source generation discharges; Judge this second capacitance discharges state, stop discharge when this second capacitance discharges voltage hangs down what one threshold value, it was one second time that this second electric capacity begins to be discharged to the timing definition that stops to discharge.
Above about embodiment explanation and the explanation of following execution mode in order to demonstration and spirit and the principle of explaining embodiment, and provide claims further to explain.
Description of drawings
Fig. 1 is the disclosed switching type capacitor dynamic switch of embodiment time control circuit.
Fig. 2 A, Fig. 2 B, Fig. 2 C are the operation chart of the disclosed switching type capacitor dynamic switch of embodiment time control circuit.
Fig. 3 is the sequential chart of the disclosed switching type capacitor dynamic switch of embodiment time control circuit.
Fig. 4 is the disclosed correcting circuit of embodiment.
Fig. 5 is the disclosed approximation circuit of the embodiment of Fig. 4.
[main element symbol description]
10.................................. very first time generator
20.................................. second time generator
30.................................. input current source
40.................................. correcting circuit
41.................................. control logic
42.................................. control circuit
43.................................. approximation circuit
44 inverters
431................................ buffer
432................................ buffer
433................................ buffer
434................................ buffer
435................................ buffer
436................................ multiplexer
437................................ D flip-flop
452................................ gate
453................................ gate
454................................ gate
455................................ gate
456................................ gate
457................................ gate
C1.................................. first electric capacity
C2.................................. second electric capacity
C3.................................. the 3rd electric capacity
M1................................. the first transistor
M2................................. transistor seconds
M3................................. the 3rd transistor
M4................................. the 4th transistor
M5................................. the 5th transistor
M6................................. the 6th transistor
M7................................. the 7th transistor
M8................................. the 8th transistor
S1.................................. first switch
S2.................................. second switch
S3.................................. the 3rd switch
S4.................................. the 4th switch
S5.................................. the 5th switch
S6.................................. the 6th switch
S7.................................. minion is closed
Vb.................................. grid bias power supply
Vin................................. supply voltage
Vss................................ earthing potential
The VGN external voltage
VC1................................. voltage
VC2................................. branch pressure voltage
Clk................................. clock signal
En.................................. enable signal
Comp transition signal
Lock.............................. locking signal
Embodiment
Below in execution mode, be described in detail detailed features and the advantage of embodiment, its content is enough to make those skilled in the art to understand the technology contents of embodiment and implements according to this, and according to the disclosed content of this specification, claims and accompanying drawing, those skilled in the art can understand purpose and the advantage that embodiment is correlated with easily.The detailed description of following embodiment is not in order to limit the scope relevant with embodiment anyways.
Please refer to Fig. 1, for the disclosed switching type capacitor dynamic switch of embodiment time control circuit, do not use the comparator and the operational amplifier that consume energy in the prior art.Below for convenience of description, will be called for short time control circuit.
Time control circuit is made up of a very first time generator 10 and one second time generator 20.Very first time generator 10 is electrically connected between a supply voltage Vin and the earthing potential Vss, second time generator 20 is electrically connected between supply voltage Vin and the earthing potential Vss equally, the representative value of earthing potential Vss is 0 volt, supply voltage Vin also is expressed as Vcc, represent one and be higher than 0 volt current potential, be generally 5 volts.
Very first time generator 10 includes one first capacitor C 1 and that one first current source, is connected with first current source and is connected in one first comparator between first current source and first capacitor C 1, and first comparator determines first current source to a very first time of first capacitor C, 1 charging.Second time generator 20 is connected with very first time generator.Second time generator includes one second current source, and is connected in one second comparator and the 3rd capacitor C 3 that is connected with second capacitor C 2 between second current source and second capacitor C 2, when the very first time finishes, second capacitor C 2 is discharged by second current source, and by one second time of second comparator to determine that second capacitor C 2 is discharged.First comparator, second comparator, first current source, second current source here will illustrate in following embodiment.
In addition, time control circuit also includes an input current source 30, is connected with this very first time generator 10, and wherein second current source in first current source in the very first time generator 10 and second time generator 20 is the image current in input current source 30.In an embodiment, the input current source is made up of first switch S 1 that a first transistor M1, a transistor seconds M2 and are connected in the first transistor M1 and transistor seconds M2.The first transistor M1 is a PMOS transistor, and transistor seconds M2 is a nmos pass transistor.The source electrode of the first transistor M1 is connected to supply voltage Vin, and drain electrode is connected to first end of one first switch S 1, and grid is connected to a grid bias power supply Vb.The drain electrode of transistor seconds M2 is connected to second end of first switch S 1, and source electrode is connected to earthing potential Vss, and grid and drain electrode link together.When first switch S 1 controlled and when closing, to form guiding path this moment, the first transistor M1 and a transistor seconds M2 will produce image current in order to the current mirroring circuit in follow-up very first time generator 10 and one second time generator 20 as the input current source.
Use a plurality of switches among the embodiment, in fact these switches can utilize transistor or gate to implement, its unlatching or close the control that is subjected to logical circuit.In an embodiment, close if mention switch, refer to that the path at this switch place forms path, if be switch open, refer to that then the path formation at this switch place is opened circuit.
Below the embodiment of explanation very first time generator 10 and second time generator 20 forms and running.
Very first time generator 10 includes the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, first capacitor C 1, second switch S2 and the 3rd switch S 3.The 3rd transistor M3 is a PMOS transistor, the 4th transistor M4 is a PMOS transistor, the 5th transistor M5 is a nmos pass transistor, and the source electrode of the source electrode of the 3rd transistor M3 and the 4th transistor M4 all is connected to supply voltage Vin, and two transistorized grids also all are connected to a grid bias power supply Vb.First end of second switch S2 is connected with the drain electrode of the 3rd transistor M3, and second end of second switch S2 is connected to first end of first capacitor C 1, and second end of first capacitor C 1 is connected to earthing potential Vss.The drain electrode of the 4th transistor M4 is connected to the drain electrode of the 5th transistor M5, and the source electrode of the 5th transistor M5 is connected to earthing potential Vss, and the grid of the 5th transistor M5 is connected between first end of second end of second switch S2 and first capacitor C 1.First end of the 3rd switch S 3 is connected between first end of second end of second switch S2 and first capacitor C 1, and second end of the 3rd switch S 3 is connected to earthing potential Vss.
In very first time generator 10, the 3rd transistor M3 is used as current source and uses, that is aforesaid first current source.When closing, the 3rd transistor M3 can respond from the input current source of the first transistor M1 and produce a mirror electric current when second switch S2 is controlled, with to 1 charging of first capacitor C.And the 5th transistor M5 is the embodiment as aforesaid first comparator, the 5th transistor M5 and 1 collocation of first capacitor C, determining a very first time, that is the charging interval when the charge volume of first capacitor C 1 surpasses the threshold voltage Vth of conducting of the 5th transistor M5 be the very first time.When the disclosed time control circuit of embodiment was applied to DC-DC converter, the very first time perhaps was called the bridge opening time for inductance is carried out the charging interval.
Second time generator 20 includes the 6th transistor M6, the 7th transistor M7 and the 8th transistor M8, second capacitor C 2, the 3rd capacitor C 3, the 4th switch S 4, the 5th switch S 5, the 6th switch S 6 and minion are closed S7.The 6th transistor M6 is nmos pass transistor, and the 7th transistor M7 is the PMOS transistor, and the 8th transistor M8 is nmos pass transistor.The grid of the 7th transistor M7 is connected to grid bias power supply Vb, and source electrode is connected to supply voltage Vin, and drain electrode is connected to the drain electrode of the 8th transistor M8, and the source electrode of the 8th transistor M8 is connected to earthing potential Vss.The grid of the 8th transistor M8 is connected to first end of the 6th switch S 6 and first end that minion is closed S7, and second end that minion is closed S7 is connected to earthing potential Vss.Second end of the 5th switch S 5 is connected to the drain electrode of the 6th transistor M6, and the source electrode of the 6th transistor M6 is connected to earthing potential Vss, and grid is connected to the grid of transistor seconds M2.
The 3rd capacitor C 3 and the 4th switch S 4 are parallel with one another, first end of the 3rd capacitor C 3 is connected to supply voltage Vin, first end of the 4th switch S 4 is connected to supply voltage Vin, second end of second end of the 3rd capacitor C 3 and the 4th switch S 4 is connected to each other, and be connected to first end of the 5th switch S 5, second end of the 5th switch S 5 is connected to first end of second capacitor C 2, and second end of second capacitor C 2 is connected to earthing potential Vss.
In second time generator 20, the 6th transistor M6 is the embodiment as aforesaid second current source, the 8th transistor M8 is the embodiment as aforementioned second comparator, and the 8th transistor M8 and second capacitor C 2 and 3 collocation of the 3rd capacitor C are to determine for one second time.When the disclosed time control circuit of embodiment was applied to DC-DC converter, second time was called an inductance and carries out discharge time, perhaps was called the following bridge opening time.
Embodiment of the present disclosure with the fixed current source to the electric capacity charge or discharge to transistorized conducting voltage (threshold voltage), and utilize the 5th transistor M5, the 8th transistor M8 as a comparison device use.When the disclosed time control circuit of embodiment is applied to DC-DC converter, and when the inductance in DC-DC converter is charged state, first current source can be to the action of charging of first capacitor C 1, and the time T of its charge cycle (on period)
ONCan be obtained by following formula:
After time by control electric current and electric capacity generation charge cycle, second capacitor C in second time generator
2With the 3rd capacitor C
3Discharge time after the control charge cycle is finished, and its branch pressure voltage V
C2Value can be obtained by following formula:
By the branch pressure voltage value, add the magnitude of voltage Vin of sampling input terminal voltage, utilize the constant-current discharge capacitor C
2On voltage can obtain the time T of inductive discharge cycle (off period)
OFFAs shown in the formula:
Composite type (1) (2) (3) and input and output voltage, can discharge and recharge the balanced type of time at discontinuous conduction mode stable state inductance, and the parameter alpha of adjusting capacitance partial pressure can be adjusted the dividing potential drop content, and then the different input and output voltage relation of foundation produces correct discharge time to cooperate the charging interval, to reach the Zero Current Switch of low-loss.
Below cooperate Fig. 2 A to Fig. 2 C and Fig. 3 that operating process of the present invention is described.
Signal CPout is the control signal of control circuit of the present invention, and when the present invention was applied to DC-DC converter, this signal can come from comparator.Signal CPout can be considered as control signal herein.
In time control circuit, one has first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4, the 5th switch S 5, the 6th switch S 6 and minion closes S7, wherein second switch S2 and the 5th switch S 5 can be opened or close simultaneously, and the 3rd switch S 3, the 4th switch S 4 and minion pass S7 can open simultaneously or close, the unlatching of first switch S 1 or pass close close the unlatching of S7 with the 3rd switch S 3, the 4th switch S 4 and minion or close opposite, that is.When the 3rd switch S 3, the 4th switch S 4 and minion were closed S7 for unlatching, first switch S 1 was for closing.Therefore in an embodiment, first switch S 1 is connected with an inverter (not shown), just can uses identical logic control signal to control first switch S 1, the 3rd switch S 3, the 4th switch S 4 and minion and close S7.
When first switch S 1 was closed, the 3rd transistor M3 was used as current source and uses, and will can be seen the voltage V of first capacitor C 1 this moment to 1 charging of first capacitor C by Fig. 3
C1Rise step by step.In this stage, the 3rd switch S 3, the 4th switch S 4 and minion are closed S7 for opening.And the voltage of second capacitor C 2 maintains the full state that fills.When the voltage of first capacitor C 1 surpassed the conducting voltage Vth of the 5th transistor M5, second switch S2 namely opened to form and opens circuit, and the charging stage of first capacitor C 1 this moment finishes, and enters discharge regime.
At discharge regime, second switch S2, the 5th switch S 5 are opened, so current source no longer charges first capacitor C, 1 discharge this moment to first capacitor C 1.At this moment, the 3rd switch S 3, the 4th switch S 4 and minion pass S7 still keep unlatching.The 6th switch S 6 is closed, and makes second capacitor C 2 to discharge, and when the discharge of second capacitor C 2 was lower than the 8th transistorized conducting voltage Vth, this discharge regime finished, and enters process segment (Idle period).
In process segment, second switch S2 and the 5th switch S 5 are opened, the 3rd, the 4th and minion close S7 and close, the 6th switch S 6 is opened, in this stage, the two the hold C2 and the 3rd capacitor C 3 can discharge offs.
When the disclosed time control circuit of Application Example during to DC-DC converter, these analog integrated circuit itself may have the unmatched influence of element and circuit system reaction required time of delay.Because different Zero Current Switch points can cause inductive current discharge condition in the different DC-DC converter, if the change that inductive current does not drain as yet or the inductive current discharge excessively produces for inductance both end voltage value.Therefore can utilize this change in voltage and by circuit as: inverter, comparator or amplifier carry out the detection of voltage status.Adjust the capacitance of the 3rd capacitor C 3 after tested, use the dividing potential drop ratio of adjusting, and then produce value discharge time that cooperates technology or postpone variation, inaccurate with this discharge time of revising technology and delay, more promote the power consumption efficiency of system.
Therefore in one embodiment, also include one group of correcting circuit 40, be connected with the 3rd capacitor C 3, as the correction mechanism of the inaccurate inductive discharge time that makes a variation for technology or postpone to produce.Correcting circuit is used for changing the capacitance of the 3rd electric capacity, so that non-ideal effects errors such as input and technology can be proofreaied and correct discharge time by changing the 3rd capacitance.Therefore, the capacitance of the 3rd capacitor C 3 is can be controlled in one embodiment.
In one embodiment, correcting circuit 40 can be realized with five continuous approximation circuit (successiveapproximation register).Include a control logic 41, a control circuit 42 and an approximation circuit 43 in the correcting circuit 40 shown in Figure 4.Control logic 41 is subjected to external voltage V
GNControl, and clock signal Clk gives approximation circuit 43.Control logic 41 is subjected to the control of an activation signal En simultaneously.The output of 42 responses of control circuit approximation circuit 43 is to determine to increase or reduce the capacitance of the 3rd capacitor C 3.
Approximation circuit 43 shown in Figure 5 is one 5 continuous approximation circuit, includes five buffers 431,432,433,434,435, multiplexers 436 and a D flip-flop 437.Buffer 432,433,434,43 disposes a gate 452,453,454,455 respectively and cooperates running.Gate 456,457 also is set in addition.These gates all are or door.The inverter 44 that is used as inductor produces a transition signal Comp, zero current detection (the zero currentdiction that this signal indication is long or too short, ZCD), transition signal Comp can be stored in buffer 431,432,433,434,435 respectively.In five, and highest significant position (Most Significant Bit, MSB) ZA[4] be set at high-voltage level (that is logical one), in order to the carrying out of beginning correction program.By among the figure as can be known, the transition signal Comp that inverter 44 is exported is subjected to an external voltage V
LXDetermine.If external voltage V
LXBe low voltage level, transition this moment signal Comp will become high-voltage level and input in the approximation circuit 43 to increase the capacitance of the 3rd capacitor C 3.V
LXFor low voltage level is represented the too short shut-in time.Otherwise, if external voltage V
LXBe high-voltage level, transition this moment signal Comp will become low voltage level, to reduce the capacitance of the 3rd capacitor C 3.V
LXFor high-voltage level is represented the long shut-in time.After relatively, the buffer in the running will trigger next buffer with control code ZA[n-1 at present] set 1 for, in order to the carrying out of next one comparison, receive transition signal Comp simultaneously, whether to determine with output signal ZA[n] set 0 or 1 for.Through will determining the level of least significant bit after five times the comparison, and D flip-flop 437 can be configured to high-voltage level and pinning.At this moment, the state of approximation circuit 43 will be held to export the correct shut-in time.And input can will be similar to circuit 43 lockings or make the least significant bit of approximation circuit 43 continue running from a locking signal Lock of external circuit.
In another embodiment, correcting circuit can utilize climbing method (mountain climbing method) or counter (up down counter) realizes correcting circuit up and down.
The switching type capacitor dynamic switch time control circuit of embodiment of the present disclosure, it mainly is made of one group of switch capacitor circuit and control logic, it can reach extremely low power consumption, need not use amplifier or comparator circuit to pin or judge voltage signal, only use a transistor device as a comparison that the control current source is arranged, can produce the switching signal of the bridge up and down of balance, make inductive current be discharged to zero level accurately, make the DC-DC electric pressure converter can high efficiencyly operate in discontinuous conduction mode (discontinuous conduction mode).In addition, circuit is closed fully and is not consumed energy when static state, and the control electric current maintains low-down levels of current by circuit when opening.
What specify is, though the starting point of the time control circuit that embodiment proposes is the problem for the power consumption that will solve the DC-DC electric pressure converter and zero current control circuit, be not to mean the present invention can only be applied to the DC-DC electric pressure converter.As long as need to have the control that discharges and recharges in the circuit, all can use the present invention.
Claims (16)
1. switching type capacitor dynamic switch time control circuit includes:
Very first time generator includes first electric capacity, and the charging of this very first time generator by this first electric capacity is to determine a very first time; And
Second time generator includes second electric capacity, and this second time generator is connected with this very first time generator, when this finishes very first time, this second time generator by this second capacitance discharges to determine for one second time.
2. circuit as claimed in claim 1, wherein should also include first current source and first comparator by very first time generator, this first electric capacity is connected with this first current source, this first comparator is connected between this first current source and this first electric capacity, wherein, this first comparator determines this first current source to this very first time of this first electric capacity charging.
3. circuit as claimed in claim 2, wherein this second time generator also includes second current source and second comparator, this second electric capacity is connected with this second current source, this second comparator is connected with this second electric capacity, wherein when this very first time finishes, this second electric capacity is by the discharge of this second current source, and by this second comparator to determine this second time of this second capacitor discharge.
4. circuit as claimed in claim 3 wherein also includes the 3rd electric capacity, is connected with this second electric capacity.
5. circuit as claimed in claim 4 wherein also includes correcting circuit, be connected with the 3rd electric capacity, this correcting circuit in order to the capacitance that changes the 3rd electric capacity to proofread and correct discharge time.
6. circuit as claimed in claim 3 wherein also includes the input current source, is connected with this very first time generator, wherein this first current source and this second current source image current that is this input current source.
7. circuit as claimed in claim 6, wherein this input current source comprises the first transistor, transistor seconds and first switch, is connected between this first transistor and this transistor seconds.
8. circuit as claimed in claim 7, this first current source in wherein should very first time generator is one the 3rd transistor.
9. circuit as claimed in claim 8 wherein should also include by very first time generator:
Second switch is connected between this transistor seconds and this first electric capacity;
The 3rd switch is connected with this first electric capacity parallel connection and with this second switch; And
The 4th transistor is connected with the 3rd transistor.
10. circuit as claimed in claim 9, wherein this first comparator is the 5th transistor, is connected with the 4th transistor.
11. circuit as claimed in claim 4, wherein this second current source in this second time generator is one the 6th transistor.
12. circuit as claimed in claim 11, wherein this second time generator also includes:
The 4th switch is connected with the 3rd electric capacity;
The 5th switch is connected between this second electric capacity and the 3rd electric capacity;
The 6th switch is connected between this second electric capacity of the 6th transistor AND gate;
Minion is closed, and is connected with this second electric capacity; And
The 7th transistor is connected with the 3rd electric capacity and this second comparator.
13. circuit as claimed in claim 12, wherein this second comparator is the 8th transistor, is connected with the 7th transistor.
14. a switching type capacitor dynamic switch duration control method includes:
First electric capacity responds one first electric current and charges;
Judge the charged state of this first electric capacity, stop charging when the charging voltage of this first electric capacity surpasses a first threshold, it is a very first time that this first electric capacity begins to charge to the timing definition that stops to charge;
Produce an end that was pressed on second electric capacity in a minute, one second electric current that this second electric capacity responds this second current source generation discharges;
Judge this second capacitance discharges state, stop discharge when this second capacitance discharges voltage is lower than one second threshold value, it was one second time that this second electric capacity begins to be discharged to the timing definition that stops to discharge.
15. method as claimed in claim 14, also include the step that an input current is provided, so that responding this input current, first current source produces this first electric current, and make this this input current of second current response produce this second electric current, the image current that this first electric current and this second electric current are this input current.
16. method as claimed in claim 14 also includes an aligning step, in order to the capacitance that changes one the 3rd electric capacity be connected with this second electric capacity with correction discharge time.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201261587425P | 2012-01-17 | 2012-01-17 | |
| US61/587,425 | 2012-01-17 |
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| CN103208862A true CN103208862A (en) | 2013-07-17 |
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| TW (1) | TW201332288A (en) |
Cited By (1)
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| CN106300967A (en) * | 2015-05-11 | 2017-01-04 | 远翔科技股份有限公司 | Drive circuit according to capacitor charge and discharge toggle switch |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110932729B (en) * | 2018-09-20 | 2023-04-07 | 瑞昱半导体股份有限公司 | Successive approximation register analog-to-digital converter and control circuit thereof |
| US11323034B2 (en) * | 2020-03-03 | 2022-05-03 | Himax Technologies Limited | Voltage generating circuit with timing skipping control |
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- 2012-05-18 TW TW101117916A patent/TW201332288A/en unknown
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| CN1592052A (en) * | 2003-09-05 | 2005-03-09 | 台达电子工业股份有限公司 | Variable frequency PWM controller circuit |
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| US20070040588A1 (en) * | 2005-08-17 | 2007-02-22 | Brandt Braswell | Amplifier circuit for double sampled architectures |
| US20080030181A1 (en) * | 2006-08-04 | 2008-02-07 | Kuo Ping Liu | Control circuit and method for a constant on-time PWM switching converter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106300967A (en) * | 2015-05-11 | 2017-01-04 | 远翔科技股份有限公司 | Drive circuit according to capacitor charge and discharge toggle switch |
| CN106300967B (en) * | 2015-05-11 | 2018-09-14 | 台湾类比科技股份有限公司 | Driving circuit according to capacitor charge and discharge toggle switch |
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| Publication number | Publication date |
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| TW201332288A (en) | 2013-08-01 |
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Application publication date: 20130717 |