TW201332288A - Switch capacitor dynamic on off time control circuit and control method thereof - Google Patents

Abstract

A switch capacitor dynamic on off time control circuit comprises a first time generator and a second time generator connected to the first generator. The first time generator includes a first capacitor, while the second time generator includes a second capacitor. A first time is determined through the charge of the first capacitor. When the first time ends, the second time generator determines a second time through the discharge of the second capacitor.

Description

Switching capacitor dynamic switching time control circuit and control method thereof

Embodiments disclose a switched capacitor dynamic switching time control circuit.

At present, Power Management ICs have become more and more widely used in portable electronic products. From mobile phones, personal digital assistants (PDAs), and even notebook computers, power management is a very A big and important topic. DC/DC voltage converters are the most common circuits in power management ICs. In the operation of the DC/DC voltage converter, the power transistor (Power MOS) of the upper and lower bridges is used for switching to provide a stable output voltage. However, the output current will generate ripples due to the continuous switching of the Power MOS. .

The control method has quite a number of different ways for different modes of operation and needs. Commonly used control methods include pulse width modulation and pulse frequency modulation. The former fixes the frequency and adjusts the duty cycle of the pulse to change the control switch signal. The latter can be fixedly turned on. Either the time of the shutdown, but adjust the cycle frequency of the switch to make the equivalent duty cycle change.

For the low-power DC/DC voltage converter, in the design of the controller, since the average output current is low, the discontinuous conduction mode operation is often used, so the operation is required to reduce the power consumption as much as possible. Use non-fixed frequency control (PFM) to replace the commonly used fixed frequency control (PWM) to reduce unnecessary The desired switching period reduces the switching losses across the DC/DC converter circuit to achieve overall efficiency gain or lower input energy usable range.

When the DC/DC voltage converter is operated in the discontinuous conduction mode, the inductor current will drop to the zero level when it is discharged and cut off from the output or the input, so that the output current is discontinuous, so it is called discontinuous conduction. When the inductor current reaches the zero level, the inductor current may flow backward due to the inductor current ripple. At this time, the energy of the inductor current backflow is provided by the output capacitor, and the current path is The flow from the output to the zero potential (VSS) further causes waste of energy, or the current must flow through the diode to the output due to inaccurate switching time, so the conversion efficiency of the DC/DC voltage converter is Will decrease. In order to avoid this problem, a zero current detection circuit is added to the general DC/DC voltage converter. When the inductor current is about to flow backward, the zero current detection circuit will quickly notify the system circuit that a reverse flow path will be formed. The upper transistor is turned off to avoid the occurrence of backflow to maintain high conversion efficiency. Therefore, the accurate closing of the switch becomes the most important part of the control.

In the manufacture of accurate switching time, there is a method of using zero current detection or calculating the switching time of the upper and lower bridges by using the relationship between input and output voltages.

The embodiment proposes a switched capacitor dynamic switching time control circuit.

A switched capacitor dynamic switching time control circuit according to an embodiment, comprising a first time generator and a second time generator; wherein the first time generator comprises a first capacitor, the first time generator is charged by the first capacitor to determine a first time; the second time generator includes a second capacitor, and the second time generator is coupled to the first time generator, when the first At the end of the time, the second time generator is charged by the second capacitor to determine a second time.

According to an embodiment, a switching capacitor dynamic switching time control method includes: a first capacitor responding to a first current for charging; determining a state of charge of the first capacitor, when a charging voltage of the first capacitor exceeds a threshold value Stop charging, the time when the first capacitor starts charging to stop charging is defined as a first time; generating a voltage divider to one end of a second capacitor, the second capacitor responding to the second current source generating a second current Discharging; determining the discharge state of the second capacitor, stopping discharging when the discharge voltage of the second capacitor exceeds a threshold value, and defining a time during which the second capacitor begins to discharge to stop discharging is defined as a second time.

The above description of the embodiments and the following embodiments are intended to illustrate and explain the spirit and principles of the embodiments, and to provide further explanation of the scope of the patent application.

The detailed features and advantages of the embodiments are described in detail in the following detailed description of the embodiments of the embodiments of the invention. The objects and advantages associated with the embodiments can be readily understood by those skilled in the art. The following detailed description of the embodiments is not intended to limit the scope of the embodiments.

Please refer to FIG. 1 for the switched capacitor dynamic switching time control circuit disclosed in the embodiment, without using the energy consuming comparator and operational amplifier in the prior art. Hereinafter, for convenience of explanation, the time control circuit will be referred to simply.

The time control circuit is composed of a first time generator 10 and a second time generator 20. The first time generator 10 is electrically connected between a power supply voltage Vin and a ground potential Vss, and the second time generator 20 is also electrically connected between the power supply voltage Vin and the ground potential Vss, and the ground potential Vss is a typical value. At 0 volts, the supply voltage Vin is also expressed as Vcc, representing a potential above 0 volts, typically 5 volts.

The first time generator 10 includes a first current source, a first capacitor C1 connected to the first current source, and a first comparator connected between the first current source and the first capacitor C1. A comparator determines a first time that the first current source charges the first capacitor C1. The second time generator 20 is coupled to the first time generator. The second time generator includes a second current source, a second comparator connected between the second current source and the second capacitor C2, and a third capacitor C3 connected to the second capacitor C2. At the end of the time, the second capacitor C2 is discharged through the second current source, and the second comparator determines the discharge of the second capacitor C2 for a second time. The first comparator, the second comparator, the first current source, and the second current source herein will be described in the following embodiments.

In addition, the time control circuit further includes an input current source 30 coupled to the first time generator 10, wherein the first current source in the first time generator 10 and the second current source in the second time generator 20 Mirror image for input current source 30 flow. In an embodiment, the input current source is composed of a first transistor M1, a second transistor M2, and a first switch S1 connected to the first transistor M1 and the second transistor M2. The first transistor M1 is a PMOS transistor, and the second transistor M2 is an NMOS transistor. The source of the first transistor M1 is connected to the power supply voltage Vin, the drain is connected to the first end of a first switch S1, and the gate is connected to a bias power supply Vb. The drain of the second transistor M2 is connected to the second terminal of the first switch S1, the source is connected to the ground potential Vss, and the gate is connected to the drain. When the first switch S1 is controlled to be turned off, a conduction path will be formed at this time, and the first transistor M1 and the second transistor M2 will be regarded as input current sources to facilitate the subsequent first time generator 10 and a second time. The current mirror circuit in generator 20 produces a mirror current.

Multiple switches are used in the embodiments, which can actually be implemented using transistors or logic gates that are turned on or off controlled by logic circuitry. In the embodiment, if the switch is turned off, it means that the path where the switch is located forms a path, and if the switch is turned on, it means that the path where the switch is located forms an open circuit.

The composition and operation of the embodiment of the first time generator 10 and the second time generator 20 are explained below.

The first time generator 10 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, a second switch S2, and a third switch S3. The third transistor M3 is a PMOS transistor, the fourth transistor M4 is a PMOS transistor, the fifth transistor M5 is an NMOS transistor, the source of the third transistor M3 and the fourth transistor M4 The sources are all connected to the power supply voltage Vin, and the gates of the two transistors are also connected to a bias power supply Vb. First of the second switch S2 The terminal is connected to the drain of the third transistor M3, the second end of the second switch S2 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the ground potential Vss. The drain of the fourth transistor M4 is connected to the drain of the fifth transistor M5, the source of the fifth transistor M5 is connected to the ground potential Vss, and the gate of the fifth transistor M5 is connected to the second of the second switch S2. The terminal is between the first end of the first capacitor C1. The first end of the third switch S3 is connected between the second end of the second switch S2 and the first end of the first capacitor C1, and the second end of the third switch S3 is connected to the ground potential Vss.

In the first time generator 10, the third transistor M3 is used as a current source, that is, the aforementioned first current source. When the second switch S2 is controlled to be turned off, the third transistor M3 generates a mirror current in response to the input current source from the first transistor M1 to charge the first capacitor C1. The fifth transistor M5 is used as the first embodiment of the first comparator, and the fifth transistor M5 is matched with the first capacitor C1 to determine a first time, that is, when the charging amount of the first capacitor C1 exceeds the fifth. The charging time at the threshold voltage Vth at which the transistor M5 is turned on is the first time. When the time control circuit disclosed in the embodiment is applied to the DC/DC converter, the first time is the charging time of the inductor, or the upper bridge opening time.

The second time generator 20 includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, a second capacitor C2, a third capacitor C3, a fourth switch S4, a fifth switch S5, and a sixth switch S6. And a seventh switch S7. The sixth transistor M6 is an NMOS transistor, the seventh transistor M7 is a PMOS transistor, and the eighth transistor M8 is an NMOS transistor. The gate of the seventh transistor M7 is connected to the bias power supply Vb, the source is connected to the power supply voltage Vin, and the drain is connected to the eighth transistor M8. The drain of the eighth transistor M8 is connected to the ground potential Vss. The gate of the eighth transistor M8 is connected to the first end of the sixth switch S6 and the first end of the seventh switch S7, and the second end of the seventh switch S7 is connected to the ground potential Vss. The second end of the fifth switch S5 is connected to the drain of the sixth transistor M6, the source of the sixth transistor M6 is connected to the ground potential Vss, and the gate is connected to the gate of the second transistor M2.

The third capacitor C3 and the fourth switch S4 are connected in parallel with each other. The first end of the third capacitor C3 is connected to the power supply voltage Vin, the first end of the fourth switch S4 is connected to the power supply voltage Vin, and the second end of the third capacitor C3 is connected to the second capacitor C3. The second ends of the four switches S4 are connected to each other and connected to the first end of the fifth switch S5, the second end of the fifth switch S5 is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected To the ground potential Vss.

In the second time generator 20, the sixth transistor M6 is an embodiment of the second current source described above, and the eighth transistor M8 is used as an embodiment of the second comparator, the eighth transistor M8 and the second The capacitor C2 and the third capacitor C3 are matched to determine a second time. When the time control circuit disclosed in the embodiment is applied to a DC/DC converter, the second time is called an inductor for discharging time, or is called a bridge opening time.

Embodiments of the present disclosure use a fixed current source to charge or discharge a capacitor to a threshold voltage of a transistor, and use a fifth transistor M5 and an eighth transistor M8 as comparators. When the time control circuit disclosed in the embodiment is applied to the DC/DC converter, and the inductance in the DC/DC converter is in a charging state, the first current source charges the first capacitor C1 while charging The time _{ON of the} on period can be obtained by:

After the charging current and the capacitor generate the charging period, the second capacitor C ₂ and the third capacitor C ₃ in the second time generator control the discharging time after the completion of the charging cycle, and the divided voltage V _C2 value can be obtained from get:

A divided voltage value of the sampled input voltage plus the voltage value Vin, the voltage by the constant current discharge of capacitor C ₂ is obtained inductive discharge period (off period) of time T _OFF by the following formula:

The integrated equations (1), (2) and (3) and the input and output voltages can be used to balance the steady-state inductor charging and discharging time in the discontinuous conduction mode, and the parameter α for adjusting the capacitance partial pressure can adjust the partial pressure content, and then according to different The input-output voltage relationship produces the correct discharge time to match the charging time to achieve a low-loss zero-current switch.

Hereinafter, the operation of the present invention will be described with reference to "2A" to "2C" and "3".

The signal CPout is a control signal for controlling the circuit of the present invention. When the present invention is applied to a DC/DC converter, this signal can come from the comparator. Here, the signal CPout can be regarded as a control signal.

In the time control circuit, there are a total of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh open S7, wherein the second switch S2 and the fifth switch S5 are simultaneously turned on or off, and the third switch S3, the fourth switch S4, and the seventh switch S7 are simultaneously turned on or off, and the first switch S1 is turned on or off. The third switch S3, the fourth switch S4, and the seventh switch S7 are turned on or off instead, that is,. When the third switch S3, the fourth switch S4, and the seventh switch S7 are turned on, the first switch S1 is turned off. Therefore, in the embodiment, by connecting the first switch S1 with an inverter (not shown), the first switch S1, the third switch S3, the fourth switch S4, and the seventh can be controlled by using the same logic control signal. Switch S7.

When the first switch S1 is turned off, the third transistor M3 is used as a current source. At this time, the first capacitor C1 is charged. From FIG. 3, it can be seen that the voltage V _{C1 of the} first capacitor _C1 gradually rises. At this stage, the third switch S3, the fourth switch S4, and the seventh switch S7 are turned on. The voltage of the second capacitor C2 is maintained in a fully charged state. When the voltage of the first capacitor C1 exceeds the turn-on voltage Vth of the fifth transistor M5, the second switch S2 is turned on to form an open circuit. At this time, the charging phase of the first capacitor C1 ends and enters the discharging phase.

During the discharge phase, the second switch S2 and the fifth switch S5 are turned on, so the current source no longer charges the first capacitor C1, and the first capacitor C1 is discharged. At this time, the third switch S3, the fourth switch S4, and the seventh switch S7 remain open. The sixth switch S6 is turned off so that the second capacitor C2 can be discharged, and when the second capacitor C2 is discharged lower than the turn-on voltage Vth of the eighth transistor, the discharge phase ends and enters the Idle period.

In the static phase, the second switch S2 and the fifth switch S5 are turned on, third, fourth And the seventh switch S7 is turned off, and the sixth switch S6 is turned on. At this stage, the second and second capacitors C2 and C3 are discharged.

When applying the time control circuit disclosed in the embodiment to the DC/DC converter, these analog integrated circuits themselves may have the effects of component mismatch and the delay time required for the system circuit to react. Since different zero current switching points will cause different inductor current discharge states in the DC/DC converter, if the inductor current has not been exhausted or the inductor current is excessively discharged, the voltage value across the inductor changes. Therefore, this voltage change can be utilized to detect the voltage state through a circuit such as an inverter, a comparator or an amplifier. After the detection, the capacitance value of the third capacitor C3 is adjusted, thereby adjusting the voltage division ratio, thereby generating a discharge time value that matches the process or delay variation, thereby correcting the inaccurate discharge time of the process and the delay, and improving the power consumption of the system. effectiveness.

Thus, in one embodiment, a set of correction circuits 40 is further included coupled to the third capacitor C3 as a correction mechanism for inaccurate inductor discharge times for process variations or delays. The correction circuit is used to change the capacitance value of the third capacitor to make non-ideal effect errors such as input and process, and the discharge time can be corrected by changing the third capacitance value. Therefore, the capacitance value of the third capacitor C3 can be adjusted in one embodiment.

In an embodiment, the correction circuit 40 can be implemented with a five-bit successive approximation register. The correction circuit 40 shown in FIG. 4 includes a control logic 41, a control circuit 42, and an approximation circuit 43. The control logic 41 is controlled by the external voltage V _GN and outputs a clock signal Clk to the approximation circuit 43. The control logic 41 is simultaneously controlled by the uniform energy signal En. Control circuit 42 then responds to the output of approximation circuit 43 to determine to increase or decrease the capacitance of third capacitor C3.

The approximation circuit 43 shown in FIG. 5 is a 5-bit continuous approximation circuit including five registers 431, 432, 433, 434, 435, a multiplexer 436, and a D-type flip-flop. 437. The registers 432, 433, 434, and 43 are respectively configured to cooperate with a logic gate 452, 453, 454, and 455. In addition, logic gates 456, 457 are also provided. These logic gates are either gates or gates. The inverter 44 used as the sensor generates a transition signal Comp, which indicates a zero current diction (ZCD) that is too long or too short, and the transition signal Comp is stored in the register 431, respectively. , 432, 433, 434, 435. Among the five bits, the Most Significant Bit (MSB) ZA[4] is set to a high voltage level (ie, logic 1) to facilitate the start of the calibration procedure. As can be seen from the figure, the transition signal Comp output by the inverter 44 is determined by an external voltage V _LX . If the external voltage V _LX is at a low voltage level, the transition signal Comp will become a high voltage level and input to the approximation circuit 43 to increase the capacitance value of the third capacitor C3. V _LX indicates a too short off time for low voltage levels. On the contrary, if the external voltage V _LX is at a high voltage level, the transition signal Comp will become a low voltage level at this time to lower the capacitance value of the third capacitor C3. V _LX is a high voltage level indicating an excessively long off time. After comparison, the currently operating scratchpad will trigger the next register to set the control code ZA[n-1] to 1, in order to facilitate the next comparison, and receive the transition signal Comp to determine Whether to set the output signal ZA[n] to 0 or 1. After five comparisons, the level of the least significant bit will be determined, and the D-type flip-flop 437 will be set to a high voltage level and locked. At this time, the state of the approximating circuit 43 will be maintained to output the correct off time. A lock signal Lock input from the external circuit locks the approximation circuit 43 or causes the least significant bit of the approximation circuit 43 to continue to operate.

In another embodiment, the correction circuit can implement the correction circuit using a mountain climbing method or an up down counter.

The switched capacitor dynamic switching time control circuit of the embodiment of the present disclosure is mainly composed of a set of switched capacitor circuits and control logic, which can achieve extremely low power consumption without using an amplifier or a comparator circuit to lock Or to judge the voltage signal, only use a transistor with a control current source as a comparator to create a switching signal that balances the upper and lower bridges, so that the inductor current can be accurately discharged to zero level, so that DC/DC The voltage converter can operate in a discontinuous conduction mode with high efficiency. In addition, the circuit is completely closed when quiescent and does not consume energy, and the current is controlled to keep the circuit at a very low current level when turned on.

In particular, although the timing of the time control circuit proposed in the embodiment is to solve the problem of the power consumption of the DC/DC voltage converter and the zero current control circuit, it is not intended that the present invention can only be applied to DC/ DC voltage converter. The present invention can be applied as long as the charge and discharge control is required in the circuit.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

10‧‧‧First time generator

20‧‧‧Second time generator

30‧‧‧Input current source

40‧‧‧correction circuit

41‧‧‧Control logic

42‧‧‧Control circuit

43‧‧‧ Approximate circuit

44‧‧‧ reverser

431‧‧‧ 存存器

432‧‧‧ 存存器

433‧‧‧ 存存器

434‧‧‧ register

435‧‧‧ register

436‧‧‧Multiplexer

437‧‧‧D type flip-flop

452‧‧‧Logic gate

453‧‧‧Logic gate

454‧‧‧Logic gate

455‧‧‧Logic gate

456‧‧‧Logic gate

457‧‧‧Logic gate

C1‧‧‧first capacitor

C2‧‧‧second capacitor

C3‧‧‧ third capacitor

M1‧‧‧first transistor

M2‧‧‧second transistor

3‧‧‧ Third transistor

M4‧‧‧ fourth transistor

M5‧‧‧ fifth transistor

M6‧‧‧ sixth transistor

M7‧‧‧ seventh transistor

M8‧‧‧ eighth transistor

S1‧‧‧ first switch

S2‧‧‧ second switch

S3‧‧‧ third switch

S4‧‧‧fourth switch

S5‧‧‧ fifth switch

S6‧‧‧ sixth switch

S7‧‧‧ seventh switch

Vb‧‧‧ bias power supply

Vin‧‧‧Power supply voltage

Vss‧‧‧ Ground potential

V _GN ‧‧‧External voltage

V _C1 ‧‧‧ voltage

V _C2 ‧‧ ‧ voltage divider

Clk‧‧‧ clock signal

En‧‧‧Enable signal

Comp‧‧‧Transition signal

Lock‧‧‧Lock signal

FIG. 1 is a switched capacitor dynamic switching time control circuit disclosed in the embodiment.

FIG. 2 is a schematic diagram of the operation of the switched capacitor dynamic switching time control circuit disclosed in the embodiment.

FIG. 3 is a timing diagram of the switched capacitor dynamic switching time control circuit disclosed in the embodiment.

Figure 4 is a correction circuit disclosed in the embodiment.

Figure 5 is an approximation of the circuit disclosed in the embodiment of Figure 4.

10‧‧‧First time generator

20‧‧‧Second time generator

30‧‧‧Input current source

C1‧‧‧first capacitor

C2‧‧‧second capacitor

C3‧‧‧ third capacitor

M1‧‧‧first transistor

M2‧‧‧second transistor

M3‧‧‧ third transistor

M4‧‧‧ fourth transistor

M5‧‧‧ fifth transistor

M6‧‧‧ sixth transistor

M7‧‧‧ seventh transistor

M8‧‧‧ eighth transistor

S1‧‧‧ first switch

S2‧‧‧ second switch

S3‧‧‧ third switch

S4‧‧‧fourth switch

S5‧‧‧ fifth switch

S6‧‧‧ sixth switch

S7‧‧‧ seventh switch

Vb‧‧‧ bias power supply

Vin‧‧‧Power supply voltage

Vss‧‧‧ Ground potential

V _C1 ‧‧‧ voltage

V _C2 ‧‧ ‧ voltage divider

Claims (16)

A switching capacitor dynamic switching time control circuit includes: a first time generator comprising a first capacitor, the first time generator is charged by the first capacitor to determine a first time; and a second The time generator includes a second capacitor, and the second time generator is connected to the first time generator. When the first time ends, the second time generator passes the charging of the second capacitor to determine a first time. Two times. The circuit of claim 1, wherein the first time generator further comprises a first current source and a first comparator, the first capacitor being connected to the first current source, the first comparator being connected And between the first current source and the first capacitor, wherein the first comparator determines the first time that the first current source charges the first capacitor. The circuit of claim 2, wherein the second time generator further comprises a second current source and a second comparator, the second capacitor being coupled to the second current source, the second comparator The second capacitor is connected, wherein when the first time is over, the second capacitor is discharged through the second current source, and the second comparator determines the second time of discharging the second capacitor. The circuit of claim 3, further comprising a third capacitor coupled to the second capacitor. The circuit of claim 4, further comprising a correction circuit coupled to the third capacitor, the correction circuit for changing a capacitance value of the third capacitor to correct a discharge time. The circuit of claim 3, further comprising an input current source coupled to the first time generator, wherein the first current source and the second current source are mirror currents of the input current source . The circuit of claim 6, wherein the input current source comprises a first transistor, a second transistor, and a first switch connected to the first transistor and the second transistor. between. The circuit of claim 3, wherein the first current source in the first time generator is a third transistor. The circuit of claim 8, wherein the first time generator further comprises: a second switch connected between the second transistor and the first capacitor; a third switch, and the third A capacitor is connected in parallel and in series with the second switch; and a fourth transistor is coupled to the third transistor. The circuit of claim 8, wherein the first comparator is a fifth transistor connected to the fourth transistor. The circuit of claim 3, wherein the second current source in the second time generator is a sixth transistor. The circuit of claim 11, wherein the second time generator further comprises: a fourth switch connected to the third capacitor; a fifth switch connected to the second capacitor and the third capacitor a sixth switch connected between the sixth transistor and the second capacitor; a seventh switch coupled to the second capacitor; and a seventh transistor coupled to the third capacitor and the second comparator. The circuit of claim 12, wherein the second comparator is an eighth transistor connected to the seventh transistor. A switching capacitor dynamic switching time control method includes: a first capacitor responding to a first current for charging; determining a state of charge of the first capacitor, stopping when a charging voltage of the first capacitor exceeds a first threshold Charging, the time when the first capacitor starts charging until the charging is stopped is defined as a first time; generating a voltage divider to one end of a second capacitor, the second capacitor responding to the second current source generating a second current for discharging Determining the discharge state of the second capacitor, stopping discharging when the discharge voltage of the second capacitor exceeds a second threshold, and defining a time during which the second capacitor begins to discharge to stop discharging is defined as a second time. The method of claim 14, further comprising the step of providing an input current such that a first current source returns the input current to generate the first current, and the second current is returned to the input current to generate the current a second current, the first current and the second current being a mirror current of the input current. The method of claim 14, further comprising a correcting step of changing a capacitance value of a third capacitor connected to the second capacitor to correct the discharge time.