CN101764517B - Positive-negative dual power supply system based on single input - Google Patents
Positive-negative dual power supply system based on single input Download PDFInfo
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Abstract
The invention provides a positive-negative dual power supply system based on the single input, which comprises a power supply input unit, a synchronous clock generation unit and a positive/negative voltage output circuit, wherein the power supply input unit is used for generating an input DC power supply, the synchronous clock generation unit is used for generating first clock signals and second clock signals which are synchronous, the first/second clock signals are positive/negative, the positive/negative voltage output circuit comprises a first/second output end and a first/second reference ground end, and is used for utilizing the first/second clock signals as the synchronous clock signals and generating first/second voltage between the first/second output end and the first/second reference ground end according to the input DC power supply, the fist reference ground end is connected to the second output end to be used as a common reference ground end of the system, the first output end is used as a positive power supply output end of the system for outputting the first DC power supply, and the second reference ground end is used as the negative power supply output end of the system for outputting the second DC power supply.
Description
Technical field
The present invention relates to field of power supplies, be specifically related to a kind of positive-negative dual power supply system based on single input.
Background technology
Each electronic product possibly be made up of various piece, is exactly all to can't do without electric power system but a common ground is arranged.In the design electric power system, all can receive various restrictions under a lot of situation, this has much relations with the practical application condition.One of them relatively more typical restriction is exactly to import power supply.
For instance, when system needs one+5V and one-5V duplex feeding, and the two-way power supply can have multiple design altogether the time.But be input as under the situation of single DC power supply when limiting, and whole system altogether, then possibility has just lacked a lot (this is a more common application).Usually the most frequently used is that scheme is (positive supply produces fairly simple, only is the example explanation with the negative supply), converts into-5V with a charge pump circuit general+5V.But the shortcoming of charge pump be load capacity too a little less than, generally be no more than 200mA, bigger a little circuit just can not support.Take all factors into consideration key elements such as cost, volume, performance, make up a suitable power-supply system and be not easy.
Summary of the invention
The technical problem that the present invention will solve provides a kind of positive-negative dual power supply system based on single input; Under the situation of single DC power supply input; Exportable positive and negative two-way DC power supply can be taken into account the needs of output loading capability, cost, voltage stability and volume simultaneously.
In order to address the above problem, the invention provides a kind of positive-negative dual power supply system based on single input, comprising:
Power input unit is used to produce input DC power;
The synchronised clock generating unit is used to produce first synchronous clock signal and second clock signal; Said first clock signal for just, the second clock signal is for negative;
The positive voltage output circuit, end is used for said first clock signal as synchronizing clock signals, according to said input DC power generation first voltage between said first output and first is held with reference to ground with comprising first output and first reference;
The negative voltage output circuit, end is used for said second clock signal as synchronizing clock signals, according to said input DC power generation second voltage between said second output and second is held with reference to ground with comprising second output and second reference;
The first reference ground end of said positive voltage output circuit is connected to second output of said negative voltage output unit, and as the common reference ground end of said system, first output is exported first DC power supply as the positive supply output of said system; The second reference ground end of said negative voltage output circuit is exported second DC power supply as the negative supply output of said system.
Further, said synchronised clock generating unit comprises:
Voltage stabilizing circuit, Schmidt trigger circuit and clock polarity reverse circuit;
Said voltage stabilizing circuit is used to provide chip power supply voltage to said Schmidt trigger circuit;
Said Schmidt trigger circuit is used for producing from concussion first clock signal of positive polarity;
Said clock polarity reverse circuit be used for according to said first clock signal produce identical with the first clock signal amplitude, phase place is identical, the second clock signal of negative polarity.
Further, said clock polarity reverse circuit comprises:
High-speed photoelectric coupler, first resistance and second resistance;
Said high-speed photoelectric coupler comprises input, output, collector electrode, Enable Pin and earth terminal;
Said collector electrode and Enable Pin meet said common reference ground end DGND through said second resistance; Said input receives said first clock signal, and receives said chip power supply voltage through said first resistance; Said earth terminal connects said negative supply output; Said output is used to export said second clock signal.
Further, said high-speed photoelectric coupler is the 6N137 chip; Input is pin 2 and 3, and output is a pin 6, and current collection is pin 8 very, and Enable Pin is a pin 7, and earth terminal is a pin 5.
Further, said positive voltage output circuit comprises a continuous BUCK circuit and a LC filter circuit;
Said negative voltage output circuit comprises the 2nd continuous BUCK circuit and the 2nd LC filter circuit;
Said first, second BUCK circuit respectively with first, second clock signal as synchronizing signal, be used for converting said input DC power into first, second square-wave signal with the speed-sensitive switch mode;
A said LC filter circuit is used for level and smooth said first square-wave signal, exports said first voltage;
Said the 2nd LC filter circuit is used for level and smooth said second square-wave signal, exports said second voltage.
Further, a said LC filter circuit comprises:
Inductance (L1), smothing filtering electric capacity (C3) and high-frequency filter capacitor (C4);
Said smothing filtering electric capacity (C3) and high-frequency filter capacitor (C4) parallel connection, the end after the parallel connection links to each other with first end of said inductance (L1), and as said first output, the other end is held with reference to ground as said first;
Second end of said inductance (L1) links to each other with the output of a said BUCK circuit;
Said the 2nd LC filter circuit comprises:
Inductance (L2), smothing filtering electric capacity (C8) and high-frequency filter capacitor (C9);
Said smothing filtering electric capacity (C8) and high-frequency filter capacitor (C9) parallel connection, the end after the parallel connection links to each other with first end of said inductance (L2), as said second output, and is connected to said first with reference to the ground end, and the other end is as the said second reference ground end;
Second end of said inductance (L2) links to each other with the output of said the 2nd BUCK circuit.
Further, said smothing filtering electric capacity (C3) and (C8) be electrochemical capacitor, its positive pole connect first end of said inductance L 1, L2 respectively.
Further, a said BUCK circuit comprises:
One boost chip, two diodes, a resistance, electric capacity (C1) and electric capacity (C5);
Said boost chip comprises synchronous pin, input pin, output pin, grounding pin, C pin and feedback pin;
Said synchronous pin receives said first clock signal through said electric capacity (C5), and links to each other with said grounding pin through said resistance;
Said input pin links to each other with said power input unit, receives said input DC power;
Said C pin links to each other with said output pin through said electric capacity (C1);
Said feedback pin is connected to second end of said inductance (L1);
Said output pin is connected to first end of said inductance (L1);
Said two diode parallel connections, anodal and said grounding pin links to each other, and negative pole links to each other with said output pin;
Said grounding pin is connected to said first with reference to the ground end.
Further, said the 2nd BUCK circuit comprises:
One boost chip, two diodes, a resistance, electric capacity (C6) and electric capacity (C10);
Said boost chip comprises synchronous pin, input pin, output pin, grounding pin, C pin and feedback pin;
Said synchronous pin receives said second clock signal through said electric capacity (C10), and links to each other with said grounding pin through said resistance;
Said input pin links to each other with said power input unit, receives said input DC power;
Said C pin links to each other with said output pin through said electric capacity (C6);
Said feedback pin is connected to second end of said inductance (L2);
Said output pin is connected to first end of said inductance (L2);
Said two diode parallel connections, anodal and said grounding pin links to each other, and negative pole links to each other with said output pin;
Said grounding pin is connected to said second with reference to the ground end.
In the technical scheme of the present invention, system is input as a direct-flow voltage regulation source, and output can provide one group of positive supply output and one group of negative supply output, and positive-negative power altogether; The present invention has low cost, small size, high-power and high-precision characteristics; Solved in the single supply input system; Requiring the output of positive and negative double track power supply that large load current all is provided and than the design challenges under the high stability situation, for similar application provides cost performance very high solution.Adopt the mode of reverse parallel connection BUCK chip in one embodiment of the present of invention; Through two synchronised clocks that polarity is opposite, frequency is identical; Both can control the voltage ripple frequency of output; Can also make the ripple current phase place of positive and negative two-way power supply of output opposite, thereby cancel out each other (absolute value reduction), improve the output stability of power supply; Because the BUCK circuit adopts the speed-sensitive switch principle to carry out power conversion, efficient is high, and the loss of system own is very little, and therefore the positive and negative two-way power supply of output all can be accomplished big electric current supply, breaks through the traditional design bottleneck.
Description of drawings
Fig. 1 is based on the schematic block diagram of the positive-negative dual power supply system of single input among the embodiment one;
Fig. 2 is the circuit diagram of clock polarity upset among the embodiment one;
Fig. 3 is the schematic block diagram of power supply output unit among the embodiment one.
Embodiment
To combine accompanying drawing and embodiment that technical scheme of the present invention is explained in more detail below.
Need to prove that if do not conflict, each characteristic among the embodiment of the invention and the embodiment can mutually combine, all within protection scope of the present invention.
Embodiment one, and a kind of positive-negative dual power supply system based on single input is as shown in Figure 1, comprising:
Power input unit is used to produce input DC power VIN;
The synchronised clock generating unit is used to produce first synchronous clock signal Sync clk1 and second clock signal Sync clk2; Said first clock signal for just, the second clock signal is for negative; Said first, second clock signal frequency is identical;
The power supply output unit comprises positive and negative voltage follower circuit;
Said positive voltage output circuit comprises the first output V
+ OutHold GND with first with reference to ground
+, be used for said first clock signal as synchronizing clock signals, according to said input DC power at the said first output V
+ OutHold GND with first with reference to ground
+Between produce first voltage;
Said negative voltage output circuit comprises the second output V
- OutHold GND with second with reference to ground
-, be used for said second clock signal as synchronizing clock signals, according to said input DC power at the said second output V
- OutHold GND with second with reference to ground
-Between produce second voltage;
The first reference ground end GND of said positive voltage output circuit
+Be connected to the second output V of said negative voltage output unit
- Out, as the common reference ground end DGND of said system;
The first output V of said positive voltage output circuit
+ OutAs the positive supply output of said system, export the first DC power supply VOUT+;
The second reference ground end of said negative voltage output circuit is exported the second DC power supply VOUT-as the negative supply output of said system.
It is thus clear that find out, in the present embodiment, said first, second DC power supply is respectively one group of positive and negative power supply altogether; The amplitude of said first, second DC power supply (absolute value) can but be not limited to equate.
Above-mentioned positive and negative voltage follower circuit connected mode is the reverse parallel connection mode, and the common input of said positive and negative voltage follower circuit is said input DC power VIN, and said input DC power VIN is reference with said reference ground end DGND also.
In the present embodiment; Can control the voltage ripple frequency of said positive and negative voltage follower circuit output through said first, second clock signal; Can also make the ripple current phase place of said first, second DC power supply of output opposite, thereby cancel out each other, improve output stability.
In the present embodiment, said synchronised clock generating unit specifically can comprise:
Voltage stabilizing circuit, Schmidt trigger circuit and clock polarity reverse circuit.
Said voltage stabilizing circuit is used to provide chip power supply voltage CLKVCC to said Schmidt trigger circuit;
Said Schmidt trigger circuit is used for producing from concussion first clock signal of positive polarity, frequency range 280KHZ～380KHZ;
Said clock polarity reverse circuit is used for producing according to said first clock signal second clock signal of negative polarity, and this second clock signal is identical with the first clock signal amplitude, phase place is identical, polarity is opposite.
In view of clock signal is a high speed signal; Adopt a high-speed photoelectric coupler to build said clock polarity reverse circuit; The input and output two-stage of high-speed photoelectric coupler is electric isolates fully, therefore, high-speed photoelectric coupler is exported collector electrode connect said common reference ground DGND; Emitter connects said negative supply output, promptly exportable and first clock signal polarity is opposite, frequency the is identical second clock signal; And the collector electrode pull-up resistor can be used to regulate the load capacity of output signal.
Said clock polarity reverse circuit specifically can comprise:
High-speed photoelectric coupler, first resistance R 1 and second resistance R 2;
Said high-speed photoelectric coupler comprises input, output, collector electrode, Enable Pin and earth terminal;
Said collector electrode and Enable Pin meet said common reference ground end DGND through said second resistance; Said input receives said first clock signal, and receives said chip power supply voltage CLKVCC through said first resistance; Said earth terminal connects said negative supply output; Said output is used to export said second clock signal.
Said high-speed photoelectric coupler can but be not limited to the 6N137 chip.
This moment is as shown in Figure 2, and the input of high-speed photoelectric coupler is pin 2 (AN) and pin 3 (CA), and output is pin 6 (OUT), and current collection is pin 8 (VCC) very, and Enable Pin is pin 7 (EN), and earth terminal is pin 5 (GND); Pin 1 and 4 need not.
In practical application, said high-speed photoelectric coupler specification can be selected as required; Corresponding different frequencies and load size also can be adjusted said second resistance second clock signal of output is satisfied the demand.
In the present embodiment, in the said power supply output unit, the core of said positive and negative voltage follower circuit is respectively first, second BUCK circuit, and said first, second BUCK circuit connects with the reverse parallel connection mode.
In practical application, can select suitable BUCK chip to build said first, second BUCK circuit according to output voltage needs, load current needs, also can use discrete component to realize.
Said positive voltage output circuit comprises a continuous BUCK circuit and a LC filter circuit;
Said negative voltage output circuit comprises the 2nd continuous BUCK circuit and the 2nd LC filter circuit;
Said first, second BUCK circuit respectively with first, second clock signal as synchronizing signal, be used for converting said input DC power VIN into first, second square-wave signal with the speed-sensitive switch mode;
A said LC filter circuit is used for level and smooth said first square-wave signal, exports said first voltage;
Said the 2nd LC filter circuit is used for level and smooth said second square-wave signal, exports said second voltage.
In the present embodiment, as shown in Figure 3, a said LC filter circuit specifically can comprise:
Said smothing filtering capacitor C 3 and high-frequency filter capacitor C4 parallel connection; End after the parallel connection links to each other with first end of said inductance L 1; As said first output (just said positive supply output), the other end is held (just said common reference ground end DGND) as said first with reference to ground;
Second end of said inductance L 1 links to each other with the output of a said BUCK circuit;
Said the 2nd LC filter circuit specifically can comprise:
Said smothing filtering capacitor C 8 and high-frequency filter capacitor C9 parallel connection; End after the parallel connection links to each other with first end of said inductance L 2; As said second output; And being connected to the said first reference ground end (common reference ground end DGND just), the other end is as the said second reference ground end (just said negative supply output);
Second end of said inductance L 2 links to each other with the output of said the 2nd BUCK circuit.
In the present embodiment, said smothing filtering capacitor C 3 can be electrochemical capacitor with C8, and its positive pole connects first end of said inductance L 1, L2 respectively.
In the present embodiment, a said BUCK circuit specifically can comprise:
One boost chip, diode D1, diode D2, a resistance, capacitor C 1 and capacitor C 5;
Said boost chip comprise synchronous pin (pin 5, SYNC), input pin (pin 2, IN), output pin (pin 1, SW), grounding pin (pin 4, GND), the C pin (pin 3, C) and feedback pin (pin 6, FB);
Said synchronous pin receives said first clock signal through said capacitor C 5, and links to each other with said grounding pin through said resistance;
Said input pin links to each other with said power input unit, receives said input DC power VIN;
Said C pin links to each other with said output pin through said capacitor C 1;
Said feedback pin is connected to second end of said inductance L 1;
Said output pin is connected to first end of said inductance L 1;
Said diode D1, D2 parallel connection, anodal and said grounding pin links to each other, and negative pole links to each other with said output pin;
Said grounding pin is connected to said first with reference to the ground end.
Said the 2nd BUCK circuit specifically can comprise:
One boost chip, diode D3, diode D4, a resistance, capacitor C 6 and capacitor C 10;
Said boost chip comprise synchronous pin (pin 5, SYNC), input pin (pin 2, IN), output pin (pin 1, SW), grounding pin (pin 4, GND), the C pin (pin 3, C) and feedback pin (pin 6, FB);
Said synchronous pin receives said first clock signal through said capacitor C 10, and links to each other with said grounding pin through said resistance;
Said input pin links to each other with said power input unit, receives said input DC power VIN;
Said C pin links to each other with said output pin through said capacitor C 6;
Said feedback pin is connected to second end of said inductance L 2;
Said output pin is connected to first end of said inductance L 2;
Said diode D3, D4 parallel connection, anodal and said grounding pin links to each other, and negative pole links to each other with said output pin;
Said grounding pin is connected to said second with reference to the ground end.
During practical application, also can adopt other physical circuit to realize.
In the present embodiment, the synchronous pin SYNC of boost chip is the synchronised clock pin in said first, second BUCK circuit.The one BUCK circuit is the output voltage reference data with said common reference ground end DGND; The 2nd BUCK circuit is the output voltage reference data with said negative supply output, also corresponding second DC power supply that becomes of the reference potential of its synchronizing signal.
In the present embodiment, by the second clock signal of negative polarity synchronizing signal as the 2nd BUCK circuit, first, second DC power supply and the ripple current phase place opposite, thereby can cancel out each other (absolute value reduction).Improved stability of power supply; Because said first, second BUCK circuit adopts the speed-sensitive switch principle to carry out power conversion, efficient is high, and the loss of system own is very little, and therefore first DC power supply and second DC power supply all can be accomplished big electric current supply, breaks through the traditional design bottleneck.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.
Claims (8)
1. the positive-negative dual power supply system based on single input is characterized in that, comprising:
Power input unit is used to produce input DC power;
The synchronised clock generating unit is used to produce first synchronous clock signal and second clock signal; Said first clock signal for just, the second clock signal is for negative;
The positive voltage output circuit, end is used for said first clock signal as synchronizing clock signals, according to said input DC power generation first voltage between said first output and first is held with reference to ground with comprising first output and first reference;
The negative voltage output circuit, end is used for said second clock signal as synchronizing clock signals, according to said input DC power generation second voltage between said second output and second is held with reference to ground with comprising second output and second reference;
The first reference ground end of said positive voltage output circuit is connected to second output of said negative voltage output unit, and as the common reference ground end of said system, first output is exported first DC power supply as the positive supply output of said system; The second reference ground end of said negative voltage output circuit is exported second DC power supply as the negative supply output of said system;
Said synchronised clock generating unit comprises:
Voltage stabilizing circuit, Schmidt trigger circuit and clock polarity reverse circuit;
Said voltage stabilizing circuit is used to provide chip power supply voltage to said Schmidt trigger circuit;
Said Schmidt trigger circuit is used for producing from concussion first clock signal of positive polarity;
Said clock polarity reverse circuit be used for according to said first clock signal produce identical with the first clock signal amplitude, phase place is identical, the second clock signal of negative polarity.
2. the system of claim 1 is characterized in that, said clock polarity reverse circuit comprises:
High-speed photoelectric coupler, first resistance and second resistance;
Said high-speed photoelectric coupler comprises input, output, collector electrode, Enable Pin and earth terminal;
Said collector electrode and Enable Pin meet said common reference ground end DGND through said second resistance; Said input receives said first clock signal, and receives said chip power supply voltage through said first resistance; Said earth terminal connects said negative supply output; Said output is used to export said second clock signal.
3. system as claimed in claim 2 is characterized in that:
Said high-speed photoelectric coupler is the 6N137 chip; Input is pin 2 and 3, and output is a pin 6, and current collection is pin 8 very, and Enable Pin is a pin 7, and earth terminal is a pin 5.
4. like each described system in the claim 1 to 3, it is characterized in that:
Said positive voltage output circuit comprises a continuous BUCK circuit and a LC filter circuit;
Said negative voltage output circuit comprises the 2nd continuous BUCK circuit and the 2nd LC filter circuit;
Said first, second BUCK circuit respectively with first, second clock signal as synchronizing signal, be used for converting said input DC power into first, second square-wave signal with the speed-sensitive switch mode;
A said LC filter circuit is used for level and smooth said first square-wave signal, exports said first voltage;
Said the 2nd LC filter circuit is used for level and smooth said second square-wave signal, exports said second voltage.
5. system as claimed in claim 4 is characterized in that, a said LC filter circuit comprises:
Inductance L 1, smothing filtering capacitor C 3 and high-frequency filter capacitor C4;
Said smothing filtering capacitor C 3 and high-frequency filter capacitor C4 parallel connection, the end after the parallel connection links to each other with first end of said inductance L 1, and as said first output, the other end is held with reference to ground as said first;
Second end of said inductance L 1 links to each other with the output of a said BUCK circuit;
Said the 2nd LC filter circuit comprises:
Inductance L 2, smothing filtering capacitor C 8 and high-frequency filter capacitor C9;
Said smothing filtering capacitor C 8 and high-frequency filter capacitor C9 parallel connection, the end after the parallel connection links to each other with first end of said inductance L 2, as said second output, and is connected to the said first reference ground end, and the other end is held with reference to ground as said second;
Second end of said inductance L 2 links to each other with the output of said the 2nd BUCK circuit.
6. system as claimed in claim 5 is characterized in that:
Said smothing filtering capacitor C 3 is an electrochemical capacitor with C8, and its positive pole connects first end of said inductance L 1, L2 respectively.
7. system as claimed in claim 5 is characterized in that, a said BUCK circuit comprises:
One boost chip, two diodes, a resistance, capacitor C 1 and capacitor C 5;
Said boost chip comprises synchronous pin, input pin, output pin, grounding pin, C pin and feedback pin;
Said synchronous pin receives said first clock signal through said capacitor C 5, and links to each other with said grounding pin through said resistance;
Said input pin links to each other with said power input unit, receives said input DC power;
Said C pin links to each other with said output pin through said capacitor C 1;
Said feedback pin is connected to second end of said inductance L 1;
Said output pin is connected to first end of said inductance L 1;
Said two diode parallel connections, anodal and said grounding pin links to each other, and negative pole links to each other with said output pin;
Said grounding pin is connected to said first with reference to the ground end.
8. system as claimed in claim 5 is characterized in that, said the 2nd BUCK circuit comprises:
One boost chip, two diodes, a resistance, capacitor C 6 and capacitor C 10;
Said boost chip comprises synchronous pin, input pin, output pin, grounding pin, C pin and feedback pin;
Said synchronous pin receives said second clock signal through said capacitor C 10, and links to each other with said grounding pin through said resistance;
Said input pin links to each other with said power input unit, receives said input DC power;
Said C pin links to each other with said output pin through said capacitor C 6;
Said feedback pin is connected to second end of said inductance L 2;
Said output pin is connected to first end of said inductance L 2;
Said two diode parallel connections, anodal and said grounding pin links to each other, and negative pole links to each other with said output pin;
Said grounding pin is connected to said second with reference to the ground end.
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| CN103178697B (en) * | 2013-03-01 | 2015-10-28 | 圣邦微电子（北京）股份有限公司 | Export the power-supply system of generating positive and negative voltage |
| CN104270009B (en) * | 2014-09-23 | 2017-12-12 | 广东美的制冷设备有限公司 | The power circuit and air conditioner of multi output |
| CN104270005B (en) * | 2014-09-24 | 2017-08-18 | 深圳市万拓存储技术有限公司 | A kind of power supply circuit of fan |
| CN106646305A (en) * | 2015-11-04 | 2017-05-10 | 江苏嘉钰新能源技术有限公司 | Simple current type Hall current sensor signal simulator |
| CN107094010A (en) * | 2015-12-21 | 2017-08-25 | 邓国文 | A kind of connection method of dual power supply multinode reference ground network and its device |
| CN106586346B (en) * | 2017-01-10 | 2018-11-02 | 任一帆 | A kind of garbage compression box rubbish is without shedding hopper |
| CN109861507A (en) * | 2018-12-21 | 2019-06-07 | 成都信息工程大学 | A kind of dual power supply conversion method, circuit and power protection method and circuit |
| CN110262336B (en) * | 2019-06-18 | 2021-02-02 | 中国科学院自动化研究所 | Current output circuit and transcranial electrical stimulation device comprising same |
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