CN200983361Y - Package device for FPGA - Google Patents
Package device for FPGA Download PDFInfo
- Publication number
- CN200983361Y CN200983361Y CN 200620137783 CN200620137783U CN200983361Y CN 200983361 Y CN200983361 Y CN 200983361Y CN 200620137783 CN200620137783 CN 200620137783 CN 200620137783 U CN200620137783 U CN 200620137783U CN 200983361 Y CN200983361 Y CN 200983361Y
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- CN
- China
- Prior art keywords
- chip
- solder sphere
- surface solder
- bridge joint
- base plate
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The utility model discloses a packing device used in the Field-Programmable Gate Array, which comprises a chip, a module cap, a lower base plate, lower surface soldering balls, a first directing line bridge connection, an upper base plate, upper surface soldering balls and a second directing line bridge connection. The module cap is covered outside the chip, the upper portion and the lower portion of the module cap are respectively provided with passages for the first directing line bridge connection and the second directing line bridge connection. The lower base plate and the upper base plate are respectively fixed on the lower surface and on the upper surface of the chip, which have exactly the same structure. The upper surface soldering balls and the lower surface soldering balls are respectively fixed on the upper base plate and on the lower base plate, the balls all have the same structure, fully corresponded quantity and position. Same lead foots of the chip are respectively connected with the lower surface soldering balls and the upper surface soldering balls which are corresponding in position by the first directing line bridge connection and the second directing line bridge connection. The utility model extremely provides great convenience for adjustments and tests of the Field-Programmable Gate Array.
Description
Technical field
The utility model relates to the Chip Packaging field, relates in particular to the packaging system that is used for FPGA.
Background technology
In the present high-speed digital system,, safeguard greater advantage is arranged in new function, and do not have too big difference on the performance, so the application of FPGA more and more widely than ASIC (application-specific IC) because FPGA has Reprogrammable.
Present FPGA adopts BGA or similar encapsulation usually.Fig. 1 illustrates the chip of the BGA encapsulation of prior art, and it is made of mould cap 101, chip 102, substrate 103, solder sphere 104 and lead bridge joint 105.Because the chip of BGA encapsulation that adopts prior art is on being welded to PCB (printed circuit board) plate the time, the solder sphere that welding is good is sightless for the user.So in the system design of using FPGA to carry out, the observation of internal signal when being difficult to realize debugging.General way is internal signal to be guided on the interim pin of FPGA, but need also be had test point to draw to these interim pins, so limited the wiring of pcb board level.
The utility model content
Technical problem to be solved in the utility model provides the packaging system of a kind of FPGA of being used for, it overcomes prior art and is difficult to realize in FPGA design flexibly the defective of pin signal and internal signal monitoring, especially overcomes the defective that observation FGPA pin in the prior art need add test point in the wiring of pcb board level.
For solving the problems of the technologies described above, the utility model provides the packaging system of a kind of FPGA of being used for, and it comprises chip, mould cap, infrabasal plate, lower surface solder sphere, the first lead bridge joint, upper substrate, upper surface solder sphere and the second lead bridge joint; Described mould cap covers the outside of described chip, and described mould cap 202 upper and lowers are left the passage that is used for described first lead bridge joint and the described second lead bridge joint respectively; Described infrabasal plate and described upper substrate are separately fixed at the bottom surface and the upper surface of chip, and both structures are identical; Described upper surface solder sphere is fixed on the described upper substrate, and described lower surface solder sphere is fixed on the lower surface of described infrabasal plate, and described lower surface solder sphere is identical with described upper surface solder sphere structure, and number and position are corresponding fully; By described passage, the pin that described chip is identical is connected to the described lower surface solder sphere and the described upper surface solder sphere of position correspondence respectively for the described first lead bridge joint and the second lead bridge joint.
Further, described upper substrate (201) is fixed on the upper surface of described chip (102) by binding agent.
Further, described mould cap (202) is fixed on the outside of described chip (102) by binding agent.
Further, described packaging system is connected to external circuit by described lower surface solder sphere (104).
Further, described packaging system is connected to external circuit by described upper surface solder sphere (203).
Therefore, as from the foregoing, because mould cap, upper substrate, the second lead bridge joint and upper surface solder sphere in chip upside layout, with identical with mould cap, infrabasal plate, the first lead bridge joint and lower surface solder sphere arrangement at the chip downside, and upper surface solder sphere and lower surface solder sphere the position on upper substrate, infrabasal plate and number are corresponding fully respectively;
Therefore for same inside chip pin, can guide to the solder sphere of packaged chip upper and lower surface simultaneously, upper and lower surface at packaged chip can obtain same signal, when practical application, the user can at random select by lower surface solder sphere 104 or upper surface solder sphere 203 packaging system of the present utility model to be welded on the pcb board, all can realize the signal observability of packaged chip after being welded to pcb board; When debugging and test, only need exposed solder sphere on packaged chip to measure and get final product, therefore do not change the wiring of pcb board level, need not add test point, greatly simplification and easy debugging and the test of FPGA in the wiring of pcb board level.
Description of drawings
Fig. 1 is the chip of the BGA encapsulation of prior art;
Fig. 2 is the packaging system of the FPGA of being used for of the present utility model;
Fig. 3 and Fig. 4 are the packaging system vertical views in actual applications of the FPGA of being used for of the present utility model.
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model is elaborated.
Fig. 2 is the packaging system of the FPGA of being used for of the present utility model, as shown in Figure 2, the packaging system of the FPGA of being used for of the present utility model is a phy chip 205, and it comprises upper substrate 201, mould cap 202, upper surface solder sphere 203, lead bridge joint 204, chip 102, infrabasal plate 103, solder sphere 104 and lead bridge joint 105.
As shown in Figure 2, mould cap 202 covers the outside of chip 102, preferably, is bonded in the outside of chip 102 by bonding mode.At the upside and the downside of chip 102, mould cap 202 leaves the passage that is used for lead bridge joint 204 and lead bridge joint 105 respectively.
Upper substrate 201 is bonded in the upper surface of chip 102 by adhesive, and infrabasal plate 103 is bonded in the bottom surface of chip 102.In addition, upper surface solder sphere 203 is fixed on the upper surface of upper substrate 201, and lower surface solder sphere 104 is fixed on the bottom surface of substrate 103.Wherein upper surface solder sphere 203 is identical with lower surface solder sphere 104 numbers, and the position on upper substrate 201, infrabasal plate 103 is corresponding fully respectively.
Draw lead bridge joint 204 and lead bridge joint 105 at the same pin of chip 102.Wherein lead bridge joint 204 passes through in upper substrate 201 by the passage in chip 102 upsides, the mould cap 202, and it is connected to upper surface solder sphere 203 with inside chip 102.Lead bridge joint 105 is realized being connected of inside chip 102 and lower surface solder sphere 104 by the passage in chip 102 downsides, the mould cap 202.
Should note, packaging system of the present utility model, mould cap 202, upper substrate 201, lead bridge joint 204 and upper surface solder sphere 203 at chip 102 upsides, with identical at mould cap 202, infrabasal plate 103, lead bridge joint 105 and lower surface solder sphere 104 arrangements of chip 102 downsides, structure, material etc., when practical application, the user can select arbitrarily packaging system of the present utility model to be welded on user's oneself the circuit by lower surface solder sphere 104 or upper surface solder sphere 203.
Fig. 3 is the packaging system vertical view in actual applications that the utility model is used for FPGA.
Because packaging system of the present utility model is identical in chip 102 upper and lower structures, so the user also can directly be welded on pcb board 301 surfaces with phy chip 205 by upper surface solder sphere 203.Like this, the upper surface solder sphere 203 of phy chip 205 is sightless, and lower surface solder sphere 104 remains visible, as shown in Figure 4, therefore when needing to measure the internal signal of phy chip 205, the user can realize the measurement of internal signal by lower surface solder sphere 104.Therefore the utility model can be realized the monitoring to pin signal and internal signal neatly.
In sum, the packaging system that the utility model is used for FPGA is compared with the chip of traditional BGA encapsulation, has following advantage:
Owing to arranged mould cap 202, upper substrate 201, lead bridge joint 204 and upper surface solder sphere 203 at chip 102 upsides, and arrangement and identical at mould cap 202, infrabasal plate 103, lead bridge joint 105 and lower surface solder sphere 104 arrangements of chip 102 downsides, and upper surface solder sphere 203 and lower surface solder sphere 104 position on upper substrate 201, infrabasal plate 103 and number are corresponding fully respectively, therefore
1, for same inside chip pin, can guide to the solder sphere of packaged chip upper and lower surface simultaneously, upper and lower surface at packaged chip can obtain same signal, realize the signal observability of packaged chip after the PCB welding, thereby when debugging and test, if need measure to pin, only the exposed solder sphere of need on packaged chip measured and got final product, therefore do not change the wiring of pcb board level, need not add test point, greatly simplify and easy debugging and the test of FPGA in pcb board level wiring.
2, when practical application, the user can at random select packaging system of the present utility model to be welded on user's oneself the circuit by lower surface solder sphere 104 or upper surface solder sphere 203, all can be implemented in welding signal observability afterwards.
It should be noted that the above embodiments only are exemplary, can not be interpreted as restriction of the present utility model.Under the situation that does not break away from spirit and scope of the present utility model, can make numerous variations and modification to the utility model.The utility model is limited by claims.
Claims (5)
1, a kind of packaging system that is used for FPGA, it comprises chip (102), mould cap (202), infrabasal plate (103), lower surface solder sphere (104), the first lead bridge joint (105), upper substrate (201), upper surface solder sphere (203) and the second lead bridge joint (204); Described mould cap (202) covers the outside of described chip (102), and described mould cap (202) upper and lower is left the passage that is used for described first lead bridge joint (105) and the described second lead bridge joint (204) respectively; Described infrabasal plate (103) and described upper substrate (201) are separately fixed at the bottom surface and the upper surface of described chip (102), and both structures are identical; Described upper surface solder sphere (203) is fixed on the described upper substrate (201), described lower surface solder sphere (104) is fixed on the lower surface of described infrabasal plate (103), described lower surface solder sphere (104) is identical with described upper surface solder sphere (203) structure, and number and position are corresponding fully; The described first lead bridge joint (105) and the second lead bridge joint (204) are connected to the identical pin of described chip (102) the described lower surface solder sphere (104) and the described upper surface solder sphere (203) of position correspondence respectively by described passage.
2, as packaging system as claimed in claim 1, wherein said upper substrate (201) is fixed on the upper surface of described chip (102) by binding agent.
3, packaging system as claimed in claim 1, wherein said mould cap (202) is fixed on the outside of described chip (102) by binding agent.
4, packaging system as claimed in claim 1, it is connected to external circuit by described lower surface solder sphere (104).
5, packaging system as claimed in claim 1, it is connected to external circuit by described upper surface solder sphere (203).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620137783 CN200983361Y (en) | 2006-09-29 | 2006-09-29 | Package device for FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620137783 CN200983361Y (en) | 2006-09-29 | 2006-09-29 | Package device for FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200983361Y true CN200983361Y (en) | 2007-11-28 |
Family
ID=38910512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620137783 Expired - Fee Related CN200983361Y (en) | 2006-09-29 | 2006-09-29 | Package device for FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN200983361Y (en) |
-
2006
- 2006-09-29 CN CN 200620137783 patent/CN200983361Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071128 Termination date: 20140929 |
|
| EXPY | Termination of patent right or utility model |