CN200983362Y - A BGA chip encapsulation device - Google Patents
A BGA chip encapsulation device Download PDFInfo
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- CN200983362Y CN200983362Y CNU2006201377843U CN200620137784U CN200983362Y CN 200983362 Y CN200983362 Y CN 200983362Y CN U2006201377843 U CNU2006201377843 U CN U2006201377843U CN 200620137784 U CN200620137784 U CN 200620137784U CN 200983362 Y CN200983362 Y CN 200983362Y
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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Abstract
The utility model discloses a Ball Grid Array chip package device, which comprises a chip (102), a module cap (202), a first base plate (103), lower surface soldering balls (104) and a first directing line bridge connection (105). The Ball Grid Array chip package device further comprises a second base plate (201), upper surface soldering balls (203) and a second directing line bridge connection (204). The module cap (202) is covered outside the chip (102), and the upper side is provided with a passage for the second directing line bridge connection (204). The first base plate (103) and the second base plate (201) are symmetrically and oppositely fixed on the lower surface of the chip (102) and on the upper surface of the chip (102), and upper surface soldering balls (203) and lower surface soldering balls (104) are respectively fixed on The first base plate (103) and the second base plate (201). The chip (102) is respectively connected with lower surface soldering balls (104) and upper surface soldering balls (203) through the first directing line bridge connection (105) and the second directing line bridge connection (204). The utility model extremely provides great convenience for adjustments and tests of the Field-Programmable Gate Array.
Description
Technical field
The utility model relates to microelectronics and integrated circuit is made the field.Relate in particular to the packaging system of BGA encapsulation (BGA Package) type chip.
Background technology
In the present high-speed digital system, because performance demands, the application of ASIC (application-specific IC) is more and more, in high-end and system at a high speed, ASIC has own advantageous advantage, and it can be operated under the high relatively dominant frequency, provides general-purpose chip inaccessiable performance.But ASIC also has the shortcoming of oneself, because it is non-programmable, causes exploitation and maintenance difficulties bigger, especially aspect safeguarding, even increase or change a little function, also need to design again and flow, cause its development cost to become geometric progression to increase.So now increasing FPGA is used to and replaces ASIC.FPGA has the characteristics of Reprogrammable, therefore safeguard than ASIC greater advantage is arranged in new function, and do not have too big difference on the performance, so the application of FPGA more and more widely.
Because pin is numerous, present FPGA adopts BGA or similar encapsulation usually.
Fig. 1 is the chip of prior art BGA encapsulation, and as shown in Figure 1, the phy chip 106 of prior art encapsulation is made of top mould cap 101, chip 102, substrate 103, solder sphere 104 and lead bridge joint 105.
Chip 102: chip 102 is cores of whole physical package, is the carrier of the function of phy chip, in order to realize the function on logic, sequential and the circuit.
Mould cap 101: cover the outside of chip 102, be used to prevent that chip is subjected to the effect of extraneous brute force and damages, the physical strength of mould cap is very high, can resist extraneous very strong active force, avoids the deformation of inside chip.
Substrate 103: the bottom that is bonded in chip, this laminar substrate 103 links to each other with chip 102 by binding agent, substrate 103 is used for realizing being connected of inside chip and bottom solder sphere, owing to want directly to contact with extraneous, substrate has very strong physical strength and impact resistant capability, owing to directly contact with solder sphere, substrate will have very strong heat resistance.
Solder sphere 104: be fixed on substrate 103 below, be the pin of physical package, it is unique inlet of user capture inside chip, solder sphere 104 links to each other with inside chip by the lead bridge joint, be used for the input/output signal of inside chip is directed to the outside, the user can be connected the circuit of oneself with the circuit of inside chip.
Lead bridge joint 105: lead bridge joint 105 passes through in substrate, realizes being connected of inside chip and outside weldings ball, and the general material that adopts of lead bridge joint is copper.
As from the foregoing, because chip is not direct and there is contact-making surface the outside, so the input/output signal of chip will link to each other with solder sphere by the lead bridge joint, the user will visit the pin of inside chip, must operate by solder sphere.For the user, the pin of inside chip is sightless, and solder sphere is visible.
Yet in the chip of using the BGA encapsulation, the solder sphere that welding is good is sightless for the user.Therefore, the means of FPGA debugging at present all are basically: design digital circuit in the chip in conjunction with the wave simulation of software earlier, and then carry out the debugging of plate level, debug successfully after, if production also will be carried out the test of system.Need carry out the analysis of problem when encountering problems in debugging and test, the signal that FPGA inside is monitored in very big may needing this moment changes.Yet the observation of the internal signal when debugging and test is to use the difficulty of the maximum that runs in the system design of FPGA.This internal signal can be grasped by JTAG (combined testing action group) interface by specific software, but need again device to be carried out operations such as comprehensive and wiring, expend a large amount of time, and need extra FPGA internal resource to realize, this is also inconvenient under the situation of larger resource anxiety, is unfavorable for very much the modularized design of FPGA.Another approach is that internal signal is guided on the interim pin of FPGA, because the FPGA of multitube pin adopts BGA type (EBGA (reinforcement BGA Package), FBGA (little spacing BGA Package) etc.) encapsulation basically now, therefore the solder sphere of packaged chip can not be touched, this just need also have test point to draw to these interim pins, and this is again a restriction in the wiring of PCB (printed circuit board) plate level.
The utility model content
Technical problem to be solved in the utility model provides a kind of bga chip packaging system, it overcomes prior art and is difficult to realize in FPGA design flexibly the defective of pin signal and internal signal monitoring, and especially overcoming observation FGPA pin in the prior art need add test point or FPGA be carried out again the defective of place and route in the wiring of pcb board level.
For solving the problems of the technologies described above, the utility model provides a kind of bga chip packaging system, it comprises chip, mould cap, first substrate, lower surface solder sphere and the first lead bridge joint, described mould cap covers the outside of described chip, described first substrate bonding is at described chip bottom surface, the fixing described lower surface solder sphere in its bottom, the described first lead bridge joint connects described chip and described lower surface solder sphere, it is characterized in that described bga chip packaging system also comprises second substrate, upper surface solder sphere and the second lead bridge joint; Described second substrate is fixed on the upper surface of described chip, symmetrical up and down with described first substrate, described upper surface solder sphere is fixed on described second substrate, upside being provided with of described mould cap is used for the passage of the described second lead bridge joint, the described second lead bridge joint is by described passage and stride across described mould cap and described second substrate, connects described upper surface solder sphere and described chip.
Further, in preferred embodiment of the present utility model, described second substrate is fixed on the upper surface of described chip by bonding mode.
Further, in preferred embodiment of the present utility model, described mould cap is fixed on the outside of described chip by bonding mode.
Further, in preferred embodiment of the present utility model, described mould cap and described second substrate have bigger contact-making surface.
Further, described upper surface solder sphere only is fixed on described second substrate.
Further, described bonding mode adopts the peroxidating agent to realize.
Further, in preferred embodiment of the present utility model, described upper surface solder sphere and described lower surface solder sphere be symmetry fully.
Further, the part symmetry of described upper surface solder sphere and described lower surface solder sphere.
Bga chip packaging system of the present utility model is when being welded on the pcb board surface by the lower surface solder sphere, although the solder sphere of lower surface is sightless for the user, it is visible that yet the solder sphere of upper surface remains concerning the user, so the user can measure the input/output signal of inside chip by the solder sphere of upper surface.
The utility model also provides a kind of FPGA packaged type of debugging and testing of being easy to, and it may further comprise the steps:
A: the physical structure of constructing chip in a conventional manner, at chip arranged outside mould cap, and first substrate being set at described chip bottom surface, fixing lower surface solder sphere below described first substrate is connected described lower surface solder sphere with the first lead bridge joint with described chip;
B: the upside at described mould cap leaves the passage that is used for the second lead bridge joint;
B: at same second substrate that covers of described chip upper surface;
C: same fixedly upper surface solder sphere on second substrate on described,
D: described upper surface solder sphere is connected with described chip with the second lead bridge joint.
Further, described step C can comprise:
C1: if wiring condition allows, described upper surface solder sphere at upside can be identical with the signal of the lower surface solder sphere of described opposite side (downside);
C2: because wiring, described upper surface solder sphere at upside can an extension signal, rather than the signal with the lower surface solder sphere of described opposite side (downside) is identical all.
Of the present utility model focusing on: 1, in the physical package of chip, increased by a laminar substrate; 2, add solder sphere simultaneously, the observability of enhancing signal in two sides up and down of chip.
Therefore, as from the foregoing, because the upper surface at the chip of traditional BGA encapsulation has increased a laminar substrate and solder sphere (being the upper surface solder sphere), when chip being carried out the BGA encapsulation, pin for same inside chip, guide to the two-sided physical package of carrying out of chip simultaneously, like this, the solder sphere that corresponding same signal is all arranged at the upper and lower surface of chip, realize the signal observability of chip after the PCB welding, when debugging and testing, if desired the pin of inside chip is measured, only need the exposed solder sphere on chip measure and get final product.
Use the chip of this packaged type, the developer debug test with the tester in, if pinpoint the problems, when needs are observed the pin signal of chip, it is just passable only need directly to draw test point on chip, and does not need the PCB veneer is made amendment, even also do not draw corresponding signal this moment on the chip to pin, what do also only is that chip is carried out the locking of pin again, and does not need to carry out comprehensive again and layout, wiring to chip.
Therefore adopt chip packaging device of the present utility model, when debugging and test, can not change the wiring of pcb board level, need not add test point in the wiring of pcb board level, and do not need FPGA is carried out place and route again, greatly simplify and easy debugging and the test of FPGA.
In addition, because upper surface solder sphere and lower surface solder sphere can be symmetrical fully, can only comprise the part of lower surface solder sphere again, so the utility model can be adapted to different wiring occasions.
The utility model has been realized a kind of FPGA packaging system of debugging and testing of being easy to, and by changing traditional packaged type, makes signal pin to the user fully as seen.Reduced user's development difficulty.The utility model can change, and is widely used in the Chip Packaging of multiple ASIC of BGA type, similar BGA type package, and is not only fpga chip.
Description of drawings
Fig. 1 is the chip of the BGA encapsulation of prior art;
Fig. 2 is the chip of BGA encapsulation of the present utility model;
Fig. 3 is the chip viewgraph of cross-section in actual applications of BGA encapsulation of the present utility model;
Fig. 4 is the chip vertical view in actual applications of BGA encapsulation of the present utility model;
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model is elaborated.
Fig. 2 is the chip of BGA encapsulation of the present utility model, and as shown in Figure 2, the chip of BGA encapsulation of the present utility model is a phy chip 205, and it comprises as the lower part:
Chip 102: the core of the physical device of encapsulation, just the part of the crystal in the physical device is in order to realize the function of device, identical with structure of the prior art;
Substrate 201: be fixed on the upper surface of chip 102, symmetrical about in the of 103 with the substrate below chip 102, preferably, it links to each other with chip 102 by bonding mode, and this bonding mode can adopt traditional peroxidating agent to realize.This substrate 201 is carriers of BGA encapsulation, is used to connect inside chip 102 and upper surface solder sphere 203 (following), avoids chip directly to be exposed to the external world.
Substrate 103: be bonded in the bottom surface of chip 102, link to each other with chip 102 by binding agent, itself and substrate be symmetry about in the of 201, is used for realizing being connected of inside chip 102 and lower surface solder sphere, and be identical with structure of the prior art.
Compare with the chip that the BGA of conventional art encapsulates, the chip of BGA encapsulation of the present utility model forms laterally zygomorphic substrate 201 and 103, the carrier of lead bridge joint can be provided for inside chip simultaneously at the lower surface of the upper surface of this substrate 201 and substrate 103 like this, make fixedly solder sphere of described up and down two surfaces, this variation is an emphasis of the present utility model.
Mould cap 202: cover the outside of chip 102, preferably, link to each other with chip 102 by bonding mode, wherein this bonding mode can adopt traditional peroxidating agent to realize, and preferably, this mould cap 202 has bigger contact-making surface with this substrate 201 and 103; Be used to strengthen the chip protection of power to external world, strengthen the anti-strike ability of chip.Compare with conventional art, the utility model has been reserved a substrate 201 and inside chip 102 at mould cap 202 places on upper strata interface channel is an improvement of the present utility model.
Upper surface solder sphere 203: the upper surface that is fixed on substrate 201, preferably, be bonded in the upper surface of substrate 201 by the peroxidating agent, the same with the fixed form of lower surface solder sphere 104, it links to each other with substrate 203, in order to the contact of externally welding, concerning the user, have only by solder sphere and could be connected with chip, its effect is identical with lower surface solder sphere 104.
Lower surface solder sphere 104: be fixed on substrate 103 below, identical with structure of the prior art.
Should note, the solder sphere 203 of upper surface can be in full accord corresponding up and down with solder sphere 104 positions and the number of lower surface, also can be arranged in the upper surface of substrate 201 as required, a part of corresponding with lower surface solder sphere 104 only promptly realizes the chip signal of a part is guided to the upper surface of substrate 201.Can distribute and utilize wiring and internal resource so more neatly, and applicable to some specific pin, for example power supply and ground do not need visible situation concerning the user.
Different with traditional BGA encapsulation is, the utility model all has solder sphere on two planes up and down of packaged chip, like this, when the solder sphere of user by lower surface links to each other packaged chip with the PCB circuit board, the solder sphere of upper surface is visible, when the user need measure and monitor the pin signal of inside chip, under the situation that does not have test point on the PCB circuit board, also can directly measure.Be one of improvement of the present utility model.
Lead bridge joint 204: lead bridge joint 204 passes through in substrate 201, strides across mould cap 202 and substrate 201, is used to connect upper surface solder sphere 203 and inside chip 102, acts on identical with lead bridge joint 105.
Lead bridge joint 105: lead bridge joint 105 passes through in substrate 103, realizes being connected of inside chip 102 and lower surface solder sphere 104, and is identical with structure of the prior art.
Phy chip 205: the packaged improved phy chip 205 that has constituted practical application by top substrate 201, mould cap 202, upper surface solder sphere 203, lead bridge joint 204, chip 102, substrate 103, solder sphere 104 and lead bridge joint 105.
Fig. 3 is the chip viewgraph of cross-section in actual applications of BGA encapsulation of the present utility model.Phy chip 205 is for adopting the chip of improved packaging system of the present utility model.Phy chip 205 directly is welded on pcb board 301 surfaces by lower surface solder sphere 104, and is the same with the chip of traditional BGA encapsulation, and the input/output signal that this lower surface solder sphere 104 is applied to chip is connected with the circuit in the external world.Wherein pcb board 301 is used the circuit board that designs for user's oneself Circuits System.Test lead 302 is connected to the upper surface solder sphere 203 of phy chip 205, and the user can test by the signal of 302 pairs of chips of this test lead.
In this practical application, the upper surface solder sphere 203 of phy chip 205 and lower surface solder sphere 104 be symmetry (being that position and number can be in full accord corresponding up and down) fully, also can be only a part of corresponding with lower surface solder sphere 104.Figure 3 shows that upper surface solder sphere 203 situation symmetrical fully of phy chip 205 with lower surface solder sphere 104.
As shown in Figure 3, phy chip 205 is under the situation that is welded on pcb board 301 surfaces, the solder sphere 104 of lower surface is blocked by chip itself, for the user is sightless, and 203 couples of users of the solder sphere of upper surface are visible, therefore pass through the solder sphere 203 of upper surface, the user can observe the input/output signal of inside chip, with lower surface solder sphere 104 resulting input/output signals is the same, further, for example can test by the signal of 302 pairs of chips of test lead.
Fig. 4 is the chip vertical view in actual applications of BGA encapsulation of the present utility model.It is welded on the vertical view on pcb board 301 surfaces by lower surface solder sphere 104 for phy chip 205.As shown in Figure 4, after phy chip 205 is welded on pcb board 301 surfaces, the upper surface solder sphere 203 of phy chip 205 remains visible, and lower surface solder sphere 104 is sightless, therefore when needing the pin signal of measured chip, the user can measure internal signal by upper surface solder sphere 203, easily user's measurement.
In sum, bga chip packaging system of the present utility model is compared with the chip of traditional BGA encapsulation, has following advantage:
1, owing on the chip of traditional B GA encapsulation, increased a laminar substrate and solder sphere (being the upper surface solder sphere), and the substrate of described increase and the substrate symmetry up and down that is fixed on below the chip, and the upper surface solder sphere is corresponding with the lower surface solder sphere, therefore, for same inside chip pin, can guide to the solder sphere of packaged chip upper and lower surface simultaneously, upper and lower surface at packaged chip forms the pin with same signal, realize the signal observability of packaged chip after the PCB welding, thereby when debugging and test, if need measure to pin, only the exposed solder sphere of need on chip measured and got final product, therefore do not change the wiring of pcb board level, need not add test point in the wiring of pcb board level, and do not need FPGA is carried out place and route again, greatly simplify and easy debugging and the test of FPGA;
2, because the upper surface solder sphere can be in full accord corresponding up and down with lower surface solder sphere position and number, again can be only a part of corresponding with the lower surface solder sphere, therefore can distribute and utilize wiring and internal resource more neatly, and be adapted to different wiring occasions;
3, packaging system of the present utility model can be revised, and may be used in the packaging system of multiple different Chip Packaging;
As from the foregoing, bga chip packaging system of the present utility model is easy to debugging and test, and it has realized the debugging of FPGA and the great simplification of test with a kind of simple change on encapsulating structure.This adopts the asic chip of BGA class (EBGA, FBGA etc.) encapsulation for FPGA or other, is that a kind of realization of simple and flexible is easy to the scheme of debugging and testing.
Structure of the present utility model after changing, also can provide close effect, described changing to below doing:
Can be in full accord corresponding up and down in the solder sphere of upper surface with the solder sphere of lower surface, also can be only a part of corresponding with the lower surface solder sphere, promptly only get a part of chip signal and guide to upper surface.
Encapsulating structure of the present utility model can be applied in the chip packaging device of other packaged type through revising.For example, the utility model not only can be applied in the chip of BGA encapsulation, for example can also be applied in similar encapsulation: in the device of EBGA, FBGA etc., even can be applied in dissimilar other packaged type device, for example: in the device of various packaged types such as LCC, LDCC, LQFP, PQFP.
Should note; the utility model is not limited to above-mentioned application; the utility model need can be applicable to the multiple occasion of debugging and test chip packaging system; the observability that chip packaging device internal signal when debugging and test is provided that is intended that of the present utility model is therefore if there is other form to realize that intention of the present utility model all drops in the protection range of the present utility model.The above embodiments only are exemplary in addition, can not be interpreted as restriction of the present utility model.Under the situation that does not break away from spirit and scope of the present utility model, can make numerous variations and modification to the utility model.The utility model is limited by claims.
Claims (8)
1, a kind of bga chip packaging system, it comprises chip (102), mould cap (202), first substrate (103), the lower surface solder sphere (104) and the first lead bridge joint (105), described mould cap (202) covers the outside of described chip (102), described first substrate (103) is fixed on described chip (102) bottom surface, its bottom is fixed with described lower surface solder sphere (104), the described first lead bridge joint (105) connects described chip (102) and described lower surface solder sphere (104), it is characterized in that described bga chip packaging system also comprises second substrate (201), the upper surface solder sphere (203) and the second lead bridge joint (204); Described second substrate (201) is fixed on the upper surface of described chip (102), symmetrical up and down with described first substrate (103), described upper surface solder sphere (203) is fixed on described second substrate (201), upside being provided with of described mould cap (202) is used for the passage of the described second lead bridge joint (204), the described second lead bridge joint (204) is by described passage and stride across described mould cap (202) and described second substrate (201), connects described upper surface solder sphere (203) and described chip (102).
2, bga chip packaging system as claimed in claim 1 is characterized in that, described second substrate (201) is fixed on the upper surface of described chip (102) by bonding mode.
3, bga chip packaging system as claimed in claim 1 is characterized in that, described mould cap (202) is fixed on the outside of described chip (102) by bonding mode.
4, bga chip packaging system as claimed in claim 1 is characterized in that, described mould cap (202) has bigger contact-making surface with described second substrate (201).
5, bga chip packaging system as claimed in claim 1 is characterized in that, described upper surface solder sphere (203) only is fixed on described second substrate (201).
As each described bga chip packaging system in the claim 2,3, it is characterized in that 6, described bonding mode adopts the peroxidating agent to realize.
7, bga chip packaging system as claimed in claim 1 is characterized in that, described upper surface solder sphere (203) is symmetrical fully with described lower surface solder sphere (104).
8, bga chip packaging system as claimed in claim 1 is characterized in that, described upper surface solder sphere (203) is symmetrical with the part of described lower surface solder sphere (104).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201377843U CN200983362Y (en) | 2006-09-29 | 2006-09-29 | A BGA chip encapsulation device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006201377843U CN200983362Y (en) | 2006-09-29 | 2006-09-29 | A BGA chip encapsulation device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200983362Y true CN200983362Y (en) | 2007-11-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2006201377843U Expired - Lifetime CN200983362Y (en) | 2006-09-29 | 2006-09-29 | A BGA chip encapsulation device |
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| CN (1) | CN200983362Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI765944B (en) * | 2016-12-14 | 2022-06-01 | 成真股份有限公司 | Logic drive based on standard commodity fpga ic chips |
-
2006
- 2006-09-29 CN CNU2006201377843U patent/CN200983362Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI765944B (en) * | 2016-12-14 | 2022-06-01 | 成真股份有限公司 | Logic drive based on standard commodity fpga ic chips |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20151106 Address after: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee after: ZTE Corporation Patentee after: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |
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| CX01 | Expiry of patent term |
Granted publication date: 20071128 |
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| EXPY | Termination of patent right or utility model |