CN200979682Y - Multi-chip system functional unit interface circuit - Google Patents
Multi-chip system functional unit interface circuit Download PDFInfo
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- CN200979682Y CN200979682Y CN 200620122167 CN200620122167U CN200979682Y CN 200979682 Y CN200979682 Y CN 200979682Y CN 200620122167 CN200620122167 CN 200620122167 CN 200620122167 U CN200620122167 U CN 200620122167U CN 200979682 Y CN200979682 Y CN 200979682Y
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Abstract
The utility model discloses an internal functional unit of multichip system is to input/output bus's interface circuit. One of the main features of the present invention is to remove the positive voltage protection diode between the independent power source of the functional unit and the input/output bus line or disable it in the interface circuit of the present functional unit, so that it will not form a low impedance load due to the closing of the independent power source of the functional unit, and further the signal on the input/output bus is distorted. The other main feature of the present invention is that, in addition to the aforementioned method of avoiding distortion of the signal on the bus, the zener diode in the voltage-stabilizing form is further used to replace the negative voltage protection diode between the ground and the input/output bus line in the interface circuit of the existing functional unit, so that the high voltage static electricity can penetrate through the zener diode and leak to the ground, thereby achieving the purpose of anti-static and protecting the functional unit.
Description
Technical field
The utility model relates to multichip system, relates in particular to the interface circuit that functional unit and input/output bus circle connect in the multichip system.
Background technology
Since two thousand, (System on Chip SoC) is the main flow of Mirae Corp. to the semiconductor design industry with System on Chip/SoC always.Yet because the complexity of SoC is high long with the design cycle, market is considering to be inclined to the so-called system in package of employing (System inPackage on purchase cost and the volume production time-histories on the contrary gradually, SiP) or multicore sheet encapsulation (Multi-chip Package, MCP).SiP can be defined as in a packaging body, includes the chip more than two, adds the encapsulation of passive components such as electric capacity, resistance, connector, antenna.Definition according to this, SiP can have various ways, with regard to the arrangement mode of chip, SiP may be that planar alignment or solid are piled up, and with reduction packaging body area, and its interior bonds technology can be simple routing joint, also can use chip bonding, but also the two is used also.
SiP is mainly used on mobile phone memory, the storage card at present, this is because mobile phone needs program code read, fundamental frequency to use buffering, three kinds of functions of multimedia storage simultaneously, make mobile phone need simultaneously, such as, NOR Flash, NAND Flash, three kinds of chips of Pseudo SRAM.Add memory chip and have similar size and routing, standardization electrical specification and numerous chip suppliers' cause, so mobile phone memory, storage card take the lead in adopting the encapsulation notion of SiP than other IC product.Therefore be that example illustrates background of the present utility model mainly below the utility model, and come this class of general name with SiP encapsulation known today or the following encapsulating products that similarly comprises a plurality of chips that may occur with " multichip system " speech with multicore sheet storage card.
Multichip system itself also has the difficulty that is difficult for breakthrough.One of them main problem is, each chip is from different suppliers, and the equal factor of supply voltage is arranged and needs complicated power management circuit, and thereby problems such as the power dissipation of deriving, circuit noise.It shown in Fig. 1 a the schematic internal view of an existing multicore sheet storage card, multicore sheet storage card 1 shown in Fig. 1 a is a kind of multi-medium file memory device that can insert electronic apparatus such as mobile phone, digital camera, MP3 player, PDA, also can be inserted in the storage card of the generic serial port (USB port) of general computing machine, mobile computer.As shown in Figure 1a, therefore multicore sheet storage card 1 has input/output bus 10 that is connected with the IO interface 12 of electronic apparatus and the function bus 20 that is connected with the USB port 22 of computing machine.The read-write of the storer 32 of multicore sheet storage card 1 is controlled by Memory Controller 30, is then controlled via function bus 20 by controller 40 for the input and output of the USB port 22 of computing machine.Electronic apparatus and computing machine then all carry out via input/output bus 10 read-write of storer 32.40 of controllers are connected with input/output bus 10 via impact damper 50.Can further specify below the effect of relevant impact damper 50.
Framework shown in Fig. 1 a also can be a kind of card reader 1 of many interfaces.For example the storer among Fig. 1 a 32 is a MicroSD card (shown in the dotted line square among the figure) that is attached to 1 li of card reader in the plug-in card mode with Memory Controller 30 in fact.12 of IO interface are the interfaces of a SD.By such design, the MicroSD card that card reader is 1 li can insert in the electronic apparatus such as the mobile phone that do not have the MicroSD interface, only have the SD interface, digital camera, MP3 player, PDA.See through USB port 22 then, card reader 1 also can be inserted on the generic serial port (USB port) of general computing machine, mobile computer.
From the framework shown in Fig. 1 a, expression such as Fig. 1 b that the internal circuit of similar multichip system can be abstract.As shown in the figure, include a coenosarc main control unit 300 and at least one functional unit (this figure shows two functional units 400,410 altogether) in the multichip system at least.Multichip system can comprise the greater functionality unit in fact, but only illustrates two for simplicity at this.With multicore sheet storage card 1 is example, and coenosarc main control unit 300 is its Memory Controller 30.The effect of coenosarc main control unit 300 is responsible for linking up the peripheral functional unit 400,410 of control with complete every function as the central processing unit of multichip system.Functional unit 400,410 has separately function bus 200,210 and functional interface 202,212 (similar USB port 22) promptly as the controller 40 of multicore sheet storage card 1.Coenosarc main control unit 300 all is connected on the input/output bus 100 with functional unit 400,410 (via impact damper 500,510), except the exchange of data via the input/output bus 100, various control signals also are via input/output bus 100.Input/output bus 100 also is connected with the IO interface 102 of multichip system.Note that the multichip system of Fig. 1 b is if storage card as shown in Figure 1a also can include memory chip (the dotted line square among the figure) naturally interior.Here alleged in addition " unit " also comprises its relevant passive component, but do not illustrate for simplicity except comprising main chip.
Note that also that in addition coenosarc main control unit 300 and functional unit 400,410 all have working power V1, V2 and V3 separately.For example, when multichip system is when being connected with a certain electronic installation, usually the electric power that provides through IO interface or functional interface from this electronic installation is provided for V1, V2, V3, after the suitable change-over circuit (not icon) of process becomes suitable voltage, offer each unit simultaneously.Because not all functional unit all needs running,, also form unnecessary power consumption so this arrangement causes unnecessary burden (that is script does not need big like this electric power) to the electric power that provides.Therefore impact damper (buffer switch) 500,510 need be arranged between functional unit 400,410 and the input/output bus 100, when only needing functional unit 410 work, except the power supply of hold function unit 400 (V2 sidenote note has X), controller buffer 500 makes functional unit 400 isolate (purpose of relevant isolation is explained orally after a while) with input/output bus 100 simultaneously.But the power supply V4 that uninterruptedly provides also is provided itself impact damper 500,510, so it is limited to use impact damper that the burden of electric power is alleviated in fact, and being provided with instead of impact damper can increase cost.All need such buffering on each bar Bus Wire in fact, but in diagram, for simplicity, only represent with a square.So, area and cost when impact damper can significantly increase the multichip system configuration, especially when input/output bus has seniority and needs high-speed transfer, the increase of area and cost more remarkable (for example and 32,64,128 so more the bus of seniority will need same number of impact damper).In order to address this problem, it is that a plurality of impact dampers are replaced with a derailing switch that prior art is arranged, but derailing switch still needs the power supply of a uninterrupted power supply, and the same time of derailing switch can only allow a functional unit be connected to input/output bus, can make multichip system be subjected to unnecessary restriction like this.
The purpose that impact damper 500,510 is set is the signal skew distortion for fear of input/output bus 100.It shown in Fig. 2 a the signal waveforms of existing multichip system input/output bus.Under normal conditions (that is all unit all power or have under the situation that impact damper is set), its signal bits will definitely be higher than more than the accurate TG of lowest order that can correctly recognize this signal.But when impact damper not being set and close the power supply that does not need the functional unit that operates separately, its signal waveform can be deformed into shown in Fig. 2 b general, and the position that is lower than TG of becoming is accurate and cause the undesired running of system.
The reason that causes signal skew is shown in Fig. 1 c.For simplicity, Fig. 1 c only draws coenosarc main control unit 300 and because does not need to operate and the functional unit 400 of powered-down V2.The core logic of coenosarc main control unit 300 and functional unit 400 (core logic) part also is reduced to two squares 304,404 among the figure.Wherein Bus Wire 106 with input/output bus 100 is an example, and the core logic 304,404 of coenosarc main control unit 300 and functional unit 400 has all been arranged a positive pressure protection diode 306 and 406 and negative pressure protection diodes 308 and 408 at the interface that connects with Bus Wire 106 boundaries.Note that these diodes are just to be produced in the chip in the chip manufacturing proces of coenosarc main control unit 300 and functional unit 400.Diode 306 and 308 is reverse being serially connected with between power supply V1 and the ground; Similarly, diode 406 and 408 is reverse being serially connected with between power supply V2 and the ground.The purpose of diode is set originally protection coenosarc main control unit and the unlikely destruction that is subjected to high-pressure electrostatic of functional unit at interface with input/output bus.When high-pressure electrostatic took place, for functional unit 400, it can follow dotted line among the figure, be leaked to ground via diode 406, electric capacity 402.For coenosarc main control unit 300, then be to be leaked to ground via diode 306, electric capacity 302.But under the situation that V2 does not power, the current path of dotted line representative forms a low-impedance load to input/output bus 100 among the figure, thereby the signal level shown in Fig. 2 a dragged down shown in Fig. 2 b, cause the distortion distortion of signal waveform, influence the correctness of data transmission.
Summary of the invention
Therefore, fundamental purpose of the present utility model is to propose the interface circuit of a kind of multichip system built-in function unit to input/output bus, make and adopt multichip system of the present utility model, can reach following effect simultaneously: each functional unit of (1) multichip system can be independently-powered, to reduce unnecessary electric power burden and power attenuation; (2) do not need to adopt impact damper to come isolation features unit and input/output bus, to save cost of products; (3) signal on the input/output bus can be because of the power supply of closing a certain functional unit torsional deformation; And the core logic of (4) the defencive function unit destruction that is not subjected to high-pressure electrostatic.
The utility model provides a kind of multichip system functional unit interface circuit, this multichip system inside comprises at least one coenosarc main control unit, and at least one functional unit, an and input/output bus that connects this coenosarc main control unit and this functional unit, this multichip system drives this coenosarc main control unit and this functional unit respectively with a plurality of independently power supplys, this power supply of this functional unit can optionally independently open and close, this functional unit interface circuit is between this input/output bus and this functional unit, for each Bus Wire of this input/output bus, this interface circuit comprises at least:
One Zener diode, its anode are connected in this multichip system to ground, and its negative electrode is connected in the Bus Wire of this input/output bus, and this Zener diode has a suitable disruptive voltage;
Wherein, between the power supply of this Bus Wire and this functional unit for opening circuit.
The utility model also provides a kind of multichip system functional unit interface circuit, this multichip system inside comprises at least one coenosarc main control unit, and at least one functional unit, an and input/output bus that connects this coenosarc main control unit and this functional unit, this multichip system drives this coenosarc main control unit and this functional unit respectively with a plurality of independently power supplys, the power supply of this functional unit can optionally independently open and close, this functional unit interface circuit is between this input/output bus and this functional unit, for each Bus Wire of this input/output bus, this interface circuit comprises at least:
One diode, its anode are connected in this multichip system to ground, and its negative electrode is connected in the Bus Wire of this input/output bus;
Wherein, between this power supply of this Bus Wire and this functional unit for opening circuit.
Compared with prior art, the utlity model has following remarkable advantage:
(1) each functional unit of multichip system can be independently-powered, to reduce unnecessary electric power burden and power attenuation;
(2) do not need to adopt impact damper to come isolation features unit and input/output bus, to save cost of products;
(3) signal on the input/output bus can be because of the power supply of closing a certain functional unit torsional deformation;
(4) core logic of defencive function unit is not subjected to the destruction of high-pressure electrostatic.
Below cooperate the detailed description of appended diagram, embodiment, will on address other purpose of the present utility model and advantage and be specified in after.Yet, should be understood that appended diagram is just established the improper definition that is considered as the utility model category for explaining orally spirit of the present utility model.The definition of relevant the utility model category please refer to claims.
Description of drawings
It shown in Fig. 1 a the schematic internal view of existing multicore sheet storage card;
It shown in Fig. 1 b the internal circuit synoptic diagram of existing multichip system;
Being existing multichip system shown in Fig. 1 c causes the synoptic diagram of low impedance path under the situation there being functional unit not power separately;
It shown in Fig. 2 a the signal waveforms of existing multichip system input/output bus under the normal conditions;
Being existing multichip system shown in Fig. 2 b is having do not power the separately signal waveforms of its input/output bus under the situation of functional unit;
Be to adopt multichip system of the present utility model that do not power the separately signal waveforms of its input/output bus under the situation of functional unit is being arranged shown in Fig. 2 c;
It shown in Fig. 3 a internal circuit synoptic diagram according to multichip system of the present utility model;
Shown in Fig. 3 b the interface circuit synoptic diagram of the multichip system of Fig. 3 a according to the utility model first embodiment;
Shown in Fig. 3 c the interface circuit synoptic diagram of the multichip system of Fig. 3 a according to the utility model second embodiment;
It shown in Fig. 3 d schematic internal view according to multicore sheet storage card of the present utility model;
The circuit arrangement map that is respectively the multichip system of existing employing impact damper and adopts multichip system of the present utility model shown in Fig. 4 a, the 4b.
Among the figure
1,2 multicore sheet storage card, 10 input/output bus
12 IO interface, 20 function buses
22 USB port, 30 Memory Controllers
32 storeies 40, the 40* controller
50 impact dampers, 100 input/output bus
102 IO interface, 106 Bus Wires
200 function buses
202 functional interfaces, 210 function buses
212 functional interfaces, 300 coenosarc main control units
302 electric capacity, 304 core logic
306,308 diodes
400 functional units, 402 electric capacity
404 core logic, 406,408 diodes
410 functional units, 500,510 impact dampers
600 functional units, 602 electric capacity
604 core logic, 606 diodes
608 Zener diodes, 610 diodes
The lowest order standard of TG signal
V1, V2 power supply V3, V4 power supply
Embodiment
Fundamental purpose of the present utility model is to propose the interface circuit of a kind of multichip system built-in function unit to input/output bus.The utility model is applicable to any with SiP known today, MCP packaged type or the following made multichip system of the packaged type that similarly comprises a plurality of chips that may occur.The present most typical example of multichip system is exactly the multicore sheet storage card (can support any suitable specification such as MMC, SD, Micro-SD etc.) that institutes such as mobile phone, digital camera, MP3 player, PDA, general computing machine, mobile computer can use, but the utility model is real not as limit.For example, the utility model also can be a kind of coenosarc main control unit or the functional unit card reader with plug-in card mode and multichip system combination.Whether this instructions for simplicity, not lay special stress on coenosarc main control unit or functional unit is that mode with plug-in card is attached in the multichip system.
It shown in Fig. 3 a internal circuit synoptic diagram according to multichip system of the present utility model.As shown in the figure, multichip system includes a coenosarc main control unit 300 and at least one functional unit (this figure shows two functional units 600,610 altogether) at least.Coenosarc main control unit 300 and each functional unit 600,610 are respectively naturally by independently power supply V1, V2, V3 are powered, coenosarc main control unit 300, functional unit 600 and functional unit 610 are connected with IO interface 102 by input/output bus 100, wherein the power supply V1 of coenosarc main control unit 300 is direct power supplies, and power supply V2, the V3 of functional unit 600,610 can distinguish and supplied with or cut off according to whether using functional unit 600,610.Other relevant details can be with reference to the explanation of relevant Fig. 1 b.
Shown in Fig. 3 b the interface circuit of coenosarc main control unit 300 and functional unit 600 of the multichip system of Fig. 3 a, according to the synoptic diagram of the utility model first embodiment.Wherein, coenosarc main control unit 300 has the present interfaces circuit framework.Functional unit 600 is also the same with the prior function unit, has core logic 604 and electric capacity 602 or the like.Wherein the core logic 604 of functional unit 600 is connected with the core logic 304 of coenosarc main control unit 300 by Bus Wire 106, as previously mentioned, functional unit 600 has just had the malleation of comprising and negative pressure protection diode 610,606 when making in chip manufacturer, and described malleation and the both ends of power that is connected in parallel on core logic 604 after negative pressure protects diode 610,606 to connect; And comprise in the coenosarc main control unit 300 malleation and negative pressure protection diode 306,308 be connected in parallel on the both ends of power of core logic 304 after connecting; and the negative electrode of malleation diode 306 is connected with negative pressure diode 308 anodes; the anode of malleation diode 306 is connected with the positive source of core logic 304, and the cathode of negative pressure diode 308 is connected with the power cathode of core logic 304.But by requiring chip manufacturer positive pressure protection diode 610 and Bus Wire 106 and power supply V2 to be connected disconnection (X as shown in FIG.) at the chip production back-end process.Therefore when not needing functional unit 600 runnings, power supply V2 to be closed with the saving power consumption, the current path of dotted line representative has not just existed among Fig. 1 c, also so not can form a low-impedance load, and cause the distortion distortion of input/output bus signal waveform input/output bus line 106.When occurring in input/output bus as for high-pressure electrostatic, diode 306, the electric capacity 302 that then can see through coenosarc main control unit 300 are leaked to ground and reach defencive function (path as shown in phantom in FIG.).Except positive pressure protection diode 610 and Bus Wire 106 and being connected of power supply V2 are disconnected, also can reach the same effect of present embodiment equally by requiring chip manufacturer when making chip, just to omit positive pressure protection diode 610.
Shown in Fig. 3 c the interface circuit synoptic diagram of the multichip system of Fig. 3 a according to the utility model second embodiment.With Fig. 3 b more as can be seen, except the same current path that removes from Bus Wire 106 to power supply V2 with last embodiment, existing negative pressure protection diode is replaced by a Zener diode 608 with suitable disruptive voltage.Wherein, the negative electrode of Zener diode 608 is connected with Bus Wire 106, and its anode is connected with ground.The effect of Zener diode 608 is the destruction that the core logic 604 of defencive function unit 600 is not subjected to high-pressure electrostatic.When big static generation to the disruptive voltage that surpasses Zener diode 608, Zener diode 608 is by reverse penetration, and static i.e. dotted line in the figure is leaked to ground, and makes that core logic 604 is injury-free.On the other hand, as long as the disruptive voltage of Zener diode 608 is greater than the signal level on the input/output bus 100, Zener diode 608 just can be by reverse penetration, and the dotted line in figure forms low-impedance load.In other words, the signal of input/output bus 100 can be because of the power supply of closing a certain functional unit torsional deformation.
Note that also that in addition in Fig. 3 b, 3c, the interface circuit that coenosarc main control unit 300 is adopted is the same with prior art.Also may be implemented in coenosarc main control unit 300 but the interface circuit that the utility model proposed is real, for no other reason than that the power supply V1 of coenosarc main control unit 300 is in the power supply always, the utility model only has the function of electrostatic protection to the coenosarc main control unit.
Also note that on the implementation in addition, in multichip system, owing to may not be that all functional units all can have power supply independent and that optionally close, the embodiment that the utility model proposed can be embodied in partial function unit (just those have the independent and power supply of closing optionally) or whole functional units (just having independent all and the power supply of closing optionally).When with the embodiment shown in Fig. 3 b (just omit or disconnect positive pressure protection diode) when being implemented on whole functional units; the coenosarc main control unit must have positive pressure protection diode or similar protection mechanism; with when high-pressure electrostatic betides input/output bus, the positive pressure protection diode or the similar protection mechanism that can see through coenosarc main control unit 300 are leaked to ground and reach defencive function.
Existing multichip system shown in Fig. 1 a if adopt technology of the present utility model, can become shown in Fig. 3 d.Wherein functional unit 40* and prior function unit 40 basically difference just at the interface circuit of itself and input/output bus 10, by such improvement, the functional unit 40 of multichip system 2 can be independently-powered, to reduce unnecessary power consumption, omitted impact damper simultaneously to save cost of products, but the signal on the input/output bus can the distortion because of the power supply of closing function unit, and the core logic of functional unit is not subjected to the destruction of high-pressure electrostatic.In addition, the improvement on layout area is more notable, the circuit arrangement map that is respectively the multichip system of existing employing impact damper and adopts multichip system of the present utility model shown in Fig. 4 a, the 4b.The circle frame sign person of institute is impact damper among Fig. 4 a.By comparison diagram 4a, 4b as can be seen the utility model significantly save layout area, on behalf of the elasticity on layout, this also also can significantly promote.
By the above detailed description of preferred embodiments, be to wish to know more to describe feature of the present utility model and spirit, and be not to come category of the present utility model is limited with above-mentioned disclosed preferred embodiment.On the contrary, its objective is that hope can contain in the category of the claim that is arranged in the desire application of the utility model institute of various changes and tool equality.
Claims (6)
1. multichip system functional unit interface circuit, it is characterized in that, this multichip system inside comprises at least one coenosarc main control unit, and at least one functional unit, an and input/output bus that connects this coenosarc main control unit and this functional unit, this multichip system drives this coenosarc main control unit and this functional unit respectively with a plurality of independently power supplys, this power supply of this functional unit can optionally independently open and close, this functional unit interface circuit is between this input/output bus and this functional unit, for each Bus Wire of this input/output bus, this interface circuit comprises at least:
One Zener diode, its anode are connected in this multichip system to ground, and its negative electrode is connected in the Bus Wire of this input/output bus, and this Zener diode has a suitable disruptive voltage;
Wherein, between the power supply of this Bus Wire and this functional unit for opening circuit.
2. multichip system functional unit interface circuit as claimed in claim 1 is characterized in that this disruptive voltage is at least greater than the signal level on this input/output bus.
3. multichip system functional unit interface circuit as claimed in claim 1 is characterized in that, one of them is to combine with this multichip system in the plug-in card mode at least for this coenosarc main control unit and this functional unit.
4. multichip system functional unit interface circuit, it is characterized in that, this multichip system inside comprises at least one coenosarc main control unit, and at least one functional unit, an and input/output bus that connects this coenosarc main control unit and this functional unit, this multichip system drives this coenosarc main control unit and this functional unit respectively with a plurality of independently power supplys, the power supply of this functional unit can optionally independently open and close, this functional unit interface circuit is between this input/output bus and this functional unit, for each Bus Wire of this input/output bus, this interface circuit comprises at least:
One diode, its anode are connected in this multichip system to ground, and its negative electrode is connected in the Bus Wire of this input/output bus;
Wherein, between this power supply of this Bus Wire and this functional unit for opening circuit.
5. multichip system functional unit interface circuit as claimed in claim 4 is characterized in that, one of them is to combine with this multichip system in the plug-in card mode at least for this coenosarc main control unit and this functional unit.
6. multichip system functional unit interface circuit as claimed in claim 4, it is characterized in that, one interface circuit of this coenosarc main control unit and this input/output bus, each Bus Wire for this input/output bus, this interface circuit comprises a diode at least, its anode is connected in this Bus Wire of this input/output bus, and its negative electrode is connected in this power supply of this coenosarc main control unit, to sew high-pressure electrostatic.
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| CN 200620122167 CN200979682Y (en) | 2006-07-17 | 2006-07-17 | Multi-chip system functional unit interface circuit |
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| CN 200620122167 CN200979682Y (en) | 2006-07-17 | 2006-07-17 | Multi-chip system functional unit interface circuit |
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| CN200979682Y true CN200979682Y (en) | 2007-11-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102077185A (en) * | 2008-09-08 | 2011-05-25 | 思科技术公司 | Input-output module, processing platform and method for extending a memory interface for input-output operations |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102077185A (en) * | 2008-09-08 | 2011-05-25 | 思科技术公司 | Input-output module, processing platform and method for extending a memory interface for input-output operations |
| CN102077185B (en) * | 2008-09-08 | 2014-07-16 | 思科技术公司 | Input-output module, processing platform and method for extending a memory interface for input-output operations |
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Effective date of registration: 20090320 Address after: Postcode of Taiwan County, Taipei, china: Patentee after: ADATA TECHNOLOGY Co.,Ltd. Address before: Postcode of Taiwan, Taipei, china: Co-patentee before: ADATA TECHNOLOGY Co.,Ltd. Patentee before: Zhuang Pinyang |
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Owner name: WEIGANG TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: ZHUANG PINYANG Effective date: 20090320 |
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Granted publication date: 20071121 Termination date: 20100717 |