CN200941601Y - Pulse signals generator - Google Patents
Pulse signals generator Download PDFInfo
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- CN200941601Y CN200941601Y CN 200620133009 CN200620133009U CN200941601Y CN 200941601 Y CN200941601 Y CN 200941601Y CN 200620133009 CN200620133009 CN 200620133009 CN 200620133009 U CN200620133009 U CN 200620133009U CN 200941601 Y CN200941601 Y CN 200941601Y
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Abstract
The utility model is a pulse signal generation device which is used in an electronic device to generate pulse signal, comprising a first delayed signal generation circuit, a second delayed signal generation circuit, a third delayed signal generation circuit, a first logical switch and a second logical switch. After the pulse signal generation device receives the voltage signal, the first pulse signal is produced through the first logical switch by mean of the delayed signal produced by the first delayed signal generation circuit and the second delayed signal generation circuit. The delayed signal produced by the first pulse signal and the third pulse signal generation circuit passes through the second logical switch, the second pulse signal is produced by mean of this.
Description
Technical field
The utility model relates to a kind of pulse signal generation device, particularly relates to a kind of pulse signal generation device that utilizes ball bearing made using to form.
Background technology
In computer system now, when starting computer system, can need a startup signal and allow computer system begin effect.Starting signal normally utilizes one or several electronegative potential pulses (Low Pulse) to be used as the startup signal of computer system.
In the middle of prior art, just as shown in Figure 1a, Fig. 1 a is the circuit diagram that can produce an electronegative potential pulse in the prior art.If as long as produce an electronegative potential pulse, only the delay signal generating circuit 90 that need utilize single resistance and electric capacity to form produces a delay signal, just can be used for being used as the electronegative potential pulse signal.Then, again the electronegative potential pulse signal is passed to central processing unit 61 as starting signal.
If produce several electronegative potential pulses, then will be with reference to figure 1b, Fig. 1 b is the circuit diagram that will produce several electronegative potential pulses in the prior art.In the middle of prior art, can increase a low order microprocessor (Low end micro processor) 91 generation devices again postponing after 90s of signal generating circuit usually as a plurality of electronegative potential pulses.A plurality of electronegative potential pulses are sent to central processing unit 61 again, in order to the startup signal as central processing unit 61.But use the assembly cost of low order microprocessor 91 will be thus, and need write out a kind of firmware of controlling especially with regard to this situation and control the signal that this low order microprocessor 91 is produced than higher.
Therefore, if can design a kind of pulse signal generation device more easier that have, then can save down and set up required manpower of pulse signal generation device or material resources than prior art.
The utility model content
Main purpose of the present utility model provides a kind of pulse signal generation device, and device is located in the electronic installation, can produce a plurality of pulse signals and reach the effect that reduces cost.
For realizing above-mentioned purpose, first embodiment of the utility model pulse signal generation device has comprised that first postpones signal generating circuit, the second delay signal generating circuit, the 3rd delay signal generating circuit, first logic switch, second logic switch, first inverter, second inverter and first buffer.
First postpones signal generating circuit, the second delay signal generating circuit and the 3rd delay signal generating circuit is formed by utilizing resistance and electric capacity.First logic switch, second logic switch, first inverter, second inverter and first buffer all can utilize N type MOS transistor (NMOS) or P type MOS transistor (PMOS) or other similar assembly to form.
First postpones signal generating circuit is electrically connected with first inverter, and the principle of utilizing internal capacitance to discharge and recharge after voltage signal of reception, will produce first and postpone signal.Second postpones signal generating circuit is electrically connected with second inverter, produces second and postpones signal.The 3rd delay signal generating circuit then is can be electrically connected to produce the 3rd with first buffer to postpone signal.First buffer is used for putting in order the usefulness of ripple, with the signal of guaranteeing last output apparent in view waveform can be arranged.
First postpones signal and second postpones signal and can allow first logic switch is made up of the NMOS assembly receive and carry out signal conversion.First postpones the source electrode that signal is received first logic switch, and second postpones the base stage that signal is received first logic switch, and is exported by the drain electrode of first logic switch, just can obtain first pulse signal.Then the 3rd postpones the source electrode that signal is received second logic switch, and first pulse signal is received the base stage of second logic switch, and the drain electrode of second logic switch just can be exported second pulse signal.
In another embodiment of the utility model pulse signal generation device, second postpone that signal generating circuit produced second postpone signal except the base stage of receiving first logic switch, the power signal that is used for being used as first logic switch too.Therefore when the second delay signal is electronegative potential, first logic switch will be exported the electronegative potential signal as the logic switch that do not have the power supply supply, make to win.The waveform of being exported is first pulse signal.The 3rd postpones signal generating circuit is electrically connected with second inverter to produce the 3rd delay signal.The 3rd postpones the base stage that signal is connected to second logic switch, and first pulse signal is connected to the source electrode of second logic switch, just can produce second pulse signal thus.
The utility model can increase a plurality of extension circuits again except above-mentioned basic circuit.Extension circuit can include the 4th and postpone signal generating circuit, the 5th delay signal generating circuit, the 3rd logic switch and the 4th logic switch.Increase a plurality of extension circuits and can produce a plurality of electronegative potential pulse signals.
The utility model structure is novel, can provide on the industry and utilize, and truly have the enhancement effect.
Description of drawings
Fig. 1 a is the circuit diagram that can produce an electronegative potential pulse in the prior art.
Fig. 1 b is the circuit diagram that will produce several electronegative potential pulses in the prior art.
Fig. 2 is a system of the present utility model block schematic diagram.
Fig. 3 is the calcspar of first embodiment of the utility model pulse signal generation device.
Fig. 4 is the circuit diagram of first embodiment of the utility model pulse signal generation device.
Fig. 5 is the oscillogram that first embodiment of the utility model pulse signal generation device produces.
Fig. 6 is the calcspar of second embodiment of the utility model pulse signal generation device.
Fig. 7 is the circuit diagram of second embodiment of the utility model pulse signal generation device.
Fig. 8 is the oscillogram that second embodiment of the utility model pulse signal generation device produces.
Fig. 9 is the calcspar of the 3rd embodiment of the utility model pulse signal generation device.
Figure 10 is the circuit diagram of extension circuit among the 3rd embodiment of the utility model pulse signal generation device.
Figure 11 is the oscillogram that extension circuit produces among the 3rd embodiment of the utility model pulse signal generation device.
Reference numeral is said
Pulse signal generation device 10
First postpones signal generating circuit 21,21 '
Second postpones signal generating circuit 22,22 '
The 3rd postpones signal generating circuit 23,23 '
The 4th postpones signal generating circuit 24
The 5th postpones signal generating circuit 25
The 3rd logic switch 33
The 4th logic switch 34
First inverter 41,41 '
The 3rd buffer 53
Central processing unit 61
Light-emitting diode 62
Postpone signal generating circuit 90
First postpones signal A01, A01 '
Second postpones signal A02, A02 '
The 3rd postpones signal A03, A03 '
The 4th postpones signal A04
The 5th postpones signal A05
The first pulse signal B01, B01 '
The second pulse signal B02, B02 '
The 3rd pulse signal B03
The 4th pulse signal B04
Embodiment
For understanding technology contents of the present utility model better, be described as follows especially exemplified by several preferred embodiment.
At first, system's square of the utility model pulse signal generation device 10 and electronic installation 60 as shown in Figure 2, Fig. 2 is a system of the present utility model block schematic diagram.Pulse signal generation device 10 is located in the electronic installation 60, and electronic installation 60 can be computer system or other similar device.Power supply device 13 among the figure can be the battery of electronic installation 60 inside or external power supply, and the utility model is not as limit.After the pulse signal generation device in the electronic installation 60 10 receives the voltage signal of power supply device 13, promptly produce pulse signal and pass to the startup signal of central processing unit 61 as central processing unit 61.And the purposes of pulse signal generation device 10 of the present utility model is not to be only limited to this, and the electronic installation 60 of (LED) 62 that also can be applicable to have light-emitting diode is for example on other device such as charging device or toy.
Please refer to Fig. 3, Fig. 3 is the calcspar of first embodiment of the utility model pulse signal generation device 10.The basic circuit 11 of pulse signal generation device 10 receives the voltage signal that power supply device 13 is supplied, and in order to produce two electronegative potential pulse signals.Basic circuit 11 comprises that first postpones signal generating circuit 21, the second delay signal generating circuit 22, the 3rd delay signal generating circuit 23, first logic switch 31, second logic switch 32, first inverter 41, second inverter 42 and first buffer 51.After basic circuit 11 produces two electronegative potential pulse signals, supply with central processing unit 61, as the startup signal of central processing unit 61.
The detailed action principle of basic circuit 11 please refer to shown in Figure 4, and Fig. 4 is the circuit diagram of first embodiment of the utility model pulse signal generation device 10.And please in the lump with reference to figure 5, Fig. 5 is the generation oscillogram of first embodiment of the utility model pulse signal generation device 10.
In basic circuit 11, first postpones signal generating circuit 21, second postpones signal generating circuit 22 and the 3rd to postpone signal generating circuit 23 is the circuit that utilizes resistance and electric capacity to form, and produces the delay signal by the characteristic that discharges and recharges of electric capacity.In the present embodiment, first logic switch 31, second logic switch 32, first inverter 41, second inverter 42 and first buffer 51 are to be example with N type MOS transistor (NMOS), but the utility model is not as limit, and said modules also can be P type MOS transistor (PMOS) or other similar device.
First postpones signal generating circuit 21 utilizes internal capacitance to discharge and recharge, and outside first inverter of being made up of the NMOS assembly 41, by receiving a voltage signal (VCC) afterwards, will produce first and postpone signal A01.In like manner, the second delay signal generating circuit 22 also is same mode, is electrically connected with second inverter 42, produces second and postpones signal A02.The 3rd 23 of signal generating circuits of delay are can be electrically connected to produce the 3rd with first buffer 51 to postpone signal A03.First buffer 51 is used for putting in order the usefulness of ripple, with the signal of guaranteeing last output apparent in view waveform can be arranged.
Be noted that, wherein must postpone the time of delay of signal A02 greater than second the 3rd time of delay that postpones signal A03; Must could produce correct waveform at last thus second time of delay that postpones signal A02 greater than the time of delay of the first delay signal A01.Guarantee above-mentioned situation, can utilize the size of resistance-capacitance value to guarantee the difference of time of delay.Also can be as the mode of connection in the middle of Fig. 3, after the first delay signal generating circuit 21 had charged, second postpones signal generating circuit 22 just charged; The 3rd delay signal generating circuit 23 just charged after the second delay signal generating circuit 22 had charged.Just can guarantee that by the above-mentioned mode of connection each postpones length time of delay of signal.
First postpones signal A01 and second postpones signal A02 and can allow first logic switch 31 is made up of the NMOS assembly receive and carry out signal conversion.First postpones the source electrode that signal A01 receives first logic switch 31, and second postpones the base stage that signal A02 receives first logic switch 31, and is exported by the drain electrode of first logic switch 31.The initial first delay signal A01 and second postpones signal A02 and all is in the high potential signal, and the high potential signal is also exported in drain electrode.Then the first delay signal A01 changes the electronegative potential signal into, drain electrode output electronegative potential signal.The second last postpones signal A02 and also becomes the electronegative potential signal, and output high potential signal is replied in drain electrode.Obtain the first pulse signal B01 thus.
Then the 3rd postpones the source electrode that signal A03 receives second logic switch 32, and the first pulse signal B01 receives the base stage of second logic switch 32.The 3rd delay signal A03 is the electronegative potential signal when beginning, and the waveform that the drain electrode of second logic switch 32 is exported at the beginning is the anti-phase waveform of the first pulse signal B01.When the 3rd delay signal A03 changed the high potential signal into, the high potential signal was also exported in drain electrode, and that exported is exactly the second pulse signal B02.The second pulse signal B02 is the waveform with two electronegative potential signals.
The utility model also can produce two electronegative potential signals as the mode of connection of second embodiment.Please refer to Fig. 6, Fig. 6 is the calcspar of second embodiment of the utility model pulse signal generation device 10.In a second embodiment, basic circuit 11 ' similarly has first to postpone signal generating circuit 21 ', the second delay signal generating circuit 22 ', the 3rd delay signal generating circuit 23 ', first logic switch 31 ', second logic switch 32 ', first inverter 41 ' and second inverter 42 ', the composition mode of each assembly is also identical with first embodiment, has only circuit ways of connecting difference.The detailed mode of connection please refer to Fig. 7, and Fig. 7 is the circuit diagram of second embodiment of the utility model pulse signal generation device 10.And please in the lump with reference to figure 8, Fig. 8 is the oscillogram that second embodiment of the utility model pulse signal generation device 10 produces.
In the present embodiment, first postpones the not whole ripple of process buffer of signal generating circuit 21 ', and therefore first postpones the waveform that signal A01 ' is linear rising, promptly represents the characteristic of capacitor charge and discharge.First postpones the source electrode that signal A01 ' receives first logic switch 31 '.Then second postpones signal generating circuit 22 ' through the second delay signal A02 ' that first inverter 41 ' is produced, and receives the base stage of first logic switch 31 '.Second postpones signal A02 ' input high potential signal earlier, and when first postpones magnitude of voltage of signal A01 ' charging arrival (being 1 volt in the present embodiment), first logic switch 31 ' just directly cuts out, and the drain electrode of first logic switch 31 ' will be exported the high potential signal.The difference of second embodiment and the first embodiment maximum is, second postpone that signal generating circuit 22 ' produced second postpone signal A02 ' except the base stage of receiving first logic switch 31 ', the power signal that is used for being used as first logic switch 31 ' too.Therefore when the second delay signal A02 ' was the electronegative potential signal, first logic switch 31 ' was as not having the power supply supply, make logic switch 31 ' the output electronegative potential signal of winning.The waveform of being exported is the first pulse signal B01 '.
The 3rd postpones signal generating circuit 23 ' is electrically connected with second inverter 42 ' to produce the 3rd delay signal A03 '.The 3rd postpones the base stage input of signal A03 ' in second logic switch 32 ', and the first pulse signal B01 ' is connected to the source electrode of second logic switch 32 '.The drain electrode of second logic switch 32 ' is output and the similar waveform of the first pulse signal B01 ' earlier, and when the 3rd postponed signal A03 ' by high potential commentaries on classics electronegative potential signal, the high potential signal was just exported in drain electrode.Just produce the second pulse signal B02 ' thus.The second pulse signal B02 ' is the waveform with two electronegative potential signals.
In a second embodiment, basic circuit 11 ' still can obtain the second complete pulse signal B02 ' of waveform under the condition that does not comprise buffer.First embodiment needs to add buffer, and the waveform of gained could be comparatively complete.Therefore with regard to required assembly, comparable first embodiment of second embodiment uses two NMOS assemblies less, can more save on manufacturing cost.
Next please refer to Fig. 9, Fig. 9 is the calcspar of the 3rd embodiment of the utility model pulse signal generation device 10.Pulse signal generation device 10 of the present utility model is not limited to produce two above-mentioned electronegative potential pulse signals, can increase several extension circuits 12 again and can produce several electronegative potential pulse signals.In the present embodiment, extension circuit 12 is as the extension of basic circuit 11 among first embodiment, however the utility model not as limit, extension circuit 12 also can be as the extension of the second embodiment basic circuit 11 '.
Similar with basic circuit 11, include the 4th in the extension circuit 12 and postpone signal generating circuit 24, the 5th delay signal generating circuit 25, the 3rd logic switch 33, the 4th logic switch 34, second buffer 52 and the 3rd buffer 53.
The 4th postpones signal generating circuit 24 postpones signal A03 by receiving the 3rd in the basic circuit 11, again through second buffer 52, postpones signal A04 to produce the 4th.The 5th postpones signal generating circuit 25 receives the 4th delay signal A04, again through the 3rd buffer 53, postpones signal A05 to produce the 5th.By the above mode of connection, just can guarantee that the delay signal that produces all can have appropriate time at interval.If do not require whole ripple, second buffer 52 and the 3rd buffer 53 just can not need to add, and also can save the partly cost of NMOS assembly thus.
Postpone the source electrode that signal A04 passes to the 3rd logic switch 33 with the 4th then, the base stage of the 3rd logic switch 33 receives the second pulse signal B02 that basic circuit 11 produces simultaneously, and the drain electrode of the 3rd logic switch 33 will be exported the 3rd pulse signal B03.The 3rd pulse signal B03 passes to the base stage of the 4th logic switch 34 again, and the source electrode of the 4th logic switch 34 receives the 5th and postpones signal A05, will obtain the 4th pulse signal B04.Above-mentioned the 3rd logic switch 33 is similar to the action principle of logic switch among first, second embodiment to the action principle of the 4th logic switch 34, so do not repeat them here.The 4th pulse signal B04 is the signal with three electronegative potential pulses.
The utility model has more than to be limited to can only increase an extension circuit 12, and pulse signal generation device 10 can increase the quantity of extension circuit 12 according to the various different demands of electronic installation 60, in order to produce the different pulse signal of various umber of pulses.
In sum, no matter the utility model is with regard to purpose, means and effect, all different and be better than the feature of prior art.Above-mentioned a plurality of embodiment of the present utility model give an example for convenience of explanation, and interest field of the present utility model should be as the criterion with claim of the present utility model certainly, but not only limits to the foregoing description.
Claims (19)
1. pulse signal generation device in order to receive a voltage signal to produce a pulse signal, is characterized in that this pulse signal generation device comprises:
One first postpones signal generating circuit, is electrically connected with one first inverter, postpones signal in order to receive this voltage signal and to produce one first;
One second postpones signal generating circuit, is electrically connected with one second inverter, postpones signal in order to receive this voltage signal and to produce one second;
One the 3rd postpones signal generating circuit, postpones signal in order to receive this voltage signal and to produce one the 3rd;
One first logic switch, this first logic switch receive this first delay signal and this second delay signal, to produce one first pulse signal; And
One second logic switch, this second logic switch receive this first pulse signal and the 3rd and postpone signal, to produce one second pulse signal and to export this second pulse signal.
2. pulse signal generation device as claimed in claim 1, wherein this first inverter, this second inverter, this first logic switch and this second logic switch are a N type MOS transistor or a P type MOS transistor.
3. pulse signal generation device as claimed in claim 1, wherein this first delay signal generating circuit, this second delay signal generating circuit and the 3rd delay signal generating circuit are to utilize resistance and an electric capacity to form.
4. pulse signal generation device as claimed in claim 1, wherein the 3rd delay signal generating circuit also is electrically connected with a buffer, puts in order ripple in order to postpone signal to the 3rd.
5. pulse signal generation device as claimed in claim 4, wherein this buffer is at least one N type MOS transistor or P type MOS transistor.
6. pulse signal generation device as claimed in claim 1, wherein the 3rd postpones the time of delay of the time of delay of signal greater than this second delay signal; The time of delay of this second delay signal is greater than the time of delay of this first delay signal.
7. pulse signal generation device as claimed in claim 1 is characterized in that further comprising an extension circuit, and this extension circuit comprises:
One the 4th postpones signal generating circuit, postpones signal in order to produce one the 4th;
One the 5th postpones signal generating circuit, postpones signal in order to produce one the 5th;
One the 3rd logic switch, the 3rd logic switch receive this second pulse signal and the 4th and postpone signal, to produce one the 3rd pulse signal; And
One the 4th logic switch, the 4th logic switch receive the 3rd pulse signal and the 5th and postpone signal, to produce one the 4th pulse signal and to export the 4th pulse signal.
8. pulse signal generation device in order to receive a voltage signal to produce a pulse signal, is characterized in that this pulse signal generation device comprises:
One first postpones signal generating circuit, postpones signal in order to receive this voltage signal and to produce one first;
One second postpones signal generating circuit, is electrically connected with one first inverter, postpones signal in order to receive this voltage signal and to produce one second;
One the 3rd postpones signal generating circuit, is electrically connected with one second inverter, postpones signal in order to receive this voltage signal and to produce one the 3rd;
One first logic switch, this first logic switch receive this first delay signal and this first inverse delayed signal, and utilize the power signal of this first inverse delayed signal as this first logic switch, to produce one first pulse signal; And
One second logic switch, this second logic switch receive this first pulse signal and this second inverse delayed signal, to produce one second pulse signal and to export this second pulse signal.
9. pulse signal generation device as claimed in claim 8, wherein this first inverter and this second inverter, this first logic switch and this second logic switch are a N type MOS transistor or a P type MOS transistor.
10. pulse signal generation device as claimed in claim 8, wherein this first delay signal generating circuit, this second delay signal generating circuit and the 3rd delay signal generating circuit are to utilize resistance and an electric capacity to form.
11. pulse signal generation device as claimed in claim 8, wherein the 3rd postpones the time of delay of the time of delay of signal greater than this second delay signal; The time of delay of this second delay signal is greater than the time of delay of this first delay signal.
12. pulse signal generation device as claimed in claim 8 is characterized in that further comprising an extension circuit, this extension circuit comprises:
One the 4th postpones signal generating circuit, postpones signal in order to produce one the 4th;
One the 5th postpones signal generating circuit, postpones signal in order to produce one the 5th;
One the 3rd logic switch, the 3rd logic switch receive this second pulse signal and the 4th and postpone signal, to produce one the 3rd pulse signal; And
One the 4th logic switch, the 4th logic switch receive the 3rd pulse signal and the 5th and postpone signal, to produce one the 4th pulse signal and to export the 4th pulse signal.
13. an electronic installation is characterized in that comprising:
One power supply device is in order to produce a voltage signal; And
One pulse signal generation device, in order to receive this voltage signal and to produce a pulse signal, this pulse signal generation device comprises:
One first postpones signal generating circuit, postpones signal in order to receive this voltage signal and to produce one first;
One second postpones signal generating circuit, is electrically connected with one first inverter, postpones signal in order to receive this voltage signal and to produce one second;
One the 3rd postpones signal generating circuit, is electrically connected with one second inverter, postpones signal in order to receive this voltage signal and to produce one the 3rd;
One first logic switch, this first logic switch receive this first delay signal and this first inverse delayed signal, and utilize the power signal of this first inverse delayed signal as this first logic switch, to produce one first pulse signal; And
One second logic switch, this second logic switch receive this first pulse signal and this second inverse delayed signal, to produce one second pulse signal and to export this second pulse signal.
14. electronic installation as claimed in claim 13 is characterized in that also comprising a central processing unit or a light-emitting diode, in order to receive this pulse signal.
15. electronic installation as claimed in claim 13, wherein this electronic installation can be a computer system.
16. electronic installation as claimed in claim 13, wherein this first inverter and this second inverter, this first logic switch and this second logic switch are a N type MOS transistor or a P type MOS transistor.
17. electronic installation as claimed in claim 13, wherein this first delay signal generating circuit, this second delay signal generating circuit and the 3rd delay signal generating circuit are to utilize resistance and an electric capacity to form.
18. electronic installation as claimed in claim 13, wherein the 3rd postpones the time of delay of the time of delay of signal greater than this second delay signal; The time of delay of this second delay signal is greater than the time of delay of this first delay signal.
19. electronic installation as claimed in claim 13, wherein this pulse signal generation device further comprises an extension circuit, and this extension circuit comprises:
One the 4th postpones signal generating circuit, postpones signal in order to produce one the 4th;
One the 5th postpones signal generating circuit, postpones signal in order to produce one the 5th;
One the 3rd logic switch, the 3rd logic switch receive this second pulse signal and the 4th and postpone signal, to produce one the 3rd pulse signal; And
One the 4th logic switch, the 4th logic switch receive the 3rd pulse signal and the 5th and postpone signal, to produce one the 4th pulse signal and to export the 4th pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620133009 CN200941601Y (en) | 2006-08-17 | 2006-08-17 | Pulse signals generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620133009 CN200941601Y (en) | 2006-08-17 | 2006-08-17 | Pulse signals generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN200941601Y true CN200941601Y (en) | 2007-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200620133009 Expired - Fee Related CN200941601Y (en) | 2006-08-17 | 2006-08-17 | Pulse signals generator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860351B (en) * | 2009-04-09 | 2012-12-12 | 智原科技股份有限公司 | Circuit for cancelling pulse interference |
-
2006
- 2006-08-17 CN CN 200620133009 patent/CN200941601Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860351B (en) * | 2009-04-09 | 2012-12-12 | 智原科技股份有限公司 | Circuit for cancelling pulse interference |
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