CN200941601Y - pulse signal generator - Google Patents

Abstract

The utility model is a pulse signal generating device, which is used in an electronic device to generate a pulse signal. It includes a first delay signal generating circuit, a second delay signal generating circuit, a third delay signal generating circuit, a first logic switch and a second logic switch. After the pulse signal generating device receives a voltage signal, the delay signal generated by the first delay signal generating circuit and the second delay signal generating circuit can generate a first pulse signal through the first logic switch. The first pulse signal and the delay signal generated by the third delay signal generating circuit are then passed through the second logic switch to generate a second pulse signal.

Description

pulse signal generator

technical field

The utility model relates to a pulse signal generating device, in particular to a pulse signal generating device composed of a simple circuit.

Background technique

In today's computer systems, when the computer system is started, an activation signal is required to allow the computer system to function. The start signal usually uses one or several low potential pulses (Low Pulse) as the start signal of the computer system.

In the prior art, as shown in FIG. 1a, FIG. 1a is a circuit diagram for generating a low potential pulse in the prior art. If only a low-potential pulse is to be generated, it is only necessary to use the delay signal generating circuit 90 composed of a single resistor and capacitor to produce a delayed signal, which can be used as a low-potential pulse signal. Then, the low potential pulse signal is transmitted to the central processing unit 61 as an activation signal.

If it is necessary to generate several low-potential pulses, refer to FIG. 1 b , which is a circuit diagram for generating several low-potential pulses in the prior art. In the prior art, a low end microprocessor (Low end micro processor) 91 is usually added behind the delay signal generating circuit 90 as a device for generating multiple low potential pulses. The multiple low potential pulses are then sent to the central processing unit 61 as an activation signal for the central processing unit 61 . But in this way, the component cost of using the low-level microprocessor 91 will be relatively high, and it is also necessary to write a special control firmware to control the signals generated by the low-level microprocessor 91 for this situation.

Therefore, if a pulse signal generating device that is simpler than the prior art can be designed, the manpower or material resources required to build the pulse signal generating device can be saved.

Utility model content

The main purpose of the utility model is to provide a pulse signal generating device, which is installed in an electronic device, can generate multiple pulse signals and achieve the effect of reducing cost.

In order to achieve the above-mentioned purpose, the first embodiment of the pulse signal generating device of the present utility model includes a first delay signal generating circuit, a second delay signal generating circuit, a third delay signal generating circuit, a first logic switch, a second logic switch , the first inverter, the second inverter and the first buffer.

The first delay signal generating circuit, the second delay signal generating circuit and the third delay signal generating circuit are composed of resistors and capacitors. The first logic switch, the second logic switch, the first inverter, the second inverter and the first buffer can all use N-type metal oxide transistors (NMOS) or P-type metal oxide transistors (PMOS) or other composed of similar components.

The first delay signal generating circuit is electrically connected with the first inverter, and generates the first delay signal after receiving a voltage signal by using the principle of charging and discharging the internal capacitor. The second delay signal generating circuit is electrically connected with the second inverter to generate the second delay signal. The third delay signal generating circuit can be electrically connected with the first buffer to generate the third delay signal. The first buffer is used for wave rectification to ensure that the final output signal can have a more obvious waveform.

The first delay signal and the second delay signal allow the first logic switch composed of NMOS components to receive and perform signal conversion. The first delay signal is connected to the source of the first logic switch, the second delay signal is connected to the base of the first logic switch, and is output from the drain of the first logic switch to obtain the first pulse signal. Then the third delay signal is connected to the source of the second logic switch, the first pulse signal is connected to the base of the second logic switch, and the drain of the second logic switch can output the second pulse signal.

In another embodiment of the pulse signal generating device of the present invention, the second delay signal generated by the second delay signal generating circuit is also used as the first logic switch in addition to being connected to the base of the first logic switch. The power signal of the switch. Therefore, when the second delay signal is at low potential, the first logic switch acts as if there is no power supply, so that the first logic switch outputs a low potential signal. The output waveform is the first pulse signal. The third delay signal generating circuit is electrically connected with the second inverter to generate the third delay signal. The third delay signal is connected to the base of the second logic switch, and the first pulse signal is connected to the source of the second logic switch, so that the second pulse signal can be generated.

In addition to the above-mentioned basic circuit, the utility model can add a plurality of extension circuits. The extension circuit may include a fourth delay signal generating circuit, a fifth delay signal generating circuit, a third logic switch and a fourth logic switch. Multiple low-potential pulse signals can be produced by adding multiple extension circuits.

The utility model has a novel structure, can be applied in industry, and has indeed improved effects.

Description of drawings

Fig. 1a is a circuit diagram for generating a low potential pulse in the prior art.

FIG. 1b is a circuit diagram for generating several low potential pulses in the prior art.

FIG. 2 is a schematic block diagram of the system of the present invention.

FIG. 3 is a block diagram of the first embodiment of the pulse signal generating device of the present invention.

FIG. 4 is a circuit diagram of the first embodiment of the pulse signal generating device of the present invention.

FIG. 5 is a waveform diagram generated by the first embodiment of the pulse signal generating device of the present invention.

FIG. 6 is a block diagram of a second embodiment of the pulse signal generating device of the present invention.

FIG. 7 is a circuit diagram of the second embodiment of the pulse signal generating device of the present invention.

FIG. 8 is a waveform diagram generated by the second embodiment of the pulse signal generating device of the present invention.

FIG. 9 is a block diagram of a third embodiment of the pulse signal generating device of the present invention.

FIG. 10 is a circuit diagram of the extension circuit in the third embodiment of the pulse signal generating device of the present invention.

FIG. 11 is a waveform diagram generated by the extension circuit in the third embodiment of the pulse signal generating device of the present invention.

fig says

Pulse signal generator 10

Basic circuit 11, 11'

Extension circuit 12

Power supply unit 13

The first delay signal generation circuit 21, 21'

The second delay signal generating circuit 22, 22'

The third delay signal generation circuit 23, 23'

The fourth delay signal generating circuit 24

The fifth delay signal generating circuit 25

First logic switch 31, 31'

Second logic switch 32, 32'

third logic switch 33

Fourth logic switch 34

First inverter 41, 41'

Second inverter 42, 42'

first buffer 51

Second buffer 52

third buffer 53

Electronics 60

cpu61

LED 62

Delay signal generating circuit 90

Low-level microprocessor 91

The first delayed signal A01, A01'

The second delayed signal A02, A02'

The third delayed signal A03, A03'

Fourth delayed signal A04

Fifth delayed signal A05

The first pulse signal B01, B01'

The second pulse signal B02, B02'

The third pulse signal B03

The fourth pulse signal B04

Detailed ways

In order to better understand the technical content of the present utility model, several preferred specific embodiments are described as follows.

First, the system blocks of the pulse signal generating device 10 and the electronic device 60 of the present invention are shown in FIG. 2 , which is a schematic diagram of the system block of the present invention. The pulse signal generating device 10 is set in an electronic device 60, and the electronic device 60 can be a computer system or other similar devices. The power supply device 13 in the figure can be a battery inside the electronic device 60 or an external power supply, and the present invention is not limited thereto. When the pulse signal generating device 10 in the electronic device 60 receives the voltage signal from the power supply device 13 , it generates a pulse signal and transmits it to the central processing unit 61 as an activation signal for the central processing unit 61 . Moreover, the application of the pulse signal generating device 10 of the present invention is not limited thereto, and can also be applied to an electronic device 60 having a light emitting diode (LED) 62 , such as a charging device or a toy and other devices.

Please refer to FIG. 3 , which is a block diagram of a first embodiment of the pulse signal generating device 10 of the present invention. The basic circuit 11 of the pulse signal generating device 10 receives the voltage signal supplied by the power supply device 13 and is used to generate two low potential pulse signals. The basic circuit 11 includes a first delay signal generation circuit 21, a second delay signal generation circuit 22, a third delay signal generation circuit 23, a first logic switch 31, a second logic switch 32, a first inverter 41, a second inverter The phaser 42 and the first buffer 51. After the basic circuit 11 generates two low potential pulse signals, they are supplied to the central processing unit 61 as an activation signal for the central processing unit 61 .

Please refer to FIG. 4 for the detailed working principle of the basic circuit 11 . FIG. 4 is a circuit diagram of the first embodiment of the pulse signal generating device 10 of the present invention. Please also refer to FIG. 5 . FIG. 5 is a waveform diagram of the first embodiment of the pulse signal generating device 10 of the present invention.

In the basic circuit 11, the first delay signal generating circuit 21, the second delay signal generating circuit 22, and the third delay signal generating circuit 23 are circuits composed of resistors and capacitors, and delays are generated by the characteristics of charging and discharging of capacitors. signal. In this embodiment, the first logic switch 31, the second logic switch 32, the first inverter 41, the second inverter 42, and the first buffer 51 are N-type metal oxide transistors (NMOS) as an example. , but the utility model is not limited thereto, and the above-mentioned components may also be P-type metal oxide transistors (PMOS) or other similar devices.

The first delay signal generation circuit 21 generates the first delay signal A01 after receiving a voltage signal (VCC) by charging and discharging the internal capacitor and the external first inverter 41 composed of NMOS components. Similarly, the second delay signal generating circuit 22 is also electrically connected to the second inverter 42 to generate the second delay signal A02 in the same manner. The third delay signal generation circuit 23 can be electrically connected with the first buffer 51 to generate the third delay signal A03. The first buffer 51 is used for wave rectification to ensure that the final output signal can have a more obvious waveform.

It should be noted that the delay time of the third delay signal A03 must be greater than the delay time of the second delay signal A02; the delay time of the second delay signal A02 must be greater than the delay time of the first delay signal A01, so that the final correct waveform. To ensure the above situation, the difference in delay time can be ensured by using the values of resistors and capacitors. It can also be connected as shown in Figure 3. After the first delay signal generating circuit 21 is charged, the second delay signal generating circuit 22 is charged; after the second delay signal generating circuit 22 is charged, the third delay signal generating circuit 23 before charging. The delay time length of each delay signal can be ensured by the above wiring method.

The first delay signal A01 and the second delay signal A02 allow the first logic switch 31 composed of NMOS components to receive and perform signal conversion. The first delayed signal A01 is connected to the source of the first logic switch 31 , and the second delayed signal A02 is connected to the base of the first logic switch 31 and outputted from the drain of the first logic switch 31 . Initially, both the first delayed signal A01 and the second delayed signal A02 are high potential signals, and the drains also output high potential signals. Then the first delayed signal A01 changes to a low potential signal, and the drain outputs a low potential signal. Finally, the second delayed signal A02 also becomes a low potential signal, and the drain returns to output a high potential signal. In this way, the first pulse signal B01 is obtained.

Then the third delay signal A03 is connected to the source of the second logic switch 32 , and the first pulse signal B01 is connected to the base of the second logic switch 32 . The third delay signal A03 is a low potential signal at the beginning, and the waveform initially output by the drain of the second logic switch 32 is the inverted waveform of the first pulse signal B01 . Until the third delay signal A03 changes to a high potential signal, the drain also outputs a high potential signal, and the output is the second pulse signal B02. The second pulse signal B02 is a waveform with two low potential signals.

The present invention can also generate two low-potential signals in the wiring method of the second embodiment. Please refer to FIG. 6 , which is a block diagram of a second embodiment of the pulse signal generating device 10 of the present invention. In the second embodiment, the basic circuit 11' also has a first delay signal generating circuit 21', a second delay signal generating circuit 22', a third delay signal generating circuit 23', a first logic switch 31', a second The logic switch 32 ′, the first inverter 41 ′ and the second inverter 42 ′ are composed in the same way as the first embodiment, only the way of circuit connection is different. Please refer to FIG. 7 for the detailed wiring method. FIG. 7 is a circuit diagram of the second embodiment of the pulse signal generating device 10 of the present invention. Please also refer to FIG. 8 . FIG. 8 is a waveform diagram generated by the second embodiment of the pulse signal generating device 10 of the present invention.

In this embodiment, the first delayed signal generating circuit 21' does not undergo wave rectification by the buffer, so the first delayed signal A01' is a linearly rising waveform, which represents the characteristics of capacitor charging and discharging. The first delay signal A01' is connected to the source of the first logic switch 31'. Then, the second delayed signal A02' generated by the second delayed signal generating circuit 22' is connected to the base of the first logic switch 31' through the first inverter 41'. The second delay signal A02' will first input a high potential signal, and when the charge of the first delay signal A01' reaches a voltage value (1 volt in this embodiment), the first logic switch 31' is directly closed, and the first The drain of the logic switch 31' will output a high potential signal. The biggest difference between the second embodiment and the first embodiment is that the second delayed signal A02' generated by the second delayed signal generating circuit 22' is not only connected to the base of the first logic switch 31', but also used for Serve as the power signal of the first logic switch 31'. Therefore, when the second delay signal A02' is a low-level signal, the first logic switch 31' seems to have no power supply, so that the first logic switch 31' outputs a low-level signal. The output waveform is the first pulse signal B01'.

The third delayed signal generating circuit 23' is electrically connected to the second inverter 42' to generate the third delayed signal A03'. The third delayed signal A03' is input to the base of the second logic switch 32', and the first pulse signal B01' is connected to the source of the second logic switch 32'. The drain of the second logic switch 32' first outputs a waveform similar to the first pulse signal B01', until the third delay signal A03' changes from a high potential to a low potential signal, and the drain outputs a high potential signal. In this way, the second pulse signal B02' is generated. The second pulse signal B02' is a waveform with two low potential signals.

In the second embodiment, the basic circuit 11' can still obtain the second pulse signal B02' with a complete waveform without including a buffer. However, in the first embodiment, a buffer needs to be added to obtain a relatively complete waveform. Therefore, in terms of required components, the second embodiment can use two less NMOS components than the first embodiment, which can save more on manufacturing cost.

Next, please refer to FIG. 9 , which is a block diagram of a third embodiment of the pulse signal generating device 10 of the present invention. The pulse signal generating device 10 of the present invention is not limited to only generating the above-mentioned two low-potential pulse signals, and several extension circuits 12 can be added to produce several low-potential pulse signals. In this embodiment, the extension circuit 12 is used as an extension of the basic circuit 11 in the first embodiment, but the utility model is not limited thereto, and the extension circuit 12 can also be used as an extension of the basic circuit 11' in the second embodiment .

Similar to the basic circuit 11, the extension circuit 12 includes a fourth delay signal generating circuit 24, a fifth delay signal generating circuit 25, a third logic switch 33, a fourth logic switch 34, a second buffer 52 and a third buffer 53.

Please refer to FIG. 10 for the detailed circuit connection of the extension circuit 12 . FIG. 10 is a circuit diagram of the extension circuit 12 in the third embodiment of the pulse signal generating device 10 of the present invention. Please also refer to FIG. 11 . FIG. 11 is a waveform diagram generated by the extension circuit 12 in the third embodiment of the pulse signal generating device 10 of the present invention.

The fourth delayed signal generating circuit 24 receives the third delayed signal A03 from the basic circuit 11 and passes through the second buffer 52 to generate the fourth delayed signal A04. The fifth delayed signal generating circuit 25 receives the fourth delayed signal A04 and passes through the third buffer 53 to generate the fifth delayed signal A05. With the above wiring method, it can be ensured that the generated delayed signals will have appropriate time intervals. If wave shaping is not required, the second buffer 52 and the third buffer 53 do not need to be added, so that the cost of some NMOS components can also be saved.

Then the fourth delay signal A04 is transmitted to the source of the third logic switch 33, the base of the third logic switch 33 receives the second pulse signal B02 generated by the basic circuit 11 at the same time, and the drain of the third logic switch 33 will output The third pulse signal B03. The third pulse signal B03 is transmitted to the base of the fourth logic switch 34 , and the source of the fourth logic switch 34 receives the fifth delayed signal A05 to obtain the fourth pulse signal B04 . The working principles of the above-mentioned third logic switch 33 and fourth logic switch 34 are similar to those of the logic switches in the first and second embodiments, so they will not be repeated here. The fourth pulse signal B04 is a signal with three low potential pulses.

The present invention is not limited to adding only one extension circuit 12. The pulse signal generating device 10 can increase the number of extension circuits 12 according to various requirements of the electronic device 60 to generate various pulse signals with different pulse numbers.

To sum up, the utility model is different and superior to the features of the prior art in terms of purpose, means and efficacy. The above-mentioned multiple embodiments of the utility model are only for convenience of description and examples, and the scope of rights of the utility model should be determined by the claims of the utility model, rather than being limited to the above-mentioned embodiments.

Claims (19)

1. A pulse signal generating device for receiving a voltage signal to generate a pulse signal, characterized in that the pulse signal generating device includes: A first delay signal generating circuit, electrically connected to a first inverter, for receiving the voltage signal and generating a first delay signal; A second delay signal generating circuit, electrically connected to a second inverter, for receiving the voltage signal and generating a second delay signal; A third delay signal generating circuit, used to receive the voltage signal and generate a third delay signal; a first logic switch, the first logic switch receives the first delayed signal and the second delayed signal to generate a first pulse signal; and A second logic switch, the second logic switch receives the first pulse signal and the third delay signal to generate a second pulse signal and output the second pulse signal. 2. The pulse signal generating device as claimed in claim 1, wherein the first inverter, the second inverter, the first logic switch and the second logic switch are an N-type metal oxide transistor or a P-type metal oxide transistor. 3. The pulse signal generating device as claimed in claim 1, wherein the first delay signal generating circuit, the second delay signal generating circuit and the third delay signal generating circuit are composed of a resistor and a capacitor. 4. The pulse signal generating device as claimed in claim 1, wherein the third delayed signal generating circuit is further electrically connected to a buffer for rectifying the third delayed signal. 5. The pulse signal generating device as claimed in claim 4, wherein the buffer is at least one NMOS transistor or PMOS transistor. 6. The pulse signal generating device as claimed in claim 1, wherein the delay time of the third delay signal is greater than the delay time of the second delay signal; the delay time of the second delay signal is greater than the delay time of the first delay signal . 7. The pulse signal generating device according to claim 1, further comprising an extension circuit, the extension circuit comprising: A fourth delay signal generating circuit, used to generate a fourth delay signal; A fifth delayed signal generating circuit for generating a fifth delayed signal; a third logic switch, the third logic switch receives the second pulse signal and the fourth delay signal to generate a third pulse signal; and A fourth logic switch, the fourth logic switch receives the third pulse signal and the fifth delay signal to generate a fourth pulse signal and output the fourth pulse signal. 8. A pulse signal generating device for receiving a voltage signal to generate a pulse signal, characterized in that the pulse signal generating device includes: A first delay signal generating circuit, used to receive the voltage signal and generate a first delay signal; A second delay signal generating circuit, electrically connected to a first inverter, for receiving the voltage signal and generating a second delay signal; A third delay signal generating circuit, electrically connected to a second inverter, for receiving the voltage signal and generating a third delay signal; A first logic switch, the first logic switch receives the first delay signal and the first inverted delay signal, and uses the first inverted delay signal as the power signal of the first logic switch to generate a first a pulse signal; and A second logic switch, the second logic switch receives the first pulse signal and the second inverted delay signal to generate a second pulse signal and output the second pulse signal. 9. The pulse signal generating device as claimed in claim 8, wherein the first inverter and the second inverter, the first logic switch and the second logic switch are an N-type metal oxide transistor or a P-type metal oxide transistor. 10. The pulse signal generating device as claimed in claim 8, wherein the first delay signal generating circuit, the second delay signal generating circuit and the third delay signal generating circuit are composed of a resistor and a capacitor. 11. The pulse signal generating device as claimed in claim 8, wherein the delay time of the third delay signal is greater than the delay time of the second delay signal; the delay time of the second delay signal is greater than the delay time of the first delay signal . 12. The pulse signal generating device as claimed in claim 8, further comprising an extension circuit, the extension circuit comprising: A fourth delay signal generating circuit, used to generate a fourth delay signal; A fifth delayed signal generating circuit, used to generate a fifth delayed signal; a third logic switch, the third logic switch receives the second pulse signal and the fourth delay signal to generate a third pulse signal; and A fourth logic switch, the fourth logic switch receives the third pulse signal and the fifth delay signal to generate a fourth pulse signal and output the fourth pulse signal. 13. An electronic device, characterized by comprising: a power supply device for generating a voltage signal; and A pulse signal generating device for receiving the voltage signal and generating a pulse signal, the pulse signal generating device includes: A first delay signal generating circuit, used to receive the voltage signal and generate a first delay signal; A second delay signal generating circuit, electrically connected to a first inverter, for receiving the voltage signal and generating a second delay signal; A third delay signal generating circuit, electrically connected to a second inverter, for receiving the voltage signal and generating a third delay signal; A first logic switch, the first logic switch receives the first delay signal and the first inverted delay signal, and uses the first inverted delay signal as the power signal of the first logic switch to generate a first a pulse signal; and A second logic switch, the second logic switch receives the first pulse signal and the second inverted delay signal to generate a second pulse signal and output the second pulse signal. 14. The electronic device as claimed in claim 13, further comprising a central processing unit or a light emitting diode for receiving the pulse signal. 15. The electronic device as claimed in claim 13, wherein the electronic device is a computer system. 16. The electronic device as claimed in claim 13, wherein the first inverter and the second inverter, the first logic switch and the second logic switch are an N-type metal oxide transistor or a P-type metal oxide transistors. 17. The electronic device as claimed in claim 13, wherein the first delayed signal generating circuit, the second delayed signal generating circuit and the third delayed signal generating circuit are composed of a resistor and a capacitor. 18. The electronic device as claimed in claim 13, wherein the delay time of the third delay signal is greater than the delay time of the second delay signal; the delay time of the second delay signal is greater than the delay time of the first delay signal. 19. The electronic device as claimed in claim 13, wherein the pulse signal generating device further comprises an extension circuit, and the extension circuit comprises: A fourth delay signal generating circuit, used to generate a fourth delay signal; A fifth delayed signal generating circuit for generating a fifth delayed signal; a third logic switch, the third logic switch receives the second pulse signal and the fourth delay signal to generate a third pulse signal; and A fourth logic switch, the fourth logic switch receives the third pulse signal and the fifth delayed signal to generate a fourth pulse signal and output the fourth pulse signal.

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