CN101430926A - Resetting apparatus of memory - Google Patents
Resetting apparatus of memory Download PDFInfo
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- CN101430926A CN101430926A CNA2007101669893A CN200710166989A CN101430926A CN 101430926 A CN101430926 A CN 101430926A CN A2007101669893 A CNA2007101669893 A CN A2007101669893A CN 200710166989 A CN200710166989 A CN 200710166989A CN 101430926 A CN101430926 A CN 101430926A
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Abstract
The invention discloses a memory reset device which comprises a first inverting circuit, a logic circuit and a plurality of second inverting circuits. The first inverting circuit receives a control signal generated by a north bridge chip and generates a first signal, wherein, the control signal is used for controlling reset of a plurality of memories. The logic circuit is used for performing a logic operation on the first signal and an indicator signal and generates a second signal, wherein, the indicator signal is used for indicating that various elements of a computer system complete electrification. A plurality of second inverting circuits are respectively coupled between the logic circuit and the memories. The second inverting circuits are used for inverting the second signal, and respectively generating a plurality of reset signals to the memories so as to reset the memories.
Description
Technical field
The invention relates to a kind of resetting apparatus, and particularly relevant for a kind of resetting apparatus of memory.
Background technology
In general, after computer system starts, and each element all powers on when finishing in the computer system, then needs the action that storer is reseted.Figure 1A and Figure 1B illustrate the circuit diagram into existing a kind of resetting apparatus of memory.Please earlier with reference to Figure 1A, after computer system starts, when each element in the computer system all powered on finish after, can produce the indicator signal S of a logic high voltage level
PGD, and see through the storer that impact damper 102 is sent to each different branches (branch), carry out after finishing to guarantee that storer is reseted to power in computer system.
Afterwards, please refer to Figure 1B, what north bridge chips can produce a logic high voltage level resets signal S
RESET, see through transistor T 1 and produce the anti-phase signal S that resets
RESET_N(logic low voltage level) is to the storer of different branches.As the received indicator signal S of the storer of each branch
PGDBe logic " height " voltage level and the anti-phase signal S that resets
RESET_NDuring logic " low " voltage level, then carry out the action that storer is reseted.And if indicator signal S
PGDAnd the anti-phase signal S that resets
RESET_NWhen all being logic low voltage level, then do not reset action.
Though above-mentioned resetting apparatus of memory can open in the process in computer system, finishes storer and resets.But the more circuit component that the existing memory resetting apparatus but uses thus, will make and make printed circuit board (PCB) (circuit when printed circuit board, PCB) layout is more crowded, and also can increase the cost of circuit.
Summary of the invention
The invention provides a kind of resetting apparatus of memory, can reduce the employed element of circuit design effectively by this, to save arrangement space and to reduce circuit cost.
The present invention proposes a kind of resetting apparatus of memory, and it comprises first negative circuit, logical circuit and a plurality of second negative circuit.The input end of first negative circuit receives the control signal that north bridge chips produced, and in order to control signal is anti-phase, and produces first signal in its output terminal, and wherein control signal is in order to control reseting of a plurality of storeies.Logical circuit has first input end, second input end and output terminal.The first input end of this logical circuit and second input end receive first signal and indicator signal respectively, in order to first signal and indicator signal are carried out logical operation, and in the output terminal generation secondary signal of logical circuit, wherein above-mentioned indicator signal powers in order to each element of indicating computer system and finishes.
Hold above-mentionedly, a plurality of second negative circuits are respectively coupled between logical circuit and the above-mentioned a plurality of storer.The input end of above-mentioned second negative circuit receives secondary signal, in order to secondary signal is anti-phase, and produces a plurality of above-mentioned storeies that reset signal to respectively in its output terminal, so that above-mentioned storer is reseted.
In an embodiment of the present invention, above-mentioned logical circuit comprises Sheffer stroke gate.This Sheffer stroke gate has first input end, second input end and output terminal.Wherein, the first input end of Sheffer stroke gate receives first signal, and second input end of Sheffer stroke gate receives control signal, and the output terminal of Sheffer stroke gate produces secondary signal.
In an embodiment of the present invention, above-mentioned first negative circuit comprises first resistance, second resistance, the first transistor, the 3rd resistance and electric capacity.First end of first resistance is coupled to first voltage, and its second end is coupled to indicator signal.First end of second resistance is coupled to second end of first resistance.The base terminal of the first transistor is coupled to second end of second resistance, and its emitter terminal is held with being coupled to.First end of the 3rd resistance is coupled to first voltage, and its second end is coupled to the collector terminal of the first transistor.First end of electric capacity is coupled to first end of the 3rd resistance, and its second end is held with being coupled to.Wherein, above-mentioned the first transistor is the NPN bipolar transistor.
In an embodiment of the present invention, above-mentioned second negative circuit comprises the 4th resistance and transistor seconds.First end of the 4th resistance is coupled to the output terminal of Sheffer stroke gate.The base terminal of transistor seconds is coupled to second end of the 4th resistance, and its emitter terminal is held with being coupled to, and signal is reseted in its collector terminal generation.Wherein, above-mentioned transistor seconds is the NPN bipolar transistor.
The present invention can by first negative circuit, logical circuit and second negative circuit, reach the function that storer is reseted after computer system starts.Therefore, the present invention can finish the action that storer is reseted using under the less elements, and then reaches and save arrangement space and reduce circuit cost.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A and Figure 1B illustrate the circuit diagram into existing a kind of resetting apparatus of memory.
Fig. 2 illustrates the circuit diagram into the resetting apparatus of memory of one embodiment of the invention.
Embodiment
Fig. 2 illustrates the circuit diagram into the resetting apparatus of memory of one embodiment of the invention.Please refer to Fig. 2, resetting apparatus of memory 200 comprises first negative circuit 210, logical circuit 230 and second negative circuit 250_1～250_n, and wherein n is the positive integer greater than 0.
The input end of first negative circuit 210 receives the control signal Sc that is produced by north bridge chips (not illustrating), and with control signal Sc carry out anti-phase after, and produce the first signal S1 in its output terminal.Wherein, control signal Sc can be the signal of reseting of a plurality of storeies of control (not illustrating).
Second negative circuit 250_1～250_n is respectively coupled between logical circuit 230 and the above-mentioned storer.Wherein, the input end of second negative circuit 250_1～250_n receives secondary signal S2 separately, afterwards secondary signal S2 is carried out anti-phase after, and produce a plurality of signal Srst that reset respectively to storer, so that storer is reseted in the output terminal of second negative circuit 250_1～250_n.In the present embodiment, the number of second negative circuit is the number corresponding to storer, and therefore, visual its demand of user is adjusted the number of second negative circuit voluntarily.
Please continue with reference to Fig. 2, first negative circuit 210 comprises resistance R 1～R3, transistor Tr 1 and capacitor C 1.First end of resistance R 1 is coupled to the first voltage V1, and its second termination is received indicator signal Si.First end of resistance R 2 is coupled to second end of resistance R 1.The base terminal of transistor Tr 1 is coupled to second end of resistance R 2, and its emitter terminal is held GND with being coupled to.First end of resistance R 3 is coupled to the first voltage V1, and its second end is coupled to the collector terminal of transistor Tr 1.First end of capacitor C 1 is coupled to first end of resistance R 3, and its second end is held GND with being coupled to.
In the above-mentioned resetting apparatus of memory 200 that present embodiment has been described each element with and configuration relation.Next, the operating process of resetting apparatus of memory 200 will be further specified.
At first, behind computer system boot-strap, and each element has powered on all and has finished in the computer system, and computer system can be sent the indicator signal Si of logic high voltage level, and is sent to Sheffer stroke gate 231.On the other hand, because computer system just starts, so control signal Sc is logic low voltage level, then transistor Tr 1 not conducting, and the voltage level that makes the signal S1 that wins is the first voltage V1 (also being logic high voltage level), and is sent to Sheffer stroke gate 231.
At this moment, the first signal S1 and indicator signal Si that Sheffer stroke gate 231 is received are high-voltage level, and the secondary signal S2 that makes Sheffer stroke gate 231 be produced is a logic lowland voltage level, and are sent to transistor Tr 2 through resistance R 4.Because secondary signal S2 is logic low voltage level, then transistor Tr 2 not conductings, and the action that can't reset storer.
Afterwards, north bridge chips also power on finish after, control signal Sc is converted to logic high voltage level (action that expression must be reseted storer), make transistor Tr 1 conducting.Because transistor Tr 1 conducting, then the first voltage V1 sees through resistance R 3 and holds GND with being coupled to, and making the signal S1 that wins is logic low voltage level.
Then, the first signal S1 received when the first input end of Sheffer stroke gate 231 is logic low voltage level, and the received indicator signal of second input end of Sheffer stroke gate 231 is Si is logic high voltage level, therefore the secondary signal S2 that output terminal produced of Sheffer stroke gate 231 can be converted to logic high voltage level, and see through resistance R 4 and be sent to transistor Tr 2, make transistor Tr 2 conductings.Because transistor Tr 2 conductings make that reseting signal Srst is logic low voltage level, with the action that storer is reseted.Thus, storer reset too can be in computer system each element power on and carry out after finishing.Compared to existing resetting apparatus of memory, the resetting apparatus of memory 200 used circuit components of present embodiment are less, and therefore, present embodiment can be saved arrangement space, also can reduce circuit cost.
In sum, the present invention after computer system starts, reaches the function that storer is reseted by first negative circuit, logical circuit and second negative circuit.Therefore, the present invention can finish the action that storer is reseted using under the less elements, and then reaches and save arrangement space and reduce circuit cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (6)
1. resetting apparatus of memory comprises:
One first negative circuit, its input end receives the control signal that a north bridge chips is produced, and in order to this control signal is anti-phase, and produces one first signal in its output terminal, and wherein this control signal is in order to control reseting of a plurality of storeies;
One logical circuit, have first input end, second input end and output terminal, the first input end of this logical circuit and second input end receive this first signal and an indicator signal respectively, in order to this first signal and this indicator signal are carried out logical operation, and produce a secondary signal in the output terminal of this logical circuit, wherein this indicator signal powers in order to each element of indicating a computer system and finishes; And
A plurality of second negative circuits, be respectively coupled between this logical circuit and those storeies, the input end of those second negative circuits receives this secondary signal, in order to this secondary signal is anti-phase, and produce a plurality of those storeies that reset signal to respectively in the output terminal of those second negative circuits, so that those storeies are reseted.
2. resetting apparatus of memory as claimed in claim 1 is characterized in that, this first negative circuit comprises:
One first resistance, its first end is coupled to one first voltage, and its second termination is received this indicator signal;
One second resistance, its first end is coupled to second end of this first resistance;
One the first transistor, its base terminal are coupled to second end of this second resistance, and its emitter terminal is held with being coupled to;
One the 3rd resistance, its first end is coupled to this first voltage, and its second end is coupled to the collector terminal of this first transistor;
One electric capacity, its first end is coupled to first end of the 3rd resistance, and its second end is held with being coupled to.
3. resetting apparatus of memory as claimed in claim 2 is characterized in that, this first transistor is the NPN bipolar transistor.
4. resetting apparatus of memory as claimed in claim 1 is characterized in that, this logical circuit comprises:
One Sheffer stroke gate has first input end, second input end and output terminal, and the first input end of this Sheffer stroke gate receives this first signal, and second input end of this Sheffer stroke gate receives this control signal, and the output terminal of this Sheffer stroke gate produces this secondary signal.
5. resetting apparatus of memory as claimed in claim 1 is characterized in that, those second negative circuits comprise:
One the 4th resistance, its first end is coupled to the output terminal of this Sheffer stroke gate; And
One transistor seconds, its base terminal are coupled to second end of the 4th resistance, and its emitter terminal is held with being coupled to, and its collector terminal produces this and resets signal.
6. resetting apparatus of memory as claimed in claim 5 is characterized in that, this transistor seconds is the NPN bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101669893A CN101430926B (en) | 2007-11-08 | 2007-11-08 | Resetting apparatus of memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101669893A CN101430926B (en) | 2007-11-08 | 2007-11-08 | Resetting apparatus of memory |
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| Publication Number | Publication Date |
|---|---|
| CN101430926A true CN101430926A (en) | 2009-05-13 |
| CN101430926B CN101430926B (en) | 2010-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101669893A Expired - Fee Related CN101430926B (en) | 2007-11-08 | 2007-11-08 | Resetting apparatus of memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916232A (en) * | 2009-08-26 | 2010-12-15 | 威盛电子股份有限公司 | Memory configuration apparatus and method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI464746B (en) * | 2012-03-30 | 2014-12-11 | Wistron Corp | A clearing circuit for memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU1524395A (en) * | 1994-01-05 | 1995-08-01 | Norand Corporation | Safe-stop mode for a microprocessor operating in a pseudo-static random access memory environment |
| TW467373U (en) * | 1998-04-01 | 2001-12-01 | Asustek Comp Inc | Input/output testing device of computer system |
| US6292859B1 (en) * | 1998-10-27 | 2001-09-18 | Compaq Computer Corporation | Automatic selection of an upgrade controller in an expansion slot of a computer system motherboard having an existing on-board controller |
| CN1187687C (en) * | 2001-12-18 | 2005-02-02 | 矽统科技股份有限公司 | Method and device for reducing computer initial setting element |
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2007
- 2007-11-08 CN CN2007101669893A patent/CN101430926B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101916232A (en) * | 2009-08-26 | 2010-12-15 | 威盛电子股份有限公司 | Memory configuration apparatus and method |
| CN101916232B (en) * | 2009-08-26 | 2012-09-05 | 威盛电子股份有限公司 | Memory configuration apparatus and method |
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| Publication number | Publication date |
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| CN101430926B (en) | 2010-09-22 |
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Inventor after: Li Dong Inventor before: Huang Lan Inventor before: Liu Shihao |
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Effective date of registration: 20170920 Address after: No. 23, building 26, 3 Lao Lin Road, Yindu District, Henan, Anyang Patentee after: Li Dong Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. 66 Patentee before: Inventec Corporation |
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Address after: 541002 Diecai District, Guilin City, the Guangxi Zhuang Autonomous Region, No. 147 Zhongshan North Road Patentee after: Li Dong Address before: No. 3, courtyard No. 23, No. 26, Lao an Lin Road, Yindu District, Anyang, Henan Patentee before: Li Dong |
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