CN111175641B - Electrostatic discharge immunity testing method and assembly for processor chip - Google Patents
Electrostatic discharge immunity testing method and assembly for processor chip Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 86
- 230000036039 immunity Effects 0.000 title claims abstract description 33
- 239000000523 sample Substances 0.000 claims abstract description 103
- 239000003990 capacitor Substances 0.000 claims abstract description 36
- 230000008878 coupling Effects 0.000 claims abstract description 20
- 238000010168 coupling process Methods 0.000 claims abstract description 20
- 238000005859 coupling reaction Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 230000003068 static effect Effects 0.000 claims description 4
- 238000010998 test method Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 abstract description 2
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- 238000005457 optimization Methods 0.000 description 2
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
- G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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Abstract
The invention relates to the technical field of integrated circuit detection, and discloses an electrostatic discharge immunity testing component and method for a processor chip, so as to improve the testing fineness and convenience. The inventive assembly comprises: the probe without capacitor and the probe with capacitor are respectively used for testing the noise immunity of different pins of the IC chip; and one end of the probe connector is used for connecting the output end of the electrostatic discharge generator, and the other end of the probe connector is used for detachably connecting the capacitance-free probe or the capacitance-containing probe. The capacitance carried by the probe with the capacitance is a coupling capacitance which can be connected in series between the probe connector and a single-ended signal pin of the high-speed DDR chip to be detected. The non-capacitance probe is used for connecting the probe connector with a pin of a differential signal of the high-speed DDR chip; and the assembly further comprises: the differential pins are provided with the coupling capacitors which are connected in parallel, so that the customized PCB test board for the differential signal double-ended pins of the tested high-speed DDR chip can be butted.
Description
Technical Field
The invention relates to the technical field of integrated circuit detection, in particular to an electrostatic discharge immunity testing assembly and method for a processor chip.
Background
ESD (electrostatic discharge) is a discipline developed in the middle of the 20 th century to study generation and damage of static electricity, electrostatic protection, and the like, and devices for electrostatic protection are commonly referred to as ESD in the world.
ESD testing, i.e., electrostatic discharge testing, is used to verify the immunity of electronic and electrical equipment to electrostatic discharge, both directly from the operator and to nearby objects. Because static electricity is usually very high in transient voltage (more than several kilovolts), it is the main source of excess Electrical Stress (EOS) caused by electronic components or integrated circuits; as one of the damage causes in the electronic industry, the production yield, the manufacturing cost, and the product quality are affected. As the manufacturing process of integrated circuit products is continuously developed, the anti-electrostatic damage capability of the integrated circuit needs to be measured more accurately.
Currently, only the system level electrostatic discharge standard ISO10605, IEC61000-4-2, and test control devices issued according to the system level standard, such as: patent publication No.: CN 106526366A. The description about ESD in the standard Generic IC EMC Test Specification is system-level ESD.
At present, the standard application range of the integrated circuit is mostly electronic components, and no static discharge test standard specific to an IC to a pin is provided, and a complete high-speed signal injection standard of the integrated circuit is not established. The invention relates to an electrostatic discharge immunity testing method for a processor chip, which is designed by referring to an electrostatic discharge waveform and a standard arrangement in IEC61000-4-2 aiming at the field of integrated circuits.
Disclosure of Invention
The invention aims to disclose an electrostatic discharge immunity testing component and an electrostatic discharge immunity testing method for a processor chip, so as to improve the testing fineness and convenience.
To achieve the above object, the present invention discloses an esd immunity test assembly for a processor chip, comprising:
the probe without capacitor and the probe with capacitor are respectively used for testing the noise immunity of different pins of the IC chip;
and one end of the probe connector is used for connecting the output end of the electrostatic discharge generator, and the other end of the probe connector is used for detachably connecting the capacitance-free probe or the capacitance-containing probe.
Preferably, the capacitance carried by the capacitive probe is a coupling capacitance which can be connected in series between the probe connector and a single-ended signal pin of the high-speed DDR chip to be tested.
Preferably, the capless probe is used for connecting the probe connector with a pin of a differential signal of a high-speed DDR chip; and the assembly further comprises: the differential pins are provided with the coupling capacitors which are connected in parallel, so that the customized PCB test board for the differential signal double-ended pins of the tested high-speed DDR chip can be butted.
In order to achieve the above object, the present invention further discloses a method for testing electrostatic discharge immunity of a processor chip, comprising:
dividing pins of an IC chip to be tested into two types; one is based on the non-capacitance probe to carry out the immunity test, and the other is based on the capacitance probe to carry out the immunity test;
and determining the type of the tested pin, and selecting a corresponding non-capacitance probe or capacitance probe to be connected with an electrostatic discharge generator through a probe connector for testing.
Preferably, when measuring the single-ended signal of the high-speed DDR chip, the capacitive probe is selected for testing, and the capacitor carried by the capacitive probe is a coupling capacitor which can be connected in series between the probe connector and the single-ended signal pin of the high-speed DDR chip to be measured; when measuring the differential signal of the high-speed DDR chip, selecting a customized PCB test board which is provided with parallel coupling capacitors aiming at the differential pins and is butted with the differential signal double-end pins of the measured high-speed DDR chip, and then selecting a non-capacitor probe for testing.
The invention has the following beneficial effects:
electrostatic discharge interference testing is carried out from a system level to a pin level. Moreover, one probe connector is compatible and can be switched between a non-capacitance probe and a capacitance probe, so that a user can conveniently and flexibly select different pin types and characteristics, the convenience of operation and the testing efficiency are greatly improved, and the method is particularly suitable for measuring high-speed DDR chips and other application scenes.
The present invention will be described in further detail below with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a circuit diagram of an ESD immunity probe connector according to an embodiment of the present invention.
Fig. 2 is a diagram of a testing configuration of ESD immunity according to an embodiment of the present invention.
Detailed Description
The embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways as defined and covered by the claims.
Example one
The embodiment discloses an electrostatic discharge immunity test component facing a processor chip, which comprises: the probe without capacitor and the probe with capacitor are respectively used for testing the noise immunity of different pins of the IC chip; and the probe connector is used for connecting the output end of the electrostatic discharge generator at one end and detachably connecting the capacitance-free probe or the capacitance-containing probe at one end.
In this embodiment, the capacitor carried by the probe with the capacitor is a coupling capacitor that can be connected in series between the probe connector and the single-ended signal pin of the high-speed DDR chip to be tested.
In this embodiment, the circuit structure of the probe connector may adopt the circuit shown in fig. 1, which is equivalent to splitting the conventional system-level-oriented non-detachable probe head into a probe connector and a capless probe.
In a conventional IC ESD test, an ESD probe is directly contacted with a pin of an IC to be tested to perform the test.
With the development of ICs at high speed and high frequency, the complexity is increasing. When performing the electrostatic discharge test, it is first necessary to design a minimum hardware system of PC board for making the chip work normally, which is a core system composed of a storage circuit composed of a microprocessor, a Synchronous Dynamic Random Access Memory (SDRAM), and a FLASH Memory, and some necessary auxiliary circuits, and its composition affects the low-level design of software and is the basis for the normal operation of the IC embedded operating system. The memory module and the inherent SRAM are used for controlling the system start, and the memory space is not large, so that a FLASH chip for storing the system and the program and an SDRAM chip for running the program are required to be arranged on the periphery. The main stream of the SDRAM is DDR2, DDR3 and DDR4, and the larger the number following DDR (Double Data Rate), the higher the maximum operating frequency supported, in this example, the DDR3 chip is selected.
The great problem that this brought is, because the internal clock frequency is higher, when adopting traditional probe to inject into test clock and DDR signal pin etc. EUT can't work, because, add ESD probe in pin department, the equivalent load of probe is 330 ohms, and EUT's resistance is less, introduces the equivalent load for the load of chip changes, leads to EUT can't work.
The scheme of the embodiment is to improve the probe on the premise of ensuring that the electrostatic discharge pulse meets the standard, so that the probe does not influence the EUT work after being applied. For this purpose, a probe with capacitance is added which is fitted to the probe connector, the coupling capacitance of the probe with capacitance being connected in series between the probe connector and the EUT. For example: for single-ended injection, the solution is: when the equivalent load of the probe connector is 330 ohms, a coupling capacitor of 2.2pF is added between the DDR pin and the ESD probe, and the phenomenon that the introduced equivalent load causes that the EUT cannot work normally is avoided. In comparison, if a coupling capacitor is added to the PCB test board where the chip is located, each pin needs to be added, which seriously increases the complexity of the PCB and causes a disordered layout.
Considering that the pin signals of the high-speed DDR pin are divided into a single-ended (including single-ended injection of pin for outputting signals, inputting signals, and inputting and outputting signals) and a differential end, in this embodiment, two injection methods are respectively adopted for the two pins. For the differential signal pin, because the two ends respectively need 2.2pF coupling capacitors, if a probe with a parallel capacitor is designed, the utilization rate is low, and the realization is difficult, so that the probe with the parallel capacitor is not invented. As an improvement, in this embodiment, when the high frequency high speed signal is injected into the differential pin, a coupling capacitor is designed in parallel at the DDR pin end of the PCB test board. Namely: when the differential signal of the high-speed DDR chip is measured, a customized PCB test board which is provided with parallel coupling capacitors aiming at differential pins and is butted with the double-end pins of the differential signal of the measured high-speed DDR chip is selected, and then a capacitor-free probe is selected for testing.
Furthermore, during ESD testing, the applicant found that for DDR signal pins with timing, the number and time interval of pulse injections have a large impact on the test results at a single voltage level. Even with the same test setup, the test results are still random, making the test results less reliable. Preferably, the electrostatic discharge generator of the embodiment adopts an electrostatic discharge generator with pulse voltage and frequency capable of being set, so as to set the pulse number and the time interval according to the requirements of IEC61000-4-2 and ensure the consistency of the test. Optionally, a contact discharge pulse is applied to each selected pin during the test, three injection tests are performed at each voltage level, and if the test level reaches the upper limit and is not damaged, the test enters another selected pin. In practical application, the voltage that the chip can bear in the industry is usually within 4KV, and under the equipment operating condition that awaits measuring, the reasonable regulation test is step-by-step, on the basis of the test accuracy, improves efficiency of software testing.
Because the processor chip can work in a lower voltage environment, the pulse voltage range of a common electrostatic discharge generator is +/-100V to +/-9.5 KV, and in order to realize lower voltage injection, an attenuator needs to be added between the signal generator and the probe so as to achieve the purpose that the test voltage is lower than 100V. For example: to achieve a starting voltage of 10V in this example, 20dB of attenuation is added. The pulse waveform of the generator probe is 0.7/60ns, so the added attenuation cut-off frequency is required to be 3 GHz. In the test set up of this example, the applied contact discharge pulse voltage was from 10V to 8kV, from low to high injection, at a frequency of 1Hz, with positive and negative polarity.
Therefore, the ESD immunity test configuration corresponding to the present embodiment can refer to fig. 2, in which 100 is a computer with corresponding control software installed, 200 is a signal generator BPS203, 300 is an ESD probe P331-2, 400 is a test environment with EUT, 500 is an oscilloscope, and 600 is a dc power supply.
Preferably, the non-capacitive probe of the embodiment can be also used for connecting the probe connector with pins of an IC chip except for a high-speed DDR chip. In a particular application, a user may flexibly select a capacitive probe and a capacitive probe based on a particular pin of a particular chip. The pins under test may be selected by observing the layout of the IC to locate the IC die and corresponding package pins. The reference method can be as follows:
1. all power domain pins. As most disturbances will cause fluctuations, the power domain network including power and ground is affected, and thus the IC.
2. One for each type of GPIO pin. By using a global file, note the type of I/O pads, the number and location of the corresponding pins. GPIO pins are selected according to the location in each unique layout.
3. The special function pins comprise a reset pin, an external crystal oscillator pin and the like.
4. According to the system-level EMC immunity problem in practical application, the IC module with the problem is found to select the test pin.
Overall, in other words: the specific operation in this example is to select at least one pin of each type as a test pin, or to select a pin that is susceptible to interference. And after all the pins to be tested are selected, classifying the pins according to the applicable probes, and respectively testing.
Example two
Corresponding to the above component embodiments, the present embodiment discloses an esd immunity testing method for a processor chip, including:
step S1, dividing the pins of the tested IC chip into two types; one is based on the non-capacitance probe to carry out the immunity test, and the other is based on the capacitance probe to carry out the immunity test.
And step S2, determining the type of the tested pin, and selecting a corresponding non-capacitance probe or capacitance probe to connect with the electrostatic discharge generator through the probe connector for testing.
Preferably, the method of this embodiment further includes:
and step S3, when measuring the single-ended signal of the high-speed DDR chip, selecting the probe with the capacitor to test, wherein the capacitor carried by the probe with the capacitor is a coupling capacitor which can be connected in series between the probe connector and the single-ended signal pin of the high-speed DDR chip to be measured.
And step S4, when measuring the differential signal of the high-speed DDR chip, selecting a customized PCB test board which is provided with parallel coupling capacitors aiming at the differential pins and is butted with the differential signal double-end pins of the high-speed DDR chip to be measured, and then selecting a probe without a capacitor for testing.
Further, the method of this embodiment further includes: on one hand, when the tested pin of the chip is switched and the environmental state corresponding to different noise immunity of the same tested pin is switched, the pulse voltage and the frequency parameter of the electrostatic discharge generator are correspondingly adjusted. On the other hand, when the tested pin of the chip is switched and the environmental state corresponding to different noise immunity of the same tested pin is switched, the corresponding parameters of the attenuator between the electrostatic discharge generator and the probe connector are adjusted according to the characteristics of the tested pin.
In summary, the electrostatic discharge immunity testing assembly and method for processor chips disclosed in the above embodiments of the invention at least have the following advantages:
electrostatic discharge interference testing is carried out from a system level to a pin level. Moreover, one probe connector is compatible and can be switched between a non-capacitance probe and a capacitance probe, so that a user can conveniently and flexibly select different pin types and characteristics, the convenience of operation and the testing efficiency are greatly improved, and the method is particularly suitable for measuring high-speed DDR chips and other application scenes.
In addition, the embodiments of the invention can be used for guiding the chip design and the IC test of the set top box of the terminal video equipment to form the corresponding test capability. It also has very strong guiding meaning to other types of chips, such as SoC and switch Phy chips of mobile phones. The test results of the IC further guide the optimization of the IC design and the location of EMC problems and the optimization of system level products.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (3)
1. An electrostatic discharge immunity test assembly for a processor chip, comprising:
the probe without capacitor and the probe with capacitor are respectively used for testing the noise immunity of different pins of the IC chip;
the probe connector is used for connecting the output end of the electrostatic discharge generator at one end and detachably connecting the capacitance-free probe or the capacitance-containing probe at the other end;
the capacitance carried by the probe with the capacitance is a coupling capacitance which can be connected in series between the probe connector and a single-ended signal pin of the high-speed DDR chip to be detected; the coupling capacitor of the capacitive probe is connected in series between the probe connector and the EUT;
the non-capacitance probe is used for connecting the probe connector with a pin of a differential signal of the high-speed DDR chip; and the assembly further comprises:
the differential pins are provided with coupling capacitors which are connected in parallel so as to butt against the customized PCB test board of the differential signal double-end pins of the high-speed DDR chip to be tested;
the non-capacitance probe is also used for connecting the probe connector with pins of an IC chip except the high-speed DDR chip;
the electrostatic discharge generator adopts an electrostatic discharge generator with settable pulse voltage and frequency; the electrostatic discharge generator sets the pulse number and the time interval of the output electrostatic discharge pulse according to the electrostatic discharge waveform and the standard arrangement requirement and ensures the consistency of the test;
in the testing process, a contact discharge pulse is required to be applied to each selected pin, three injection tests are carried out at each voltage level, and if the testing level reaches the upper limit and is not damaged, the test enters another selected pin.
2. The assembly of claim 1, further comprising an attenuator between the electrostatic discharge generator and the probe connector.
3. A static discharge immunity test method facing a processor chip is characterized by comprising the following steps:
dividing pins of an IC chip to be tested into two types; one is based on the non-capacitance probe to carry out the immunity test, and the other is based on the capacitance probe to carry out the immunity test;
determining the type of the pin to be tested, and selecting a corresponding probe without capacitance or with capacitance to be connected with an electrostatic discharge generator through a probe connector for testing;
when the single-ended signal of the high-speed DDR chip is measured, the capacitive probe is selected for testing, and a capacitor carried by the capacitive probe is a coupling capacitor which can be connected in series between the probe connector and the single-ended signal pin of the high-speed DDR chip to be measured;
when measuring the differential signal of the high-speed DDR chip, selecting a customized PCB test board which is provided with parallel coupling capacitors aiming at differential pins and is butted with the differential signal double-end pins of the measured high-speed DDR chip, and then selecting a non-capacitor probe for testing;
when switching a tested pin of a chip and switching an environment state corresponding to different noise immunity of the same tested pin, correspondingly adjusting pulse voltage and frequency parameters of the electrostatic discharge generator;
and when switching the tested pins of the chip and the environment states corresponding to different noise immunity of the same tested pin, adjusting corresponding parameters of an attenuator between the electrostatic discharge generator and the probe connector according to the characteristics of the tested pin.
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| CN115420979A (en) * | 2022-08-31 | 2022-12-02 | 中国科学院国家空间科学中心 | Precise injection system and test method for electrostatic discharge pulse in integrated circuit space |
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| CN201540360U (en) * | 2008-10-31 | 2010-08-04 | 崧顺电子（深圳）有限公司 | Electromagnetic compatibility inspection device of switch regulated power supply |
| CN111034389B (en) * | 2009-01-13 | 2013-09-04 | 中国人民解放军陆军工程大学 | Electrostatic discharge immunity test method |
| CN202033429U (en) * | 2010-12-24 | 2011-11-09 | 北京东方计量测试研究所 | Anti-static shielding bag testing device |
| CN104965141A (en) * | 2015-07-03 | 2015-10-07 | 江苏益邦电力科技有限公司 | Floating electronic equipment electric rapid transient pulse group protection method |
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