CN1996445A - Test method for liquid crystal display panel - Google Patents
Test method for liquid crystal display panel Download PDFInfo
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- CN1996445A CN1996445A CN 200710001273 CN200710001273A CN1996445A CN 1996445 A CN1996445 A CN 1996445A CN 200710001273 CN200710001273 CN 200710001273 CN 200710001273 A CN200710001273 A CN 200710001273A CN 1996445 A CN1996445 A CN 1996445A
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Abstract
A way for testing LCD panel combines the LCD panel to grid through grid drive circuit, at least inputting positive and negative phase time sequence and lower pull signal to selected zone grid driver positive sequence input end, negative time sequence input end and lower pull signal input end. Inputting start signal at the same time to grid driver start signal input end to start selected area grid, and starting the selected thin film transistor at the same time. Send a testing signal by all data cables. It can also be used for local testing. It divides the panel into several zones with different testing areas.
Description
Technical field
The present invention relates to the method for testing of panel of LCD, wherein gate driver circuit is integrated on the panel of LCD.
Background technology
Along with electronic goods market is day by day flourishing, also increasing for the demand of panel of LCD.This demand be because many electronic products adopt LCD (Liquid Crystal Display, LCD), TV screen for example, computer screen, and mobile phone screen.Relatively, the test of panel of LCD also becomes the committed step of volume production panel of LCD.The method of testing of panel of LCD comprises comprehensive engagement method of testing (Full Contact) and short-circuit rods method of testing (Shorting Bar) at present.The advantage of comprehensive engagement method of testing is its good test function, but can consume many chip testing times.The short-circuit rods method of testing can shorten the test duration, because this method of testing is divided into two groups of odd number bar and even number bars with all grid lines (gate line), and every group of all clock signal input end linked together, all start signal input ends link together, and all pulldown signal input ends link together.Therefore not being required to be each bar grid line imports independently signal, and can be in signal of tie point input of above-mentioned signal.Test can begin by opening all odd number grid lines earlier.After finishing the odd number grid line it is closed, and open all even number grid lines and test.The panel test zone will be decided by a modulator, and modulator also can provide pixel voltage in all zones simultaneously.
The short-circuit rods method of testing is applicable to the panel of LCD with gate drivers.But (Gate On Array, in the time of GOA), the short-circuit rods method of testing promptly can't use with existing mode on the panel of LCD when gate drivers is integrated in.Reason is in the short-circuit rods method of testing, and the signal that is used to start grid line is directly by the input end input of grid line, need not pass through gate drivers.When gate drivers and grid line electric connection, the short-circuit rods method of testing promptly can't directly overlap the input end that is used for grid line.
The method that is used to test GOA technology panel at present is by the input end input drive signal that is integrated in first gate drivers on the panel.When first gate drivers is driven, promptly open article one grid line.Drive signal can reach second gate drivers by first gate drivers, and closes the first grid driver, and opens the second grid line, by that analogy.
Please refer to Fig. 1, it illustrates present GOA panel test pattern diagram.If down test from the grid line of the top in regular turn, when a defect point 102 occurring on finding a certain grid line 101, test promptly stops, and defect point 102 all the other later grid lines 103 all can't be tested again.Carry out the test second time when awaiting repairing found defect point again.As finding another defect point (not being shown among the figure) once more, test promptly stops, and defect point 102 all the other later grid lines 103 all need not to test again, and abandon this panel.Therefore, the tester can't know after the defect point 102 whether also have defective, if the grid line zero defect after the defect point 102, the waste of abandoning a kind of material of formation of panel also reduces output.
Therefore, need a kind of method that can test many grid lines on the GOA panel simultaneously at present.When many grid lines can be measured simultaneously, can reduce or solve grid line because of sequencing problem can't be tested possibility.
Summary of the invention
Therefore, purpose of the present invention is exactly that a kind of method of testing of panel of LCD is being provided, in order to when gate driver circuit being integrated in panel of LCD on it the time, can test simultaneously thin film transistor (TFT) on many grid lines (Thin Film Transistor, TFT).One embodiment of the invention is connected to a positive timing sequence test pad, an anti-phase timing sequence test pad and a drop-down signal testing pad with positive clock signal input end (CK), anti-phase clock signal input end (XCK) and the pulldown signal end (Pull Down) of the gate drivers in selected zone.Positive clock signal, anti-phase clock signal and pulldown signal can be inputed to the positive clock signal input end of the gate driving in selected zone, anti-phase clock signal input end and pulldown signal end simultaneously respectively thus.In the same manner, with start signal (Start Pulse) input end of the gate drivers in the selected zone beginning signal testing pad that is connected together, and start signal is inputed to simultaneously the start signal input end of the gate drivers in selected zone.Above-mentioned selection area can comprise the full wafer panel.After above-mentioned signal is imported simultaneously, promptly open all thin film transistor (TFT)s on the selected regional grid line.When test signal was imported by all data lines (data line) simultaneously, all thin film transistor (TFT)s on the selected regional grid line can be tested simultaneously.
Another embodiment disclosed in this invention tests panel of LCD in the mode of subregion.Present embodiment is divided into a plurality of zones with panel, and wherein each zone comprises a grid line at least.The start signal end of the gate drivers in each zone is connected together on the beginning signal testing pad, the positive clock signal input end of the gate drivers in each zone is connected on the positive timing sequence test pad, the anti-phase clock signal input end of the gate drivers in each zone is connected on the anti-phase timing sequence test pad, and the pulldown signal input end of the gate drivers in each zone is connected on the drop-down signal testing pad.Therefore, above-mentioned signal can input to the gate drivers of zones of different simultaneously respectively, and zones of different is tested.
All signal connecting lines that do not need to isolate each zone before testing maybe can avoid each regional signal to enter in other regional gate drivers all signal connecting lines in each zone electrical isolation each other.If all signal connecting lines in each zone each other during electrical isolation, after test finishes, are promptly needed the signal connecting line of All Ranges is electrically connected mutually again, make the overall operation again of full wafer panel.
Three kinds of isolation are provided in the present invention and reconnect each regional structure or method as example, other is any to apply to isolate and reconnects each regional structure or method all can apply to this.With the start signal is example (other is all identical as positive clock signal, anti-phase clock signal and drop-down signal), first kind is the start signal connecting line formation welding bridge joint place between the zone, be electrically connected at respectively between the two start signal connecting lines, and the mode with welding reconnects all start signal connecting lines after test.Second kind is to form metal-oxide semiconductor (MOS) bridge joint place between the start signal connecting line between the zone, be electrically connected at respectively between the two start signal connecting lines, and the mode with voltage breakdown reconnects all start signal connecting lines after test.The third is not need electrical isolation can reach the purpose of panel subregion, and the method is with the grid line in the non-test of drop-down signal at stop, so that start signal can't be opened the gate drivers in the non-test.Though the isolation that is provided with reconnect each regional structure or method openly as above, yet it is not in order to limit the present invention.All testing weld pad among the present invention comprises positive timing sequence test pad, anti-phase timing sequence test pad, pulldown signal testing weld pad and start signal testing weld pad, all is formed on the nonclient area of substrate, and is cut after test is finished.
Disclosed embodiment of this invention provides a kind of method of testing of panel of LCD, and the method can be tested the grid line of most panel of LCD simultaneously.So can avoid the defective blind spot that possibly can't be tested because test in regular turn.And this method of testing can promote the defects detection rate, promptly the panel of only finding two defectives need not abandoned, and is also repaired but can detect all defect simultaneously.In addition, test speed can be faster than the method for testing in regular turn of prior art because of test simultaneously.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of accompanying drawing:
Fig. 1 is present GOA panel test pattern diagram;
Fig. 2 is the panel of LCD selection area synoptic diagram according to first embodiment of the invention;
Fig. 3 is a GOA panel test pattern diagram of the present invention;
Fig. 4 is the panel of LCD subregion synoptic diagram according to second embodiment of the invention;
Fig. 5 is the panel of LCD subregion welding bridge joint place synoptic diagram according to second embodiment of the invention;
Fig. 6 is the panel of LCD subregion metal-oxide semiconductor (MOS) bridge joint place synoptic diagram of second embodiment of the invention;
Fig. 7 is the synoptic diagram of the panel of LCD of second embodiment of the invention with the pulldown signal subregion.Wherein Reference numeral is:
101: grid line 102: defect point
103: all the other grid lines 201: gate drivers
202: grid line 203: face glass
204: positive sequential input end 205: positive timing sequence test pad
206: anti-phase sequential input end 207: start signal input end
208: anti-phase timing sequence test pad 209: start signal testing weld pad
210: thin film transistor (TFT) 211: data line
212: pulldown signal input end 213: the pulldown signal testing weld pad
301: grid line 302: defect point
401: grid line 402: gate drivers
403: face glass 404: positive sequential input end
405: positive timing sequence test pad 406: anti-phase sequential input end
407: anti-phase timing sequence test pad 408: start signal input end
409: start signal testing weld pad 410: zone
411: thin film transistor (TFT) 412: zone
413: data line 414: the pulldown signal input end
415: pulldown signal testing weld pad 501: the start signal testing weld pad
502: the welding bridge joint 502a of place: welding bridge joint place enlarged drawing
503: zone 504: zone
505: start signal testing weld pad 506: positive timing sequence test pad
507: positive timing sequence test pad 508: welding bridge joint place
509: anti-phase timing sequence test pad 510: anti-phase timing sequence test pad
511: welding bridge joint place 512: pulldown signal testing weld pad
513: pulldown signal testing weld pad 514: welding bridge joint place
515: face glass 601: the start signal testing weld pad
602: metal-oxide semiconductor (MOS) bridge joint place 603: zone
602a: metal-oxide semiconductor (MOS) bridge joint place enlarged drawing 604: zone
605: start signal testing weld pad 606: positive timing sequence test pad
607: positive timing sequence test pad 609: anti-phase timing sequence test pad
608: metal-oxide semiconductor (MOS) bridge joint place 610: anti-phase timing sequence test pad
611: metal-oxide semiconductor (MOS) bridge joint place 612: pulldown signal testing weld pad
614: metal-oxide semiconductor (MOS) bridge joint place 613: pulldown signal testing weld pad
701: gate drivers 615: face glass
703: zone 702 in the non-test: pulldown signal input end
704: zone in the test
Embodiment
The invention provides a kind of method of testing of panel of LCD,, can test the thin film transistor (TFT) on many grid lines simultaneously in order to when being integrated in gate driver circuit on the panel of LCD.The first embodiment of the present invention is that the positive sequential input end of the gate drivers of selection area on the panel of LCD, anti-phase sequential input end and start signal input end are electrically connected at corresponding testing weld pad respectively.After the gate drivers in selected zone is opened grid line, can test the pixel of thin film transistor (TFT) representative in all selection areas.
Please refer to Fig. 2, it shows the synoptic diagram according to the panel of LCD selection area of first embodiment of the invention.Gate drivers 201 is integrated on the face glass 203 with grid line 202.The positive sequential input end 204 of the gate drivers in the selection area 201 is electrically connected at a positive timing sequence test pad 205.This testing weld pad 205 may extend to beyond the face glass 203, in order to input positive clock signal.Identical, anti-phase sequential input end 206, pulldown signal input end 212 and start signal input end 207 can model identical connect.The anti-phase sequential input end 206 of the gate drivers in the selection area 201 is electrically connected at an anti-phase timing sequence test pad 208.This testing weld pad 208 may extend to beyond the face glass 203, in order to the input inversion clock signal.The pulldown signal input end 212 of the gate drivers in the selection area 201 is electrically connected at a drop-down signal testing pad 213.This testing weld pad may extend to beyond the face glass 203, in order to the input pulldown signal.The start signal input end 207 of the gate drivers in the selection area 201 is electrically connected at an initial signal testing pad 209.This testing weld pad may extend to beyond the face glass 203, in order to the input start signal.When positive clock signal, anti-phase clock signal, pulldown signal and start signal are imported positive timing sequence test pad 205, anti-phase timing sequence test pad 208, pulldown signal testing weld pad 213 and start signal testing weld pad 209 respectively, 201 of gate drivers begin to drive in all selection areas grid line 202 and on thin film transistor (TFT) 210.Test signal is sent to all data lines 211, and all thin film transistor (TFT)s 210 in the selection area promptly bear test voltage simultaneously to test.The selection area scope of Fig. 2 is for amplifying for example, and it is not to be limited to shown scope.Selection area can comprise all grid lines of full wafer panel of LCD.
Please refer to Fig. 3, it illustrates GOA panel test pattern diagram of the present invention.When all grid lines 301 of test panel simultaneously, all defect point 302 can be found simultaneously on the panel, and does not retain any test blindspot.
The second embodiment of the present invention is panel of LCD to be divided in a plurality of zones respectively the zone is tested.Panel of LCD is divided into a plurality of zones.Please refer to Fig. 4, it illustrates the panel of LCD subregion synoptic diagram according to second embodiment of the invention.Each zone comprises a grid line 401 at least.Gate drivers 402 is integrated on the face glass 403 with grid line 401.Is example at this with two zones after dividing, so that the division points between the zone to be shown.Positive sequential input end 404 with the gate drivers in the zone 402 is electrically connected at a positive timing sequence test pad respectively.This testing weld pad 405 may extend to beyond the face glass 403, in order to import the positive clock signal respectively.Anti-phase sequential input end 406 with the gate drivers in the zone 402 is electrically connected at an anti-phase timing sequence test pad 407 respectively.This testing weld pad 407 may extend to beyond the face glass 403, in order to difference input inversion clock signal.Pulldown signal input end 414 with the gate drivers in the zone 402 is electrically connected at a drop-down signal testing pad 415 respectively.This testing weld pad may extend to beyond the face glass 403, in order to import pulldown signal respectively.Start signal input end 408 with the gate drivers in each zone 402 is electrically connected at an initial signal testing pad 409 respectively.This testing weld pad may extend to beyond the face glass 403, in order to import start signal respectively.
All start signal testing weld pads 409, positive timing sequence test pad 405, anti-phase timing sequence test pad 407 and pulldown signal testing weld pad 415 mutual electrical isolation.For example, be sent to the anti-phase timing sequence test pad 407 in zone 410 and pulldown signal when being sent to the pulldown signal testing weld pad 415 in zone 410 when start signal is sent to positive timing sequence test pad 405, anti-phase sequential that zone 410 start signal testing weld pad 409, positive sequential be sent to zone 410, the gate drivers in zone 410 then begin in the drive area 410 grid line 401 and on thin film transistor (TFT) 411.Test signal is sent to the data line 413 of All Ranges, and all thin film transistor (TFT)s 411 in the zone 410 promptly bear test voltage simultaneously to test.After zone 410 tests are finished, utilize this moment another group start signal to be sent to anti-phase timing sequence test pad 407 and the pulldown signal that positive timing sequence test pad 405, anti-phase sequential that zone 412 start signal testing weld pad 409, positive sequential be sent to zone 412 be sent to zone 412 again and be sent to the pulldown signal testing weld pad 415 in zone 412, and stop the grid line 401 of drive area 410.Grid line 401 in 402 beginnings of 412 gate drivers drive area 412, zone and on thin film transistor (TFT) 411.Test signal is sent to the data line 413 of All Ranges, and all thin film transistor (TFT)s 411 in the zone 412 promptly bear test voltage simultaneously to test.The testing sequence of subregion test is not limited to the zone down test in regular turn by the top, and can be tested from lower to upper by the zone of panel below, and can be simultaneously from the top and the zone of below begin to test.
So analogize, the All Ranges of panel of LCD will be tested respectively.After All Ranges test finishes, the signal connecting line of All Ranges is electrically connected again.
Among the second above-mentioned embodiment, for will reaching the mutual electrical isolation of signal testing pad between the zone, and electrically connect mutually, enumerate two kinds at this and isolate and connected mode in the test back that finishes.First kind please refer to Fig. 5, and it illustrates the panel of LCD subregion welding bridge joint place synoptic diagram according to second embodiment of the invention.This example is to weld to form between bridge joint place 502, positive clock signal testing weld pad 506 and the positive clock signal testing weld pad 507 to form between welding bridge joint place 508, anti-phase clock signal testing weld pad 509 and the anti-phase clock signal testing weld pad 510 in formation between the start signal testing weld pad 501 in zone and the start signal testing weld pad 505 to weld formation welding bridge joint place 514 between bridge joint place 511 and pulldown signal testing weld pad 512 and the anti-phase clock signal testing weld pad 513.All bridge joint places all are arranged on the face glass 515 (substrate workspace).With welding bridge joint place 502 is example, and the enlarged drawing 502a of place is pointed by arrow for its welding bridge joint.The enlarged drawing at other welding bridge joint place is all identical.For example, the welding bridge joint place 502,508,511 and 514 between zone 503 and the zone 504 makes the signal that is sent to start signal testing weld pad 501, positive clock signal testing weld pad 506, anti-phase clock signal testing weld pad 509 and pulldown signal testing weld pad 512 can't be sent to start signal pad 505, positive clock signal testing weld pad 507, anti-phase clock signal testing weld pad 510 and pulldown signal testing weld pad 513.After the All Ranges test finishes, electrically connect welding bridge joint place 502,508,511 and 514 with scolding tin, then can further carry out follow-up test, for example full test of panel.
Second kind please refer to Fig. 6, and it illustrates the panel of LCD subregion metal-oxide semiconductor (MOS) bridge joint place synoptic diagram of second embodiment of the invention.This example is to form metal-oxide semiconductor (MOS) bridge joint place 602 between the start signal testing weld pad 601 in zone and start signal testing weld pad 605, form metal-oxide semiconductor (MOS) bridge joint place 608 between positive clock signal testing weld pad 606 and the positive clock signal testing weld pad 607, form between anti-phase clock signal testing weld pad 609 and the anti-phase clock signal testing weld pad 610 and form metal-oxide semiconductor (MOS) bridge joint place 614 between metal-oxide semiconductor (MOS) bridge joint place 611 and pulldown signal testing weld pad 612 and the anti-phase clock signal testing weld pad 613.All bridge joint places all are arranged on the face glass 615 (substrate workspace).With metal-oxide semiconductor (MOS) bridge joint place 602 is example, and enlarged drawing 602a is pointed by arrow at its metal-oxide semiconductor (MOS) bridge joint place.For example, the metal-oxide semiconductor (MOS) bridge joint place 602,608,611 and 614 between zone 603 and the zone 604 makes the signal that is sent to start signal pad 601, positive clock signal testing weld pad 606, anti-phase clock signal testing weld pad 609 and pulldown signal testing weld pad 612 can't be sent to start signal pad 605, positive clock signal testing weld pad 607, anti-phase clock signal testing weld pad 610 and pulldown signal testing weld pad 613.After the All Ranges test finishes, because of working signal voltage is higher than test signal voltage, so when operating voltage is signal voltage, can puncture metal-oxide semiconductor (MOS), to electrically connect metal-oxide semiconductor (MOS) bridge joint place 602,608,611 and 614, then can further carry out follow-up test, for example full test of panel.
The purpose that the bridge joint place is set is to do for the zone to cut apart, and each zone can independently be tested.As the bridge joint place is not set, also can utilize pulldown signal to open or close the zone that reaches in the test in the non-test.With reference to Fig. 7, it illustrates the synoptic diagram of the panel of LCD of second embodiment of the invention with the pulldown signal subregion.Gate drivers 701 among the figure within each zone all can be by pulldown signal input end 702 inputs one drop-down signal.This pulldown signal can be pulled down to ground connection with the start signal in the zone.Thus, the zone 703 of input pulldown signal to the non-test can be with 704 independent tests respectively of the zone in the test.
Embodiments of the invention provide a kind of method of testing all thin film transistor (TFT)s in the zone on the GOA panel of LCD simultaneously.When thin film transistor (TFT) can be tested simultaneously, promptly improve the verification and measurement ratio of panel defect, and can accelerate test speed.On the other hand, method of testing of the present invention can reduce abandons the wasting of resources that good panel produces, and also promptly improves panel production efficiency.
Though the present invention with embodiment openly as above; yet it is not in order to limit the present invention; any those of ordinary skill in the art without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention should be as the criterion with accompanying claims scope.
Claims (19)
1, a kind of method of testing liquid crystal display panel, wherein panel of LCD has a plurality of gate driver circuits and many grid lines are integrated thereon, and described method comprises at least:
Import a positive clock signal, an anti-phase clock signal and a drop-down signal a positive sequential input end, an anti-phase sequential input end and a drop-down signal input part simultaneously to the gate drivers in selected zone;
Import an initial signal simultaneously to an initial signal input part of described gate drivers, starting the grid line of described selection area simultaneously, and open the thin film transistor (TFT) of described selection area simultaneously; And
Simultaneously send into a test signal by many data lines.
2, the method for testing liquid crystal display panel according to claim 1, the positive sequential input end of wherein said selection area is connected to a positive timing sequence test pad.
3, the method for testing liquid crystal display panel according to claim 1, the anti-phase sequential input end of wherein said selection area is connected to an anti-phase timing sequence test pad.
4, the method for testing liquid crystal display panel according to claim 1, the pulldown signal input end of wherein said selection area are connected to a drop-down signal testing pad.
5, the method for testing liquid crystal display panel according to claim 1, the start signal input end of wherein said selection area are connected to an initial signal testing pad.
6, a kind of method of testing liquid crystal display panel, panel of LCD have a plurality of gate driver circuits and many grid lines are integrated thereon, and described method comprises at least:
Dividing many grid lines is a plurality of zones;
Import a positive sequential input end, an anti-phase sequential input end and a drop-down signal input part of a positive clock signal, an anti-phase clock signal and a drop-down signal described gate drivers to each described zone simultaneously;
Simultaneously send into a test signal by all a plurality of data lines; And
Import an initial signal input part of the gate drivers of an initial signal to each described zone respectively, in order to successively starting the described grid line in described zone, and a plurality of thin film transistor (TFT)s of opening described zone respectively are to test.
7, the method for testing liquid crystal display panel according to claim 6, the positive sequential input end in wherein said zone is connected to a positive timing sequence test pad.
8, the method for testing liquid crystal display panel according to claim 6, the anti-phase sequential input end in wherein said zone is connected to an anti-phase timing sequence test pad.
9, the method for testing liquid crystal display panel according to claim 6, wherein the pulldown signal input end in each described zone is connected to a drop-down signal testing pad.
10, the method for testing liquid crystal display panel according to claim 6, wherein the start signal input end in each described zone is connected to an initial signal testing pad.
11, the method for testing liquid crystal display panel according to claim 6, wherein each described zone comprises at least one grid line.
12, the method for testing liquid crystal display panel according to claim 6, wherein the subregion test can be by the gate drivers in the zone of input one drop-down signal in a plurality of non-tests, to close the thin film transistor (TFT) in the described zone.
13, the method for testing liquid crystal display panel according to claim 6, wherein each zone order of testing is that zone by the panel top begins to test from top to bottom, zone by panel below begins to test from lower to upper, or is begun to test by the zone of panel top and below simultaneously.
14, the method for testing liquid crystal display panel according to claim 11, the wherein described start signal testing weld pad in each described zone, described positive timing sequence test pad, described anti-phase timing sequence test pad and described pulldown signal testing weld pad difference electrical isolation.
15, the method for testing liquid crystal display panel according to claim 14 wherein also is included in and again described start signal testing weld pad, described positive timing sequence test pad, described anti-phase timing sequence test pad and described pulldown signal testing weld pad is electrically connected respectively after panel test is finished.
16, as the method for testing liquid crystal display panel according to claim 14, wherein the method for the described start signal testing weld pad in each described zone of electrical isolation comprise form between the connecting line that metal-oxide semiconductor (MOS) bridge joint place is electrically connected at two described start signal testing weld pads respectively, between the connecting line of two described positive timing sequence test pads, between the connecting line of two described anti-phase timing sequence test pads and between the connecting line of two described pulldown signal testing weld pads.
17, the method for testing liquid crystal display panel according to claim 14, wherein the method for the described start signal testing weld pad in each described zone of electrical isolation comprise form between the connecting line that welding bridge joint place is electrically connected at two described start signal testing weld pads respectively, between the connecting line of two described positive timing sequence test pads, between the connecting line of two described anti-phase timing sequence test pads and between the connecting line of two described pulldown signal testing weld pads.
18, the method for testing liquid crystal display panel according to claim 15, wherein the method that electrically connects again comprises and applies a voltage in described start signal testing weld pad, described positive timing sequence test pad, described anti-phase timing sequence test pad and pulldown signal testing weld pad, to puncture described metal-oxide semiconductor (MOS) bridge joint place.
19, the method for testing liquid crystal display panel according to claim 15, wherein the method that electrically connects again comprises the described welding bridge joint place that connects described start signal testing weld pad, described positive timing sequence test pad, described anti-phase timing sequence test pad and pulldown signal testing weld pad with scolding tin.
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