CN1988521A - Decoder and decoding method for mobile communication system terminal channels - Google Patents
Decoder and decoding method for mobile communication system terminal channels Download PDFInfo
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Abstract
The invention discloses a channel decoder used applying for the third generation mobile communications system terminals, relating to the channel decoder and its corresponding method based on the hardware. To solve inefficiency of the existing decoders, the channel decoder includes: the channel type judging module for judging the wireless signal data channel type, more than one channel decoding logic modules for decoding by each transmission channel, the control module for controlling the channel decoding logic modules. The invention also discloses the decoding method, including: judging the type of channels for transmitting data, selecting and starting the channel decoding logic module according to the determined type, conducting decoding according to the chosen decoding logic modules.
Description
Technical field
The present invention relates to channel decoder and interpretation method thereof in a kind of mobile communication system, relate in particular to a kind of channel decoder and corresponding interpretation method thereof that realizes decoding based on hardware.
Background technology
Channel decoding is an important step of 3G communication system terminal physical layer.As shown in Figure 1, with TD-SCDMA is example, and the channel decoding process is: finish JD (Joint Detection, joint-detection) according to relevant parameter after receiving radio frequency signal, export the decoding of soft bit again, the data after will deciphering at last send to the process of high level (High Layer).
The channel type that channel decoding need be handled has: DCH (dedicated transmission channel), BCH (broadcast channel), FACH (forward access channel), PCH (paging channel), PICH (Page Indication Channel) and FPACH (physical access channel), wherein the decode procedure of DCH is the most complicated, the decode procedure of other channels then according to high-rise configuration, may be simplified to some extent.As shown in Figure 2, the decode procedure with DCH is that example is carried out simple declaration.This decode procedure comprises two parts: decode procedure before the demultiplexing and the decode procedure behind the demultiplexing.At first need decipher, and then decipher at the TrCH (transmission channel) of each decomposition at whole C CTrCH (code combination transmission channel).
In present 3G terminal, channel decoding process implementation procedure on DSP mainly realizes by software mode.As shown in Figure 3, existing channel decoding method is at first determined the channel type of desire decoding, then at the decode procedure of every kind of channel type, utilizes software to programme respectively, after having determined channel type, directly call the decoding program of this channel type correspondence and decode.For example, if determine that the channel type of desire decoding is a dedicated transmission channel, carry out decoding process shown in Figure 2 with calling corresponding decoding program.For different channel types, the decode procedure difference.Like this, in actual decode procedure, owing to must decode respectively at different channel types when software is realized, the difference that must cause each decoding program, caused the increase of staff's workload, and the mode of software decode is also very unfavorable for maintenance in the future: must carry out at the different channels type; If different decoding programs is to write (platform difference) by different codes, then can limit the transplantability of this coded program in the future.Because major part all adopts software to decode, and will inevitably cause a large amount of consumption of system resource, this is as good as and has reduced its overall performance the limited terminal of disposal ability.
There is following shortcoming when particularly, existing communication system terminal adopts DSP (digital signal processor) to realize channel decoding:
(1) for satisfying the decoded mode of different channels, existing channel decoding is most of to realize that by software this will consume a large amount of DSP calculation resources; Existing portable terminal is mostly realized channel decoding by pure software mode, and this has consumed the DSP calculation resources of whole system more than 60%.The other terminal just adopts hardware to realize Viterbi and Turbo decoding algorithm, and most processes of channel decoding still are the software realization, can only save a very little part (about 10%) operand like this, whole decode procedure still needs a lot of DSP calculation resources.This has caused the reduction of terminal capabilities undoubtedly.
(2) implementation strategy: call separately channel decoding function at different channel types respectively, so just need write and test the decoding function for every kind of channel, workload is big.
(3) scheduling strategy: need to determine scheduling occasion according to Transmission Time Interval (TTI) parameter that obtains at every turn; Because may there be the multiplexing of a plurality of transmission channels in a kind of business, and the TTI of each transmission channel is not quite similar.This just causes two stages of channel decoding process: behind the decode procedure and demultiplexing before the demultiplexing.So will determine which transmission channel is deciphered processing according to current time and channel TTI parameter.Owing to have a large amount of judgements and computational process in the decoding scheduling process of each business, all there is complicated scheduling process between a plurality of transmission channels between the miscellaneous service, with a kind of business, therefore implements code and realize that difficulty, error probability and test job amount are all very big.
(4) Memory Allocation principle: the transmission channel combining form according to maximum possible is distributed the maximum memory space that needs; May there be difference in the decoding of every kind of transmission channel dispatching cycle, before a TrCH decode procedure is carried out, data about this channel must be by complete reservation, so must open up a Buffer (buffer memory) that can comprise the complete decoding data of all transmission channels, for the relatively limited terminal of system resource, caused huge resource consumption.
(5) code service efficiency: the software implementation strategy causes the code development of different platform probably, and portability and durability are poor.Every kind of language platform possibility difference that DSP uses, when developing on a new DSP, the past code of exploitation often can not be transplanted, necessary recompile; In addition, because the instruction characteristics of various platforms are not quite similar, test experience in the past can not directly be used.The workload of development﹠ testing also will be bigger.
Summary of the invention
At the existing problem and shortage of realization of decoding mode in the above-mentioned existing 3G mobile communication system terminal, the purpose of this invention is to provide and a kind ofly can improve strong channel decoder that is applicable to the 3-G (Generation Three mobile communication system) terminal of terminal data disposal ability, easy care, expansion and corresponding interpretation method thereof greatly.
The present invention is achieved in that a kind of channel decoder that is applicable to mobile communication system terminal, and it comprises:
Be used to judge the channel type judge module of wireless signal data channel type;
The more than one channel decoding logic module that is used for each transmission channel decoding;
Be used to control the control module whether each channel decoding logic module starts.
Further, described channel decoding logic module is to be provided with according to all transmission channels that portable terminal need be deciphered, and promptly for arbitrary transmission channel, can select corresponding channel decoding logic module combination and realization decoding.
Further, described control module is a command register, described command register is by the operating state of corresponding digital position control channel decoding logic module, when the command register digit order number is output as high level, corresponding channel decoding logic module starts, otherwise this channel decoding logic module is closed data bypass.
Further, described channel decoding logic module is specially: be used for the data separating module that code combination transmission channel signal data separates, being used for channel separates the physical channel of mapping and separates mapping block, be used for subframe cascade module that subframe is combined successively, be used to remove second de-interleaving block that interweaves for the second time, the descrambling module that is used for bit descrambling, be used to recover with integral data separate the rate-matched module, be used to remove first de-interleaving block that interweaves for the first time, be used for the frame length recovery module that frame length recovers, the channel decoding module that is used for channel-decoding, be used for code block cascade module and the cyclic redundancy check (CRC) module that is used for error check with the code block combination.
Further, described data separating module, physical channel are separated mapping block, subframe cascade module, second de-interleaving block and descrambling module and are connected to form code combination transmission channel decoding accelerator successively, the described rate-matched module formation of separating is separated the rate-matched accelerator, and described first de-interleaving block, frame length recover module, channel decoding module, code block cascade module and cyclic redundancy check (CRC) module and connect to form transmission channel decoding accelerator successively.
Further, each channel decoding logic module of described code combination transmission channel decoding accelerator is controlled by same command register, separate the rate-matched accelerator and controlled by a command register, each channel decoding logic module of transmission channel decoding accelerator is controlled by same command register.
Further, the command register of control code combination of transmitted channel decoding accelerator and transmission channel decoding accelerator is at least 5 register.
Further, described channel decoding logic module is realized by corresponding logical circuit or chip.
A kind of terminal channel interpretation method based on the aforementioned channels decoder may further comprise the steps:
(1) channel type of judgement transmit signal data;
(2) the channel decoding logic module of desire use is selected and started to the channel type after basis is determined;
(3) carry out channel decoding by selected channel decoding logic module.
Further, carrying out channel decoding by selected channel decoding logic module in the described step (3) is specially each transmission channel is carried out serial decoding.
Further, described channel decoding logic module is started by command register, described command register is by the operating state of corresponding digital position control channel decoding logic module, when the command register digit order number is output as high level, corresponding channel decoding logic module starts, otherwise this channel decoding logic module is closed data bypass.
The present invention realizes logic module by the channel decoder in the 3G mobile communication system terminal being split as different channel decodings, and utilize command register to realize the unlatching of channel decoding logic module or close, the various channels that will decipher at the 3G mobile communication system terminal, can need select the channel decoding logic module group of use by command register, corresponding data are finished decoding through selected channel decoding logic module group successively.Channel decoding logic module of the present invention is all realized by hardware.
Particularly, the present invention has the following advantages:
(1) the channel decoding logic module of hardware realizes breaking away from the constraint of platform, widens the product adaptation face; And can save DSP calculation resources more than 90%;
(2) the channel decoding logic module can be controlled separately by command register, has improved testability and maintainability; Reduce the hardware designs of chip simultaneously and realize risk;
(3) serial realizes the mode of channel decoding, only needs to distribute the needed maximum memory capacity of TrCH to get final product, and has saved DSP and has gone up precious memory source.
Description of drawings
Fig. 1 is existing downlink chain circuit data stream journey figure;
Fig. 2 is the decoding flow chart of DCH in the existing 3G portable terminal;
Fig. 3 is the decoding schematic diagram of transmission channel in the existing 3G portable terminal;
Fig. 4 is the structural representation of channel decoder of the present invention;
Fig. 5 is the logical construction schematic diagram of CCTrCH accelerator of the present invention;
Fig. 6 is the logical construction schematic diagram that the present invention separates the rate-matched accelerator;
Fig. 7 is the logical construction schematic diagram of TrCH accelerator of the present invention;
Fig. 8 is the decoding schematic diagram of transmission channel of the present invention.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
The present invention, is divided into 3 hardware accelerators according to its cycle characteristics that is performed and finishes implementation complexity, the fixing decoded operation step of rule according to the characteristics of channel decoding.As shown in Figure 4, these 3 hardware accelerators are respectively the CCTrCH accelerator that can finish CCTrCH and separate, are used to recover and the separating the rate-matched accelerator and finish the TrCH accelerator of single transmission channel decoding of integral data.These 3 hardware accelerators are connected to command register C, R, T.Command register C, R, T are controlled by Control Software.These 3 hardware accelerator common terminal internal memories, this internal memory are used to store wireless signal data, decoding back data and execution command etc.The CCTrCH accelerator, separate the rate-matched accelerator and the TrCH accelerator is realized by hardware such as logical circuit or respective chip.The operations relevant with platform such as control bit extraction, TFCI (combinations of transport formats indication) decoding, scheduling are transferred to Control Software and are handled.This channel decoder also comprises the input module and the output module that is used for exporting behind the data decoding that is used to receive the downstream wireless signals data, but does not illustrate in the drawings.
The CCTrCH of focusing on accelerator of the present invention, the design of separating rate-matched accelerator and TrCH accelerator, the CCTrCH accelerator, separate rate-matched accelerator and TrCH accelerator characteristics by channel decoding, be designed to different realization modules respectively, these channel decodings realize that logic module is to be provided with according to all transmission channels that portable terminal need be deciphered, for arbitrary transmission channel, all can select corresponding channel decoding logic module combination and realization decoding.The present invention is directed to all channels to be decoded, need to determine needed each flow process of these channels of decoding, and these are carried out flow process integrate, so that its shared as much as possible identical decoder module; Below describe respectively.
As shown in Figure 5, the CCTrCH accelerator comprises 5 main channel decoding logic modules, is respectively: be used for data separating module that code combination transmission channel signal data separates, be used for channel and separate subframe cascade module that the physical channel of mapping separates mapping block, is used for subframe is combined successively, be used to remove second de-interleaving block that interweaves for the second time and the descrambling module that is used for bit descrambling; These 5 channel decoding logic modules realize that by hardware it is connected in series successively, and are controlled by command register C.Wherein, being designed to of command register C:
| Bit#15～#5 | Bit#4 | Bit#3 | Bit#2 | Bit#1 | Bit#0 |
| Reserved | C4 | C3 | C2 | C1 | C0 |
And each control bit Ci of command register C (i=0,1,2,3,4) independent one of them channel decoding logic module of control is when control bit Ci is changed to " 1 ", then the channel decoding logic module of control bit Ci correspondence starts, otherwise this channel decoding logic module function is closed data bypass.
As shown in Figure 6, separating the rate-matched accelerator is made of separately the rate-matched module of separating that is used to recover with integral data.This is separated the rate-matched module and is controlled by command register R.Wherein, being designed to of command register R:
| Bit#15～#1 | Bit#0 |
| Reserved | R1 |
Control bit R1 is changed to " 1 ", then separate the rate-matched module and start, otherwise this is separated the rate-matched functions of modules and closes, data bypass.
As shown in Figure 7, the TrCH accelerator comprises 5 main channel decoding logic modules, is respectively: be used to remove first de-interleaving block that interweaves for the first time, be used for the frame length that frame length recovers recover module, be used for channel-decoding channel decoding module, be used for the code block cascade module of code block combination and be used for the cyclic redundancy check (CRC) module of error check; These 5 channel decoding logic modules realize that by hardware it is connected in series successively, and are controlled by command register T.Wherein, being designed to of command register T:
| Bit#15～#5 | Bit#4 | Bit#3 | Bit#2 | Bit#1 | Bit#0 |
| Reserved | T4 | T3 | T2 | T1 | T0 |
One of them channel decoding logic module of the independent control of each control bit Ti (i=0,1,2,3,4), when control bit Ti is changed to " 1 ", then this channel decoding logic module starts, otherwise this channel decoding logic module function is closed data bypass.
Like this, command register can use any one submodule in each hardware accelerator, so the independent test of each submodule function is become quite simple.For example, when testing the performance of Turbo decoder, only need command register T to be set to Ox0004, and Control Software is with the Input Address input test vector of TrCH accelerator, and obtain dateout after starting the TrCH accelerator, relatively can finish the performance test of Turbo decoder again with output test vector.Here, the command register of control usefulness adopts 5 can realize.Command register position in the chip that the present invention adopts is 16.
The mode that the present invention adopts this multimode to control respectively can satisfy the decoding requirement of different types of channels.Specific implementation sees Table 1:
Table 1
| Channel type | Command register C | Command register R | Command register T | Remarks |
| DPCH | Ox001f | Ox0001 | Ox001f | |
| P-CCPCH | Ox001e | Ox0001 | Ox0015 | No TFCI need not do data separating |
| S-CCPCH | Ox001f，0x001e | Ox0001 | Ox001f | The configuration of TFCI may appear not having |
| PICH | Ox006，0x0002 | Ox0000 | Ox0000 | May do PICH decoding to the 5ms data |
| FPACH | Ox0000 | Ox0001 | Ox0014 | Data rearrangement is given software processes |
Be that example describes with the DPCH channel still, for the DPCH channel, command register C is set to Ox001f, has promptly started whole 5 channel decoding logic modules of CCTrCH accelerator.
Command register R is set to Ox0001 and means that promptly separating the rate-matched accelerator is in starting state; Similarly, command register T is set to Ox001f, has promptly started whole 5 channel decoding logic modules of TrCH accelerator equally.In order to understand the present invention better, be that example illustrates the selection of module quickly again with FPACH: for the FPACH channel, command register C is set to Ox0000, has promptly closed the CCTrCH accelerator; Command register R is set to Ox0001 and means that promptly separating the rate-matched accelerator is in starting state; Command register T is set to Ox0014 and promptly means and started cyclic redundancy check (CRC) module and channel decoding module.
As shown in Figure 8, interpretation method of the present invention is very simple: Control Software is at first judged channel type, and the numerical value that look-up table 1 provides is provided with 3 control registers, starts selected hardware then respectively.Because the input of hardware decoder links to each other with decoding input data, in a single day then receive starting command, then can finish decoding automatically, and export final decode results according to the setting of control register.
The present invention is directed to each TrCH decoding configuration parameter, serial starts the decoding that the TrCH accelerator is finished a TrCH.Like this, the maximum memory space demand assignment internal memory according to a TrCH gets final product.Compare at the way that a plurality of TrCH of a CCTrCH once dispatch with software decoding, saved greatly and deciphered required buffer area.
Implementation procedure of the present invention is very simple, does not need to write, debug and safeguards a large amount of software codes; The complexity that control register is set of tabling look-up almost can be ignored; And because taking of Installed System Memory space at utmost saved in the decode results serial of a plurality of transmission channels output.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those skilled in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (11)
1, a kind of channel decoder that is applicable to mobile communication system terminal, it comprises:
Be used to judge the channel type judge module of wireless signal data channel type;
The more than one channel decoding logic module that is used for each transmission channel decoding;
Be used to control the control module whether each channel decoding logic module starts.
2, the channel decoder that is applicable to mobile communication system terminal according to claim 1, it is characterized in that, described channel decoding logic module is to be provided with according to all transmission channels that portable terminal need be deciphered, promptly, can select corresponding channel decoding logic module combination and realization decoding for arbitrary transmission channel.
3, the channel decoder that is applicable to mobile communication system terminal according to claim 2, it is characterized in that, described control module is a command register, described command register is by the operating state of corresponding digital position control channel decoding logic module, when the command register digit order number is output as high level, corresponding channel decoding logic module starts, otherwise this channel decoding logic module is closed data bypass.
4, the channel decoder that is applicable to mobile communication system terminal according to claim 3, it is characterized in that described channel decoding logic module is specially: be used for the data separating module that code combination transmission channel signal data separates, being used for channel separates the physical channel of mapping and separates mapping block, be used for subframe cascade module that subframe is combined successively, be used to remove second de-interleaving block that interweaves for the second time, the descrambling module that is used for bit descrambling, be used to recover with integral data separate the rate-matched module, be used to remove first de-interleaving block that interweaves for the first time, be used for the frame length recovery module that frame length recovers, the channel decoding module that is used for channel-decoding, be used for code block cascade module and the cyclic redundancy check (CRC) module that is used for error check with the code block combination.
5, the channel decoder that is applicable to mobile communication system terminal according to claim 4, it is characterized in that, described data separating module, physical channel are separated mapping block, subframe cascade module, second de-interleaving block and descrambling module and are connected to form code combination transmission channel decoding accelerator successively, the described rate-matched module formation of separating is separated the rate-matched accelerator, and described first de-interleaving block, frame length recover module, channel decoding module, code block cascade module and cyclic redundancy check (CRC) module and connect to form transmission channel decoding accelerator successively.
6, the channel decoder that is applicable to mobile communication system terminal according to claim 5, it is characterized in that, each channel decoding logic module of described code combination transmission channel decoding accelerator is controlled by same command register, separate the rate-matched accelerator and controlled by a command register, each channel decoding logic module of transmission channel decoding accelerator is controlled by same command register.
7, the channel decoder that is applicable to mobile communication system terminal according to claim 6 is characterized in that, the command register of control code combination of transmitted channel decoding accelerator and transmission channel decoding accelerator is at least 5 register.
According to the described channel decoder that is applicable to mobile communication system terminal of arbitrary claim in the claim 1 to 7, it is characterized in that 8, described channel decoding logic module is realized by corresponding logical circuit or chip.
9, a kind of terminal channel interpretation method of the channel decoder based on claim 1 is characterized in that this method may further comprise the steps:
(1) channel type of judgement transmit signal data;
(2) the channel decoding logic module of desire use is selected and started to the channel type after basis is determined;
(3) carry out channel decoding by selected channel decoding logic module.
10, terminal channel interpretation method according to claim 9 is characterized in that, carries out channel decoding by selected channel decoding logic module in the described step (3) and is specially each transmission channel is carried out serial decoding.
11, terminal channel interpretation method according to claim 9, it is characterized in that, described channel decoding logic module is started by command register, described command register is by the operating state of corresponding digital position control channel decoding logic module, when the command register digit order number is output as high level, corresponding channel decoding logic module starts, otherwise this channel decoding logic module is closed data bypass.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860915A (en) * | 2009-04-10 | 2010-10-13 | 大唐移动通信设备有限公司 | Processing method and equipment for scheduling information |
| CN101902300A (en) * | 2010-07-27 | 2010-12-01 | 华为技术有限公司 | Decoding equipment and implementation method thereof |
| CN101615970B (en) * | 2008-06-27 | 2012-08-08 | 普天信息技术研究院有限公司 | Method and device for decoding uplink control channels in LTE TDD system |
| CN111133700A (en) * | 2017-09-22 | 2020-05-08 | 华为技术有限公司 | High-rate receiving circuit |
| CN112583771A (en) * | 2019-09-30 | 2021-03-30 | 瑞昱半导体股份有限公司 | Data mapping device and data mapping method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6594241B1 (en) * | 1999-12-08 | 2003-07-15 | Telefonaktiebolaget Lm Ericsson (Publ) | Channel-type switching control |
| EP1126651A1 (en) * | 2000-02-16 | 2001-08-22 | Lucent Technologies Inc. | Link adaptation for RT-EGPRS |
| CN1159933C (en) * | 2002-05-29 | 2004-07-28 | 信息产业部电信传输研究所 | Universal convolution encoder and viterbi decoder |
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2005
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101615970B (en) * | 2008-06-27 | 2012-08-08 | 普天信息技术研究院有限公司 | Method and device for decoding uplink control channels in LTE TDD system |
| CN101860915A (en) * | 2009-04-10 | 2010-10-13 | 大唐移动通信设备有限公司 | Processing method and equipment for scheduling information |
| CN101902300A (en) * | 2010-07-27 | 2010-12-01 | 华为技术有限公司 | Decoding equipment and implementation method thereof |
| CN111133700A (en) * | 2017-09-22 | 2020-05-08 | 华为技术有限公司 | High-rate receiving circuit |
| CN111133700B (en) * | 2017-09-22 | 2021-06-29 | 华为技术有限公司 | High-rate receiving circuit |
| US11212043B2 (en) | 2017-09-22 | 2021-12-28 | Huawei Technologies Co., Ltd. | High rate receiver circuit |
| CN112583771A (en) * | 2019-09-30 | 2021-03-30 | 瑞昱半导体股份有限公司 | Data mapping device and data mapping method |
| CN112583771B (en) * | 2019-09-30 | 2023-08-08 | 瑞昱半导体股份有限公司 | Data mapper and data mapping method |
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