CN101615970B - Method and device for decoding uplink control channels in LTE TDD system - Google Patents
Method and device for decoding uplink control channels in LTE TDD system Download PDFInfo
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Abstract
The invention discloses a method and a device for decoding uplink control channels in an LTE TDD system. The method comprises the following steps: carrying out trellis decoding of soft information received through a control channel to acquire a vector to be judged; according to a preconstructed characteristic vector matrix and the obtained vector to be judged, acquiring a fifth information bit value and a ninth information bit value, wherein characteristic vector groups consisting of characteristic vectors in the characteristic vector matrix respectively corresponding to each information bit in an information bit sequence; according to the acquired fifth information bit value and the ninth information bit value and characteristic vectors in the characteristic vector matrix corresponding to both bit values, carrying out interference removing of the vector to be judged to acquire a new vector to be judged; and according to the corresponding relation of the characteristic vector matrix and the new vector to be judged, acquiring other information bit values in the information bit sequence. Meanwhile, the invention also discloses a device for decoding uplink control channels in the LTE TDD system. The method and the device reduce decoding complexity of uplink control channels in the LTE TDD system, and ensure decoding performance.
Description
Technical field
The present invention relates to wireless communication system channel coding and decoding technology, the method and the code translator of ascending control channel decoding in particularly a kind of long-term advancing time division duplex (LTE TDD, Long Term Evolution Time Division Duplex) system.
Background technology
In TD SDMA (TD-SCDMA, the Time Division-Synchronous CodeDivision Multiple Access) system, control information uses RM (Reed-Muller) coding sign indicating number to carry out; The information bit length of codified is shorter; For example, the block code length behind the coding is 16bit, and the information bit length of long codified is 5bit; Or the block code length behind the coding is 32bit, and the information bit length of long codified is 6bit.General soft, the hard associated translation method (being related operation) of using realizes the block code behind the coding is deciphered, because the information bit length of codified is shorter, realizes comparatively simple.
In the existing LTE TDD system, use to shorten the RM sign indicating number of structure control information is encoded, coding back length is 20bit, and the information bit length of long codified is 14bit.When using soft, hard associated translation method to decipher; Because complexity and information encoded bit length exponent function relation, therefore, the coding than growing after using soft, hard associated translation method that control information is encoded is deciphered; Decoding complexity is higher, realizes complicated.
Summary of the invention
In view of this, a main purpose of the present invention is to provide the method for ascending control channel decoding in the LTE TDD system, can reduce the decoding performance of the complexity and the assurance LTE TDD system of control channel decoding in the LTE TDD system.
Another main purpose of the present invention is to provide ascending control channel code translator in the LTE TDD system, can reduce the decoding performance of the complexity and the assurance LTE TDD system of control channel decoding in the LTE TDD system.
For achieving the above object, the invention provides the method for ascending control channel decoding in the LTE TDD system, this method may further comprise the steps:
Soft information to receiving through control channel is carried out trellis decoding, obtains vector to be adjudicated;
According to the feature matrix of constructing in advance and the vector to be adjudicated of acquisition; Obtain the 5th and the 9th information bit value in the information bit sequence, each information bit in the characteristic vector group difference corresponding informance bit sequence that the characteristic vector in the said feature matrix is formed;
According to the 5th and the 9th information bit value of obtaining, and in said feature matrix with the 5th and the 9th information bit characteristic of correspondence vector, the vector to be adjudicated that obtains is gone to disturb, obtain vector newly to be adjudicated;
According to said feature matrix corresponding relation and vector newly to be adjudicated, obtain all the other information bit values except that the 5th and the 9th information bit value in the information bit sequence.
Said trellis decoding specifically comprises: Viterbi decoding or soft input soft output decode, the soft input soft output decode of perhaps simplifying.
Said feature matrix specifically comprises:
Said feature matrix comprises 64 characteristic vectors, and said information bit sequence is 14 bits;
The the 5th, the 9th, the 7th information bit in the characteristic vector group difference corresponding informance bit sequence that the 1st to the 6th characteristic vector in the said feature matrix, the 7th to the 12nd characteristic vector and the 13rd to the 18th characteristic vector are formed;
The the 19th to the 62nd characteristic vector in the said feature matrix, the characteristic vector group that per 4 characteristic vectors are formed be the 1st, 2,3,4,6,8,10,11,12,13,14 information bit bits in the corresponding informance bit sequence successively respectively;
The the 63rd to the 64th characteristic vector in the said feature matrix is used for vector said to be adjudicated is gone to disturb.
Said the 5th information bit value of obtaining specifically comprises:
With said wait to adjudicate in vector and the 5th information bit characteristic of correspondence Vector Groups each characteristic vector respectively step-by-step do and computing; Then 20 bits among the result who obtains after each step-by-step and the computing are carried out the bit XOR, obtain the result of calculation of 61 bits respectively;
If in 6 result of calculations that obtain the value more than 4 or 4 being arranged is 1, then the 5th information bit value is 1, otherwise is 0.
Vector said to be adjudicated is gone to disturb, obtains and newly wait to adjudicate vector and specifically comprise:
If the result of calculation of said the 5th information bit and said the 9th information bit all is 0, then saidly waits to adjudicate vector and be vector newly to be adjudicated;
If the result of calculation of said the 5th information bit is the result of calculation of the 1, the 9th information bit is 0, then wait to adjudicate vector and XOR is done in the 63rd characteristic vector step-by-step with said, obtain said vector newly to be adjudicated;
If the result of calculation of said the 9th information bit is 1, the result of calculation of said the 5th information bit is 0, then wait to adjudicate vector and XOR is done in the 64th characteristic vector step-by-step with said, obtain said vector newly to be adjudicated;
If the result of calculation of said the 5th information bit and said the 9th information bit all is 1; Then wait to adjudicate vector and XOR is done in the 63rd characteristic vector step-by-step with said; The result who then the step-by-step XOR that obtains is obtained does XOR with the 64th characteristic vector step-by-step again, obtains said vector newly to be adjudicated.
Said all the other information bit values of obtaining specifically comprise:
With said newly wait to adjudicate in corresponding with the information bit respectively said feature matrix of vector each characteristic vector respectively step-by-step do and computing; Then 20 bits among the result who obtains after each step-by-step and the computing are carried out the bit XOR, obtain a said information bit characteristic of correspondence vector result of calculation respectively;
If surpassing half the value in the result of calculation that obtains is 1, then this information bit bit is 1, otherwise is 0.
Ascending control channel code translator in the long-term advancing time division duplex LTE TDD system, this device comprises trellis decoding unit and characteristic vector decoding unit, wherein,
Said trellis decoding unit is used for the soft information that receives through control channel is carried out trellis decoding, obtains vector to be adjudicated, and is sent to said characteristic vector decoding unit;
Said characteristic vector decoding unit; According to feature matrix of constructing in advance and the vector said to be adjudicated that receives; Obtain the 5th and the 9th information bit value in the information bit sequence, each information bit in the characteristic vector group difference corresponding informance bit sequence that the characteristic vector in the said feature matrix is formed; According to the 5th and the 9th information bit value of obtaining, and in said feature matrix with the 5th and the 9th information bit characteristic of correspondence vector, the vector said to be adjudicated that obtains is gone to disturb, obtain vector newly to be adjudicated; According to all the other information bit characteristic of correspondence vectors except that the 5th and the 9th information bit value and said vector newly to be adjudicated in the information bit sequence, obtain all the other information bit values.
Said trellis decoding unit specifically comprises: Viterbi decoding module or soft input soft output decode module, the soft input soft output decode module of perhaps simplifying are used for the soft information that receives is carried out trellis decoding.
Said characteristic vector decoding unit comprises: characteristic vector memory module, control module, decoding module, judge module, information bit memory module, goes to disturb module and waits to adjudicate the vector memory module, wherein,
Said trellis decoding unit is used for the vector to be adjudicated that decoding is obtained is sent to and waits to adjudicate the vector memory module;
Said characteristic vector memory module is used to store feature matrix, and said feature matrix comprises 64 characteristic vectors, 14 information bits in the corresponding informance bit sequence;
Respectively corresponding the 5th, the 9th, the 7th information bit of the 1st to the 6th characteristic vector in the said feature matrix, the 7th to the 12nd characteristic vector and the 13rd to the 18th characteristic vector;
Corresponding successively respectively the 1st, 2,3,4,6,8,10,11,12,13,14 information bits of the 19th to the 62nd characteristic vector in the said feature matrix, per 4 characteristic vectors;
The the 63rd to the 64th characteristic vector in the said feature matrix is used for vector said to be adjudicated is gone to disturb;
Said control module is provided with corresponding relation, and corresponding relation comprises each information bit characteristic of correspondence set of vectors and the corresponding corresponding relation that removes to disturb characteristic vector of the 5th and the 9th information bit in the information bit sequence,
Be used for reading the information bit value of corresponding information bit and receiving saidly going to disturb that module sends removes to disturb the completion indication information from said information bit memory module,
If the information that reads only comprises the 5th and the 9th information bit value; According to the said the 5th and the 9th information bit value that reads and the corresponding relation of setting, read the corresponding characteristic vector that goes to disturb from said characteristic vector memory module, be sent to and disturb module; Otherwise; According to the corresponding relation that is provided with, read the corresponding pairing characteristic vector group of next information bit of this information bit from said characteristic vector memory module, be sent to said decoding module;
If receive the said completion indication information that goes to disturb, read the 7th information bit characteristic of correspondence set of vectors from said characteristic vector memory module, be sent to decoding module;
Said decoding module is used for according to the characteristic vector group that receives, and waits to adjudicate the vector memory module and reads vector to be adjudicated from said, and the vector to be adjudicated that reads is deciphered, and obtains the characteristic vector result of calculation that the characteristic vector group comprises, and is sent to judge module;
Said judge module is used to receive the result of calculation of said decoding module decoding and confirms the pairing characteristic vector result of calculation of information bit number,
If in the 1st to the 6th result of calculation that judge to receive the value more than 4 or 4 being arranged is 1, sending the 5th information bit value to said information bit acquisition module is 1 indication, otherwise, send the 5th information bit value and be 0 indication;
If judge that in the 7th to the 12nd result of calculation value more than 4 or 4 being arranged is 1, sending the 9th information bit value to said information bit acquisition module is 1 indication, otherwise, send the 9th information bit value and be 0 indication;
If judge that in all the other information bit characteristic of correspondence vector result of calculations the value above half being arranged is 1; Sending corresponding information bit value to said information bit bit acquisition module is 1 indication; Otherwise sending corresponding information bit value to said information bit bit acquisition module is 0 indication;
The information bit acquisition module is used to store the 5th information bit value, the 9th information bit value and corresponding all the other information bit values except that the 5th and the 9th information bit value of reception;
Saidly go to disturb module; Be used for and disturb characteristic vector and to wait to adjudicate the vector to be adjudicated that the vector memory module reads from going of receiving of said control module from said; Do the step-by-step XOR; And operation result is sent to the said vector memory module of waiting to adjudicate, the vector said to be adjudicated of updated stored sends to said control module and to remove to disturb the completion indication information;
Saidly wait to adjudicate the vector memory module, be used to receive the vector to be adjudicated that said trellis decoding unit sends, store, remove to disturb the vector said to be adjudicated that goes to disturb the operation result updated stored that module is sent according to said.
Said control module comprises: correspondence memory, information bit value reader, controller and go to disturb and accomplish the indication information receiver,
Said correspondence memory, the corresponding relation of information bit and characteristic vector group and the 5th and the 9th information bit and the corresponding relation that removes to disturb characteristic vector in the stored information sequence;
Said information bit value reader is used for reading from said information bit acquisition module the information bit value of corresponding information bit, is sent to controller;
Controller is judged the information that information bit value reader sends,
If only comprise the 5th and the 9th information bit value; Corresponding relation according to the said the 5th and the 9th information bit value and said correspondence memory; Read the corresponding characteristic vector that goes to disturb from said characteristic vector memory module, be sent to the said module of going to disturb, otherwise; According to last information bit value that receives and the corresponding relation of said correspondence memory; Read the corresponding pairing characteristic vector group of next information bit of this last information bit from the characteristic vector memory module, be sent to decoding module
If receive the said completion indication information that goes to disturb, read the 7th information bit characteristic of correspondence set of vectors from said characteristic vector memory module, be sent to said decoding module;
Said go to disturb accomplish the indication information receiver, be used to receive and saidly go to disturb going that module sends and disturb the completion indication information, be sent to said controller.
Said decoding module comprises and computing circuit and XOR circuit,
Said and computing circuit; Be used for according to the characteristic vector group that receives; Wait to adjudicate the vector memory module and read vector to be adjudicated from said; Said characteristic vector group characteristic of correspondence vector is done and computing with vector said to be adjudicated respectively, exported the result who obtains after each step-by-step and the computing to said XOR circuit successively then;
Said XOR circuit is used to receive result said and computing circuit output, does the bit XOR, obtains the result of calculation of characteristic vector group characteristic of correspondence vector 1 bit respectively, is sent to said judge module.
Said judge module comprises: receiver, counter, determining device,
Said receiver is used to receive the result of calculation that said decoding module decoding is sent, and is sent to said counter and said determining device,
Said counter is used for the result of calculation that said receiver sends is counted, and when the information bit characteristic of correspondence vector that count down to setting is individual, triggers said determining device and judges;
Said determining device is used for according to the triggering signal of said counter transmission the result of calculation that receives being judged,
If in the 1st to the 6th result of calculation that receives the value more than 4 or 4 being arranged is 1, sending the 5th information bit value to said information bit acquisition module is 1 indication, otherwise, send the 5th information bit value and be 0 indication;
If in the 7th to the 12nd result of calculation value more than 4 or 4 being arranged is 1, sending the 9th information bit value to said information bit bit acquisition module is 1 indication, otherwise, send the 9th information bit value and be 0 indication;
If judge that in all the other information bit characteristic of correspondence vector result of calculations the value above half being arranged is 1; Sending corresponding information bit value to said information bit bit acquisition module is 1 indication; Otherwise sending corresponding information bit value to information bit bit acquisition module is 0 indication.
Visible by above-mentioned technical scheme; The method and the code translator of ascending control channel decoding in the LTE TDD provided by the invention system; Through the structural feature vector matrix; In the feature matrix; Characteristic vector composition characteristic set of vectors, characteristic vector group be the information bit in the corresponding informance bit sequence respectively, will through waiting of obtaining of trellis decoding adjudicate vector at first with information bit sequence in the 5th and the 9th information bit characteristic of correspondence set of vectors each characteristic vector carry out related operation respectively; Obtain the 5th and the 9th information bit value according to operation result; And remain to be adjudicated vector and go to disturb and obtain the vector to be adjudicated that upgrades former according to the 5th and the 9th information bit value of obtaining, utilize each characteristic vector of waiting to adjudicate in vector and the information bit sequence in all the other information bit characteristic of correspondence set of vectors of upgrading to carry out related operation respectively, thereby obtain all the other information bit values.Reduce the complexity of LTE TDD system neutral line nonsystematic code decoding and guaranteed the decoding performance of LTE TDD system.
Description of drawings
Fig. 1 is the method flow sketch map of control channel decoding in the LTE TDD of the present invention system;
Fig. 2 is a control channel code translator structural representation in the LTE TDD provided by the invention system;
Fig. 3 is a characteristic vector decoding unit structural representation of the present invention;
Fig. 4 is a control module structural representation of the present invention;
Fig. 5 is a decoding module structural representation of the present invention;
Fig. 6 is a judge module structural representation of the present invention;
Fig. 7 is that decoding algorithm provided by the invention compares sketch map with the decoding performance simulation result that has now under soft, hard associated translation algorithm QPSK, the AWGN condition.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing and specific embodiment that the present invention is done to describe in detail further below.
The method and the code translator of ascending control channel decoding in the LTE TDD provided by the invention system; Through the structural feature vector matrix; Characteristic vector group in the information bit bit difference character pair vector matrix of codified; The corresponding a plurality of characteristic vectors of characteristic vector group; Will through waiting of obtaining of trellis decoding adjudicate vector at first with the information bit bit of codified in the 5th and the 9th information bit characteristic of correspondence set of vectors carry out related operation respectively; And remain to be adjudicated vector and go to disturb and obtain the vector to be adjudicated that upgrades former according to the result of calculation of obtaining, utilize waiting of upgrading to adjudicate in the information bit bit of vector and codified in all the other information bit characteristic of correspondence set of vectors each characteristic vector and carry out related operation respectively, thereby obtain all the other information bit values.
In the prior art; Viterbi, soft inputting and soft output (SISO; Soft Input Soft Output) trellis decoding of interpretation method and simplification thereof can directly be used in the decoding of linear system sign indicating number; Promptly, use the method for trellis decoding to decipher, from the decode results of obtaining, can directly obtain information bit for the soft information that receives from channel.
Because trellis decoding uses check matrix structure grid chart when existing linear system sign indicating number is deciphered, thereby for the linear system sign indicating number of high code check, the complexity of trellis decoding is lower.
And in the LTE TDD system, the block code length behind the control channel coding is 20bit, and the information bit length of long codified is 14bit, and code check is higher, is the nonsystematic block code of linearity, promptly linear nonsystematic code.Therefore, can not directly utilize above-mentioned trellis decoding method to decipher.That is to say, decipher,, can not obtain decode results, promptly can't obtain the information bit bit of codified though can reduce the complexity of control channel decoding in the LTE TDD system if use with the similar interpretation method of linear system sign indicating number.Thereby the present invention is higher when code check what utilize above-mentioned trellis decoding method to have, after the advantage that the complexity of trellis decoding is lower is deciphered, the first step decode results that obtains after the decoding is deciphered again, to obtain the information bit bit of codified.In describing below, abbreviate the information bit bit of codified as information bit.
Be that example describes with the Viterbi decoding algorithm below.Mainly be divided into the decoding of two steps, utilize the Viterbi decoding algorithm to obtain first step decode results, this step and existing procedure are similar; And then utilizing method of the present invention that first step decode results is adjudicated, i.e. second step decoding is to obtain information bit.
Fig. 1 is the method flow sketch map of control channel decoding in the LTE TDD of the present invention system.Referring to Fig. 1, this flow process comprises:
In this step, the structural feature vector matrix is as shown in table 1, and table 1 is the feature matrix of the present invention's structure.
Table 1
| 821248 | 946224 | 157440 | 94860 | 566442 | 639529 | 169152 | 909312 |
| 989232 | 200448 | 6796 | 642218 | 34560 | 983040 | 823344 | 188416 |
| 672938 | 442921 | 529448 | 296612 | 872578 | 120321 | 856832 | 168960 |
| 192 | 512170 | 885504 | 37056 | 132096 | 475306 | 853632 | 1020480 |
| 103436 | 541226 | 922752 | 819264 | 165388 | 741418 | 824064 | 201728 |
| 98496 | 413866 | 99072 | 823488 | 918528 | 737450 | 98824 | 856196 |
| 312994 | 540705 | 197152 | 37392 | 411274 | 704521 | 774912 | 442560 |
| 283648 | 69802 | 49792 | 153152 | 806924 | 362026 | 31806 | 225668 |
In the table 1, comprise 64 characteristic vectors, each characteristic vector is expressed as metric numerical value, corresponding to the binary system vector of a 20bit.According to from left to right, order from top to bottom is 1～64 with the characteristic vector label successively, below representes (1≤i≤14, information bit i position with characteristic i; Be positive integer) the characteristic of correspondence set of vectors, for example, the 5th characteristic of correspondence set of vectors of characteristic 5 expression information bits; Label is j (1≤j≤64 in characteristic (j) the representation feature vector matrix; Be positive integer) characteristic vector, in the characteristic vector group, corresponding a plurality of characteristic vectors.Wherein,
Characteristic (1) in the characteristic 5 character pair vector matrixs～characteristic (6).
Characteristic (7) in the characteristic 9 character pair vector matrixs～characteristic (12).
Characteristic (13) in the characteristic 7 character pair vector matrixs～characteristic (18).
In the remaining characteristic vector group; Be among characteristic 1～characteristic 4, characteristic6, characteristic 8, the characteristic 10～characteristic 14; Corresponding 4 characteristic vectors of each characteristic vector group; By its order, the characteristic (19) in the character pair vector matrix～characteristic (62) successively; Characteristic (63)～characteristic (64) is for being used for the relevant characteristic vector of computing in follow-up.Specifically,
Characteristic (19) in the characteristic 1 character pair vector matrix～characteristic (22).
Characteristic (23) in the characteristic 2 character pair vector matrixs～characteristic (26).
Characteristic (27) in the characteristic 3 character pair vector matrixs～characteristic (30).
Characteristic (31) in the characteristic 4 character pair vector matrixs～characteristic (34).
Characteristic (35) in the characteristic 6 character pair vector matrixs～characteristic (38).
Characteristic (39) in the characteristic 8 character pair vector matrixs～characteristic (42).
Characteristic (43) in the characteristic 10 character pair vector matrixs～characteristic (46).
Characteristic (47) in the characteristic 11 character pair vector matrixs～characteristic (50).
Characteristic (51) in the characteristic 12 character pair vector matrixs～characteristic (54).
Characteristic (55) in the characteristic 13 character pair vector matrixs～characteristic (58).
Characteristic (59) in the characteristic 14 character pair vector matrixs～characteristic (62).
Characteristic (63)～characteristic (64) is called and disturbs characteristic vector for the follow-up characteristic vector that need use when going to disturb.
In the practical application; In the step 101, the structural feature vector matrix only need be carried out once, constructed the structural feature vector matrix after; Feature matrix is stored, carry out handled according to the corresponding relation in the good feature matrix of structure in the flow and get final product.
Step 102 utilizes trellis decoding that the soft information that receives from control channel is deciphered, and obtains first step decode results;
In this step, can use the check matrix of block code in the TDD LTE system to set up the linear block codes grid chart, its method and prior art of setting up trellis state figure is similar, repeats no more at this.Utilize the Viterbi decoding algorithm to decipher, obtain first step decode results, and, be followed successively by the high low level that arrives according to from left to right, the corresponding decimal system number that is converted into, this decode results is the vector of 20bit, at this, is called vector to be adjudicated.
In the practical application, the first step decode results that obtains through Viterbi decoding is linear nonsystematic code, the information bit that can not directly wherein be comprised; Need decipher again, therefore, in the present embodiment; Treat the judgement vector and carry out the decoding of second step, i.e. step 103～step 105.
Step 103 according to feature matrix of constructing in advance and the vector to be adjudicated that obtains, is obtained the 5th and the 9th information bit value;
In this step,, treat the judgement vector and carry out the decoding of second step, obtain the information bit value the vector from waiting to adjudicate according to the corresponding relation of characteristic vector group and information bit in the feature matrix of constructing in advance.
Information bit comprises 14 bits, according to the position that 14 bits are arranged, treats the judgement vector respectively with the order of obtaining the 5th, 9,7,1,2,3,4,6,8,10,11,12,13,14 information bit values successively and deciphers.Certainly, in the practical application, also can treat the judgement vector respectively and decipher according to other the feature matrix corresponding relation of order and other method construct.
The method of obtaining the 5th information bit value is following:
Characteristic (1)～characteristic (6) that characteristic 5 is comprised carries out " step-by-step with " computing respectively with vector to be adjudicated; Obtain 6 step-by-steps and operation result; Then 20 bit among the result are carried out " bit XOR " computing, thereby obtain the result of calculation of 61 bits.Specifically,
Characteristic 5 comprises characteristic (the 1)～characteristic (6) in the feature matrix; To wait to adjudicate vector and characteristic (1) and carry out " step-by-step with " computing; Then 20 bit among the result after " step-by-step with " computing are carried out " bit XOR " computing, thereby obtain the result of calculation of 11 bit.
To wait to adjudicate vector and characteristic (2)～characteristic (6) successively and carry out " step-by-step with " computing respectively; Then 20 bit among the result after " step-by-step with " computing are carried out " bit XOR " computing, obtain the result of calculation of other 51 bits respectively.
If there is the value more than 4 or 4 to be " 1 " in 6 result of calculations that obtain, just there is the value that surpasses half to be " 1 ", then the 5th information bit value is " 1 ", otherwise then is " 0 ".
Characteristic 9 comprises characteristic (the 7)～characteristic (13) in the feature matrix, according to above-mentioned similar flow process, obtain the 9th information bit value.
In this step, utilize the 5th and the 9th information bit value to treat the judgement vector and go to disturb, obtain new vector to be adjudicated, new vector to be adjudicated is used for the remaining information bit is adjudicated, and promptly all the other information bit values are relevant with the 5th and the 9th information bit value.
The 5th information bit is corresponding goes to disturb characteristic vector is characteristic (63); The 9th information bit is corresponding goes to disturb characteristic vector is characteristic (64).
In above-mentioned the 5th information bit value and the 9th information bit value, if certain information bit value is " 1 ", disturbs characteristic vector with corresponding the going of this information bit and carry out " step-by-step XOR " computing waiting to adjudicate vector, the gained result is new vector to be adjudicated; If certain information bit value is " 0 ", then do not do any operation.
Table 2 be the 5th, 9 information bits need when getting different value remove to disturb characteristic vector.
Table 2
| The 5th information bit value | The 9th information bit value | What need removes to disturb |
| 0 | 0 | Do not have |
| 1 | 0 | characteristic(63) |
| 0 | 1 | characteristic(64) |
| 1 | 1 | characteristic(63) characteristic(64) |
Referring to table 2, specifically,
If the 5th information bit value and the 9th information bit value all are " 0 ", newly wait to adjudicate vector and to wait to adjudicate vector identical;
If the 5th information bit value is that " 1 ", the 9th information bit value are " 0 ", then will wait to adjudicate vector and characteristic (63) and carry out " step-by-step XOR " computing, vector newly to be adjudicated, and with waiting that newly adjudicating vector upgrades vector to be adjudicated;
If the 9th information bit value is that " 1 ", the 5th information bit value are " 0 ", then will wait to adjudicate vector and characteristic (64) and carry out " step-by-step XOR " computing, vector newly to be adjudicated, and with waiting that newly adjudicating vector upgrades vector to be adjudicated;
If the 5th information bit and the 9th information bit value all are " 1 "; Then will wait to adjudicate vector and characteristic (63) and carry out " step-by-step XOR " computing; What obtain second waits to adjudicate vector and carries out " step-by-step XOR " computing with characteristic (64) again; Vector newly to be adjudicated, and with waiting that newly adjudicating vector upgrades vector to be adjudicated;
Through the above-mentioned flow-disturbing journey of going, vector newly to be adjudicated is used for follow-up judgement to all the other information bits.
Step 105 according to all the other information bit characteristic of correspondence set of vectors and the vector newly to be adjudicated that obtains, is obtained all the other information bit values in the information bit sequence.
For remaining information bit; Characteristic (13) in characteristic 7 character pair vector matrixs～characteristic (18), respectively corresponding 4 characteristic vectors of out of Memory bit, the method for its judgement is with similar to the decision method of the 5th, 9 information bits; Different is; Information bit for corresponding 4 characteristic vectors obtains the result of calculation of 4 bits, if there is the value more than 3 or 3 to be " 1 "; Then this information bit value is " 1 ", otherwise then is " 0 ".
Specifically,
Each characteristic vector in corresponding with all the other information bits respectively set of vectors of vector of newly waiting to adjudicate that obtains is carried out " step-by-step with ", then 20 bit among each " step-by-step with " result are carried out " bit XOR " thus computing obtains the result of calculation of this information bit characteristic of correspondence vector 1 bit respectively.
At first; Obtain the 7th information bit value: will newly wait to adjudicate characteristic in vector and the set of vectors (13)～characteristic (18) and carry out " step-by-step with " respectively; Respectively 20 bit among " step-by-step with " result are carried out " bit XOR " then thus computing obtains the result of calculation of 61 bits; If there is the value more than 4 or 4 to be " 1 ", then the 7th information bit value is " 1 ", otherwise then is " 0 ";
Then; Obtain the 1st information bit value: will newly wait to adjudicate characteristic in vector and the set of vectors (19)～characteristic (22) and carry out " step-by-step with " respectively; Respectively 20 bit among " step-by-step with " result are carried out " bit XOR " then thus computing obtains the result of calculation of 41 bits; If there is the value more than 3 or 3 to be " 1 ", then the 1st information bit value is " 1 ", otherwise then is " 0 ";
Obtain all the other information bit values according to above-mentioned similar approach.
So far, finish this flow process.
In the practical application; The present invention also can not only be used for the decoding to LTE TDD system control channel; Also can be used for other system is deciphered; So long as the linear nonsystematic code behind the coding is deciphered, just can adopt trellis decoding of the present invention and the mode that characteristic vector decoding combines, obtain the information bit value.If the code check of the linear nonsystematic code that will decipher high more, the interpretation method that proposes of the present invention then, efficient is just higher.Under high code check situation, than associated translation, its decoding complexity reduces.
Fig. 2 is a control channel code translator structural representation in the LTE TDD provided by the invention system.Referring to Fig. 2, this device comprises trellis decoding unit and characteristic vector decoding unit, wherein,
The trellis decoding unit is used for the soft information that receives from control channel is carried out trellis decoding, obtains vector to be adjudicated, and is sent to the characteristic vector decoding unit;
Characteristic vector decoding unit, the characteristic vector group of forming according to the feature matrix of structure in advance, characteristic vector in the feature matrix be corresponding informance bit and the vector to be adjudicated that receives respectively, obtains the 5th and the 9th information bit value in the information bit sequence; According to go to disturb in the 5th and the 9th information bit value of obtaining and the characteristic of correspondence vector matrix characteristic vector treat the judgement vector go to disturb, obtain vector newly to be adjudicated; According to all the other information bit characteristic of correspondence set of vectors and vector newly to be adjudicated, obtain all the other information bit values, the output information bit sequence.
The trellis decoding unit specifically can use the decoding algorithm of Viterbi decoding, SISO decoding or its simplification that the soft information that receives is carried out corresponding decoding.
Fig. 3 is a characteristic vector decoding unit structural representation of the present invention.Referring to Fig. 3, this characteristic vector decoding unit comprises: characteristic vector memory module, control module, decoding module, judge module, information bit memory module, go to disturb module and wait to adjudicate the vector memory module, wherein,
The trellis decoding unit is used for the vector to be adjudicated that decoding is obtained is sent to and waits to adjudicate the vector memory module;
The characteristic vector memory module is used to store feature matrix, and feature matrix comprises the characteristic vector of 64 20 bits;
Respectively corresponding the 5th, the 9th, the 7th information bit of in the feature matrix the 1st to the 6th characteristic vector, the 7th to the 12nd characteristic vector and the 13rd to the 18th characteristic vector;
In the feature matrix the 19th is to the 62nd characteristic vector, and per 4 characteristic vectors difference is correspondence the 1st, 2,3,4,6,8,10,11,12,13,14 information bits successively;
In the feature matrix the 63rd, is used to treat the judgement vector and goes to disturb processing for removing to disturb characteristic vector to the 64th characteristic vector, wherein,
Corresponding the 5th information bit value of the 63rd characteristic vector is that " 1 ", the 9th information bit value are the situation of " 0 ",
Corresponding the 5th information bit value of the 64th characteristic vector is that " 0 ", the 9th information bit value are the situation of " 1 ",
Corresponding the 5th information bit value of the 63rd and the 64th characteristic vector is that " 1 ", the 9th information bit value are the situation of " 1 ";
Control module is provided with corresponding relation, and corresponding relation comprises information bit characteristic of correspondence set of vectors and the corresponding corresponding relation that removes to disturb characteristic vector of the 5th and the 9th information bit,
Be used for going to disturb that module sends removes to disturb the completion indication information from information bit value and reception that the information bit memory module reads the corresponding information bit,
If only comprise the 5th and the 9th information bit value,, read the corresponding characteristic vector that goes to disturb from the characteristic vector memory module according to the 5th and the 9th information bit value that reads and the corresponding relation of setting; Be sent to and disturb module; Otherwise,, read the corresponding pairing characteristic vector group of next information bit of this information bit from the characteristic vector memory module according to the corresponding relation that is provided with; Be sent to decoding module
Disturb the completion indication information if receive, read the 7th information bit characteristic of correspondence set of vectors, be sent to decoding module from the characteristic vector memory module;
According to the 5th and the 9th information bit value that reads and the corresponding relation of setting, read the corresponding characteristic vector that goes to disturb from the characteristic vector memory module, be sent to and disturb module and be specially:
If the 5th information bit value is that " 0 ", the 9th information bit value are " 0 ", the notice go to disturb module treat the judgement vector do not deal with; Certainly, also can not send announcement information, directly read the pairing characteristic vector group of the 7th information bit, be sent to decoding module from the characteristic vector memory module,
If the 5th information bit value is that " 1 ", the 9th information bit value are " 0 ", read the 63rd characteristic vector from the characteristic vector memory module, be sent to and disturb module;
If the 5th information bit value is that " 0 ", the 9th information bit value are " 1 ", read the 64th characteristic vector from the characteristic vector memory module, be sent to and disturb module;
If the 5th information bit value is that " 1 ", the 9th information bit value are " 1 ", read the 63rd and the 64th characteristic vector from the characteristic vector memory module, be sent to and disturb module.
If the 5th and the 9th information bit value all is " 1 ", from waiting that adjudicating the vector memory module reads all the other information bit characteristic of correspondence Vector Groups, is sent to decoding module;
Decoding module is used for, from waiting that adjudicating the vector memory module reads vector to be adjudicated the vector to be adjudicated that reads being deciphered according to the characteristic vector group that receives, and obtains the characteristic vector result of calculation that the characteristic vector group comprises, and is sent to judge module;
Specifically,
The characteristic vector group characteristic of correspondence vector that receives is carried out " step-by-step with " computing respectively with the vector to be adjudicated that reads; Obtain vector step-by-step of characteristic vector group characteristic of correspondence and operation result; Then 20 bit among the result are carried out " bit XOR " computing, thereby obtain the result of calculation of characteristic vector group characteristic of correspondence vector 1 bit.
Judge module is used to receive the result of calculation of decoding module decoding and confirms the pairing characteristic vector result of calculation of information bit number,
Be " 1 " if judge the value that has in the 1st to the 6th result of calculation that receives more than 4 or 4, send of the indication of the 5th information bit value for " 1 " to the information bit acquisition module, otherwise, of the indication of the 5th information bit value sent for " 0 ";
Be " 1 " if judge the value that has in the 7th to the 12nd result of calculation more than 4 or 4, send of the indication of the 9th information bit value for " 1 " to information bit bit acquisition module, otherwise, of the indication of the 9th information bit value sent for " 0 ";
Be " 1 " if judge the value that has in all the other information bit characteristic of correspondence vector result of calculations above half; Sending corresponding information bit value to information bit bit acquisition module is the indication of " 1 "; Otherwise sending corresponding information bit value to information bit bit acquisition module is the indication of " 0 ";
The information bit acquisition module is used to store the 5th information bit value, the 9th information bit value and all the other corresponding information bit values of reception;
Go to disturb module; Be used for will from going of receiving of control module disturb characteristic vector with from waiting to adjudicate the vector to be adjudicated that the vector memory module reads; Carry out " step-by-step XOR " computing; And operation result is sent to waits to adjudicate the vector memory module, the vector to be adjudicated of updated stored sends to control module and to remove to disturb the completion indication information.
Specifically,
If what receive is the 63rd characteristic vector; From waiting that adjudicating the vector memory module reads vector to be adjudicated; This is waited to adjudicate vector and the 63rd characteristic vector carries out " step-by-step XOR " computing; And operation result is sent to waits to adjudicate the vector memory module, the vector to be adjudicated of updated stored sends to control module and to remove to disturb the completion indication information;
If what receive is the 64th characteristic vector; From waiting that adjudicating the vector memory module reads vector to be adjudicated; This is waited to adjudicate vector and the 64th characteristic vector, carry out " step-by-step XOR " computing, and operation result is sent to waits to adjudicate the vector memory module; The vector to be adjudicated of updated stored removes to disturb the completion indication information to the control module transmission;
If what receive is the 63rd and the 64th characteristic vector; From waiting that adjudicating the vector memory module reads vector to be adjudicated, this is waited to adjudicate vector and the 63rd characteristic vector, carry out " step-by-step XOR " computing; Then the operation result that obtains is carried out " step-by-step XOR " computing again with the 64th characteristic vector; And operation result is sent to waits to adjudicate the vector memory module, the vector to be adjudicated of updated stored sends to control module and to remove to disturb the completion indication information.
Wait to adjudicate the vector memory module, be used to receive the vector to be adjudicated that the trellis decoding unit sends, store, according to removing to disturb the vector to be adjudicated that goes to disturb the operation result updated stored that module is sent.
Fig. 4 is a control module structural representation of the present invention.Referring to Fig. 4, this control module comprises: correspondence memory, information bit value reader, controller and go to disturb and accomplish the indication information receiver,
Correspondence memory, the corresponding relation of store information bits and characteristic vector group and the 5th and the 9th information bit and the corresponding relation that removes to disturb characteristic vector;
Information bit value reader is used for reading from the information bit memory module information bit value of corresponding information bit, is sent to controller;
Controller is judged the information that information bit value reader sends,
If only comprise the 5th and the 9th information bit value,, read the corresponding characteristic vector that goes to disturb from the characteristic vector memory module according to the corresponding relation of the 5th and the 9th information bit value and correspondence memory; Be sent to and disturb module; Otherwise,, read the corresponding pairing characteristic vector group of next information bit of this last information bit from the characteristic vector memory module according to last information bit value that receives and the corresponding relation of correspondence memory; Be sent to decoding module
Disturb the completion indication information if receive, read the 7th information bit characteristic of correspondence set of vectors, be sent to decoding module from the characteristic vector memory module;
Go to disturb and accomplish the indication information receiver, be used to receive and disturb going that module sends and disturb the completion indication information, be sent to controller.
Fig. 5 is a decoding module structural representation of the present invention.Referring to Fig. 5, this decoding module comprises and computing circuit and XOR circuit,
With computing circuit; Be used for according to the characteristic vector group that receives; From waiting that adjudicating the vector memory module reads vector to be adjudicated, characteristic vector group characteristic of correspondence vector is carried out " step-by-step with " computing respectively with vector to be adjudicated, export calculated result to the XOR circuit successively;
The XOR circuit is used to receive the result who exports with computing circuit, carries out " bit XOR " computing, obtains the result of calculation of characteristic vector group characteristic of correspondence vector 1 bit respectively, is sent to judge module.
Fig. 6 is a judge module structural representation of the present invention.Referring to Fig. 6, this judge module comprises: receiver, counter, determining device,
Receiver is used to receive the result of calculation that decoding module decoding is sent, and is sent to counter and determining device,
Counter is used for the result of calculation that receiver sends is counted, and when counting down to the information bit characteristic of correspondence vector number of setting, triggers determining device and judges;
Specifically, can carry out since 1 counting, when counting down to 6 result of calculation; Triggering when counting down to 12, triggers the judgement to the 9th information bit to the judgement of the 5th information bit; And when counting down to 62, trigger the judgement to the 14th information bit, counter O reset then.
Determining device is used for according to the triggering signal of counter transmission the result of calculation that receives being judged,
If there is the value more than 4 or 4 to be " 1 " in the 1st to the 6th result of calculation that receives, send of the indication of the 5th information bit value to the information bit acquisition module for " 1 ", otherwise, send of the indication of the 5th information bit value for " 0 ";
If have the value more than 4 or 4 to be " 1 " in the 7th to the 12nd result of calculation, send of the indication of the 9th information bit value to information bit bit acquisition module for " 1 ", otherwise, send of the indication of the 9th information bit value for " 0 ";
Be " 1 " if judge the value that has in all the other information bit characteristic of correspondence vector result of calculations above half; Sending corresponding information bit value to information bit bit acquisition module is the indication of " 1 "; Otherwise sending corresponding information bit value to information bit bit acquisition module is the indication of " 0 ".
Below in conjunction with simulation result, the effect of the inventive method is described.
Fig. 7 is decoding algorithm provided by the invention and existing soft, hard associated translation algorithm Quaternary Phase Shift Keying (QPSK; Quaternary Phase Shift Keying), the decoding performance simulation result under additive white Gaussian noise (AWGN, the AdditiveWhite Gaussian Noise) condition compares sketch map.
Referring to Fig. 7, among the figure, abscissa is bit signal to noise ratio (Eb/No, Bit Energy perNoise-density of the Signal), and ordinate is block error rate (BLER, Block Error Ratio).The decoding performance curve that the curve representation of band circle utilizes hard decision associated translation algorithm to obtain; The decoding performance curve that the curve representation of band rectangle utilizes soft-decision associated translation algorithm to obtain; Utilize the decoding performance curve of Viterbi decoding and characteristic vector decoding combination with leg-of-mutton curve representation the present invention; As can be seen from the figure, the present invention utilizes Viterbi decoding and characteristic vector decoding decoding performance that combines and the decoding performance that utilizes soft-decision associated translation algorithm to obtain to be close, and is superior to the decoding performance that utilizes hard decision associated translation algorithm to obtain.
Table 3 is Viterbi decoding provided by the invention and characteristic vector decoding combination algorithm and the comparison sheet that has soft, hard associated translation algorithm execution operation times now.
Table 3
Visible by table 3, when using hard associated translation, because the maximum code length of this coded system is 14bit, needing memory length is 8192 of the vectors of 20bit; Carry out related operation, need carry out 8192 XORs, 163840 sub-additions and 8192 comparisons.
When using soft associated translation, memory space is with associated translation is identical firmly, and needing memory length is 8192 of the vectors of 20bit; Carry out related operation, need carry out 163840 multiplication, 163840 sub-additions and 8192 comparisons.
And among the present invention, need 906 of storage 6bit data, and 64 of 20bit vectors, 128 of 32bit data are carried out related operation, need carry out 958 sub-additions, 2200 XORs, 1240 times and and 1806 comparisons.
Can find out by Fig. 7 and table 3; The present invention uses Viterbi decoding with the mode that characteristic vector decoding combines the coded system that TDD LTE control channel adopts to be deciphered; On memory space and operand, very big simplifying arranged with relevant soft, hard decoding; Greatly reduce the complexity of linear nonsystematic code decoding, realizes comparatively simple and directly, but decoding performance is not decayed.
Visible by the foregoing description; The method and the code translator of ascending control channel decoding in the LTE TDD provided by the invention system; Through the structural feature vector matrix; Characteristic vector group in the information bit difference character pair vector matrix; The information bit of the unique definite relevant position of every stack features set of vectors; Will through trellis decoding obtain waiting to adjudicate vector at first with information bit sequence in the 5th and the 9th information bit characteristic of correspondence set of vectors carry out related operation respectively, obtain the 5th and the 9th information bit value according to operation result, and remain to be adjudicated vector and go to disturb and obtain the vector to be adjudicated that upgrades former according to the 5th and the 9th information bit value of obtaining; All the other information bit characteristic of correspondence set of vectors of waiting to adjudicate in vector and the information bit sequence of utilize upgrading are carried out related operation respectively, thereby obtain all the other information bit values according to operation result.Because the interpretation method that has adopted the decoding of trellis decoding and characteristic vector to combine, thereby reduced the complexity of in the LTE TDD system linear nonsystematic code being deciphered and guaranteed the decoding performance of LTE TDD system.And, the interpretation method that trellis decoding of the present invention and characteristic vector decoding combine, suitable equally for other nonsystematic linear block codes, for the decoding of different linear nonsystematic codes, only need set up the different character set of vectors.
More than lift preferred embodiment; The object of the invention, technical scheme and advantage have been carried out further explain, and institute it should be understood that the above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (12)
1. the method that ascending control channel is deciphered in the long-term advancing time division duplex LTE TDD system is characterized in that this method may further comprise the steps:
Soft information to receiving through control channel is carried out trellis decoding, obtains vector to be adjudicated;
According to the feature matrix of constructing in advance and the vector to be adjudicated of acquisition; Obtain the 5th and the 9th information bit value in the information bit sequence, each information bit in the characteristic vector group difference corresponding informance bit sequence that the characteristic vector in the said feature matrix is formed;
According to the 5th and the 9th information bit value of obtaining, and in said feature matrix with the 5th and the 9th information bit characteristic of correspondence vector, the vector to be adjudicated that obtains is gone to disturb, obtain vector newly to be adjudicated;
According to said feature matrix corresponding relation and vector newly to be adjudicated, obtain all the other information bit values except that the 5th and the 9th information bit value in the information bit sequence.
2. the method for claim 1 is characterized in that, said trellis decoding specifically comprises: Viterbi decoding or soft input soft output decode, the soft input soft output decode of perhaps simplifying.
3. method as claimed in claim 2 is characterized in that, said feature matrix specifically comprises:
Said feature matrix comprises 64 characteristic vectors, and said information bit sequence is 14 bits;
The the 5th, the 9th, the 7th information bit in the characteristic vector group difference corresponding informance bit sequence that the 1st to the 6th characteristic vector in the said feature matrix, the 7th to the 12nd characteristic vector and the 13rd to the 18th characteristic vector are formed;
The the 19th to the 62nd characteristic vector in the said feature matrix, the characteristic vector group that per 4 characteristic vectors are formed be the 1st, 2,3,4,6,8,10,11,12,13,14 information bit bits in the corresponding informance bit sequence successively respectively;
The the 63rd to the 64th characteristic vector in the said feature matrix is used for vector said to be adjudicated is gone to disturb.
4. method as claimed in claim 3 is characterized in that, said the 5th information bit value of obtaining specifically comprises:
With said wait to adjudicate in vector and the 5th information bit characteristic of correspondence Vector Groups each characteristic vector respectively step-by-step do and computing; Then 20 bits among the result who obtains after each step-by-step and the computing are carried out the bit XOR, obtain the result of calculation of 61 bits respectively;
If in 6 result of calculations that obtain the value more than 4 being arranged is 1, then the 5th information bit value is 1, otherwise is 0.
5. like claim 3 or 4 described methods, it is characterized in that, vector said to be adjudicated gone to disturb, obtain and newly wait to adjudicate vector and specifically comprise:
If the result of calculation of said the 5th information bit and said the 9th information bit all is 0, then saidly waits to adjudicate vector and be vector newly to be adjudicated;
If the result of calculation of said the 5th information bit is the result of calculation of the 1, the 9th information bit is 0, then wait to adjudicate vector and XOR is done in the 63rd characteristic vector step-by-step with said, obtain said vector newly to be adjudicated;
If the result of calculation of said the 9th information bit is 1, the result of calculation of said the 5th information bit is 0, then wait to adjudicate vector and XOR is done in the 64th characteristic vector step-by-step with said, obtain said vector newly to be adjudicated;
If the result of calculation of said the 5th information bit and said the 9th information bit all is 1; Then wait to adjudicate vector and XOR is done in the 63rd characteristic vector step-by-step with said; The result who then the step-by-step XOR that obtains is obtained does XOR with the 64th characteristic vector step-by-step again, obtains said vector newly to be adjudicated.
6. method as claimed in claim 5 is characterized in that, said all the other information bit values of obtaining specifically comprise:
With said newly wait to adjudicate in corresponding with the information bit respectively said feature matrix of vector each characteristic vector respectively step-by-step do and computing; Then 20 bits among the result who obtains after each step-by-step and the computing are carried out the bit XOR, obtain a said information bit characteristic of correspondence vector result of calculation respectively;
If surpassing half the value in the result of calculation that obtains is 1, then this information bit bit is 1, otherwise is 0.
7. ascending control channel code translator in the long-term advancing time division duplex LTE TDD system is characterized in that, this device comprises trellis decoding unit and characteristic vector decoding unit, wherein,
Said trellis decoding unit is used for the soft information that receives through control channel is carried out trellis decoding, obtains vector to be adjudicated, and is sent to said characteristic vector decoding unit;
Said characteristic vector decoding unit; According to feature matrix of constructing in advance and the vector said to be adjudicated that receives; Obtain the 5th and the 9th information bit value in the information bit sequence, each information bit in the characteristic vector group difference corresponding informance bit sequence that the characteristic vector in the said feature matrix is formed; According to the 5th and the 9th information bit value of obtaining, and in said feature matrix with the 5th and the 9th information bit characteristic of correspondence vector, the vector said to be adjudicated that obtains is gone to disturb, obtain vector newly to be adjudicated; According to all the other information bit characteristic of correspondence vectors except that the 5th and the 9th information bit value and said vector newly to be adjudicated in the information bit sequence, obtain all the other information bit values.
8. device as claimed in claim 7; It is characterized in that; Said trellis decoding unit specifically comprises: Viterbi decoding module or soft input soft output decode module, the soft input soft output decode module of perhaps simplifying are used for the soft information that receives is carried out trellis decoding.
9. device as claimed in claim 7; It is characterized in that; Said characteristic vector decoding unit comprises: characteristic vector memory module, control module, decoding module, judge module, information bit memory module, go to disturb module and wait to adjudicate the vector memory module, wherein
Said trellis decoding unit is used for the vector to be adjudicated that decoding is obtained is sent to and waits to adjudicate the vector memory module;
Said characteristic vector memory module is used to store feature matrix, and said feature matrix comprises 64 characteristic vectors, 14 information bits in the corresponding informance bit sequence;
Respectively corresponding the 5th, the 9th, the 7th information bit of the 1st to the 6th characteristic vector in the said feature matrix, the 7th to the 12nd characteristic vector and the 13rd to the 18th characteristic vector;
Corresponding successively respectively the 1st, 2,3,4,6,8,10,11,12,13,14 information bits of the 19th to the 62nd characteristic vector in the said feature matrix, per 4 characteristic vectors;
The the 63rd to the 64th characteristic vector in the said feature matrix is used for vector said to be adjudicated is gone to disturb;
Said control module is provided with corresponding relation, and corresponding relation comprises each information bit characteristic of correspondence set of vectors and the corresponding corresponding relation that removes to disturb characteristic vector of the 5th and the 9th information bit in the information bit sequence,
Be used for reading the information bit value of corresponding information bit and receiving saidly going to disturb that module sends removes to disturb the completion indication information from said information bit memory module,
If the information that reads only comprises the 5th and the 9th information bit value; According to the said the 5th and the 9th information bit value that reads and the corresponding relation of setting, read the corresponding characteristic vector that goes to disturb from said characteristic vector memory module, be sent to and disturb module; Otherwise; According to the corresponding relation that is provided with, read the corresponding pairing characteristic vector group of next information bit of this information bit from said characteristic vector memory module, be sent to said decoding module;
If receive the said completion indication information that goes to disturb, read the 7th information bit characteristic of correspondence set of vectors from said characteristic vector memory module, be sent to decoding module;
Said decoding module is used for according to the characteristic vector group that receives, and waits to adjudicate the vector memory module and reads vector to be adjudicated from said, and the vector to be adjudicated that reads is deciphered, and obtains the characteristic vector result of calculation that the characteristic vector group comprises, and is sent to judge module;
Said judge module is used to receive the result of calculation of said decoding module decoding and confirms the pairing characteristic vector result of calculation of information bit number,
If in the 1st to the 6th result of calculation that judge to receive the value more than 4 being arranged is 1, sending the 5th information bit value to said information bit acquisition module is 1 indication, otherwise, send the 5th information bit value and be 0 indication;
If judge that in the 7th to the 12nd result of calculation value more than 4 being arranged is 1, sending the 9th information bit value to said information bit acquisition module is 1 indication, otherwise, send the 9th information bit value and be 0 indication;
If judge that in all the other information bit characteristic of correspondence vector result of calculations the value above half being arranged is 1; Sending corresponding information bit value to said information bit bit acquisition module is 1 indication; Otherwise sending corresponding information bit value to said information bit bit acquisition module is 0 indication;
The information bit acquisition module is used to store the 5th information bit value, the 9th information bit value and corresponding all the other information bit values except that the 5th and the 9th information bit value of reception;
Saidly go to disturb module; Be used for and disturb characteristic vector and to wait to adjudicate the vector to be adjudicated that the vector memory module reads from going of receiving of said control module from said; Do the step-by-step XOR; And operation result is sent to the said vector memory module of waiting to adjudicate, the vector said to be adjudicated of updated stored sends to said control module and to remove to disturb the completion indication information;
Saidly wait to adjudicate the vector memory module, be used to receive the vector to be adjudicated that said trellis decoding unit sends, store, remove to disturb the vector said to be adjudicated that goes to disturb the operation result updated stored that module is sent according to said.
10. device as claimed in claim 9 is characterized in that, said control module comprises: correspondence memory, information bit value reader, controller and go to disturb and accomplish the indication information receiver,
Said correspondence memory, the corresponding relation of information bit and characteristic vector group and the 5th and the 9th information bit and the corresponding relation that removes to disturb characteristic vector in the stored information sequence;
Said information bit value reader is used for reading from said information bit acquisition module the information bit value of corresponding information bit, is sent to controller;
Controller is judged the information that information bit value reader sends,
If only comprise the 5th and the 9th information bit value; Corresponding relation according to the said the 5th and the 9th information bit value and said correspondence memory; Read the corresponding characteristic vector that goes to disturb from said characteristic vector memory module, be sent to the said module of going to disturb, otherwise; According to last information bit value that receives and the corresponding relation of said correspondence memory; Read the corresponding pairing characteristic vector group of next information bit of this last information bit from the characteristic vector memory module, be sent to decoding module
If receive the said completion indication information that goes to disturb, read the 7th information bit characteristic of correspondence set of vectors from said characteristic vector memory module, be sent to said decoding module;
Said go to disturb accomplish the indication information receiver, be used to receive and saidly go to disturb going that module sends and disturb the completion indication information, be sent to said controller.
11., it is characterized in that said decoding module comprises and computing circuit and XOR circuit like claim 9 or 10 described devices,
Said and computing circuit; Be used for according to the characteristic vector group that receives; Wait to adjudicate the vector memory module and read vector to be adjudicated from said; Said characteristic vector group characteristic of correspondence vector is done and computing with vector said to be adjudicated respectively, exported the result who obtains after each step-by-step and the computing to said XOR circuit successively then;
Said XOR circuit is used to receive result said and computing circuit output, does the bit XOR, obtains the result of calculation of characteristic vector group characteristic of correspondence vector 1 bit respectively, is sent to said judge module.
12. device as claimed in claim 11 is characterized in that, said judge module comprises: receiver, counter, determining device,
Said receiver is used to receive the result of calculation that said decoding module decoding is sent, and is sent to said counter and said determining device,
Said counter is used for the result of calculation that said receiver sends is counted, and when the information bit characteristic of correspondence vector that count down to setting is individual, triggers said determining device and judges;
Said determining device is used for according to the triggering signal of said counter transmission the result of calculation that receives being judged,
If in the 1st to the 6th result of calculation that receives the value more than 4 being arranged is 1, sending the 5th information bit value to said information bit acquisition module is 1 indication, otherwise, send the 5th information bit value and be 0 indication;
If in the 7th to the 12nd result of calculation value more than 4 being arranged is 1, sending the 9th information bit value to said information bit bit acquisition module is 1 indication, otherwise, send the 9th information bit value and be 0 indication;
If judge that in all the other information bit characteristic of correspondence vector result of calculations the value above half being arranged is 1; Sending corresponding information bit value to said information bit bit acquisition module is 1 indication; Otherwise sending corresponding information bit value to information bit bit acquisition module is 0 indication.
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| CN1988521A (en) * | 2005-12-23 | 2007-06-27 | 大唐移动通信设备有限公司 | Decoder and decoding method for mobile communication system terminal channels |
| CN101022597A (en) * | 2007-03-19 | 2007-08-22 | 中兴通讯股份有限公司 | Channel quality identification decoding device for high-speed special physical control channel |
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| CN1400831A (en) * | 2001-08-03 | 2003-03-05 | 华为技术有限公司 | Channel coding and decoding treatment method |
| CN1988521A (en) * | 2005-12-23 | 2007-06-27 | 大唐移动通信设备有限公司 | Decoder and decoding method for mobile communication system terminal channels |
| CN101022597A (en) * | 2007-03-19 | 2007-08-22 | 中兴通讯股份有限公司 | Channel quality identification decoding device for high-speed special physical control channel |
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