CN112202530B

CN112202530B - Channel blind detection method and device, communication device and storage medium

Info

Publication number: CN112202530B
Application number: CN202011062223.2A
Authority: CN
Inventors: 任江涛; 邓敬贤; 胡剑锋; 张国松
Original assignee: Core Semiconductor Technology Beijing Co ltd
Current assignee: Core Semiconductor Technology Beijing Co ltd
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2024-03-22
Anticipated expiration: 2040-09-30
Also published as: CN112202530A

Abstract

A channel blind detection method and apparatus, a communication apparatus and a storage medium are disclosed. And receiving a subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one subframe, acquiring a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and a candidate subframe head index, determining a starting position of the first bit sequence according to the candidate subframe head index, performing de-rate matching on the first bit sequence according to the starting position to acquire a second bit sequence, decoding and checking the second bit sequence to acquire a checking result, and determining the number of candidate antenna ports and the candidate subframe head index corresponding to a third bit sequence with correct checking result as the number of antenna ports and the subframe head index corresponding to the subframe signal. Therefore, the buffer memory and the calculation amount of the solution rate matching can be reduced, and the blind detection efficiency is improved.

Description

Channel blind detection method and device, communication device and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for blind channel detection, and a communications device and storage medium.

Background

The NB-IoT (Narrow Band Internet of Things ) system has the characteristics of low speed, low power consumption, low cost, high capacity, wide coverage, multiple connections, and the like. The NPBCH (Narrowband physical broadcast channel ) of NB-IoT is used to carry MIB-NB (master information block-Narrow Band, narrowband master information block) of system broadcast information. The MIB-NB information includes scheduling information and operation mode type of SIB1 (System Information Block ), and the like.

After the transmitting end of the downlink control information determines the related data to be transmitted, the MIB-NB information is sequentially subjected to CRC (Cyclic Redundancy Check ) check, channel coding, rate matching, winding, modulation, mapping preprocessing, resource mapping and other processes, and the processed information is transmitted. If the receiving end needs to receive MIB-NB information, blind detection is needed to be carried out on the MIB-NB information, namely, the position where the MIB-NB information is located is searched in the calculated search space, the MIB-NB information at the position is decoded, and the decoded MIB-NB information is subjected to processing such as de-resource mapping, de-rate matching, descrambling, de-channel coding, CRC (cyclic redundancy check) and the like in sequence, and if the result is correct after the CRC, the blind detection is successful.

However, the blind detection method in the prior art needs to occupy a larger buffer memory, and the calculation amount is larger.

Disclosure of Invention

In view of the above, an object of the embodiments of the present invention is to provide a method and apparatus for blind detection of a channel, a communication device and a storage medium, which can reduce buffering and calculation amount of rate-de-matching and improve blind detection efficiency.

In a first aspect, an embodiment of the present invention provides a method for blind detection of a channel, where the method includes:

receiving at least one subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one subframe;

acquiring a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the index of a candidate subframe head;

determining a starting position of the first bit sequence according to the candidate sub-period frame head index;

performing de-rate matching on the first bit sequence according to the initial position to obtain a second bit sequence;

decoding the second bit sequence to obtain a corresponding third bit sequence;

checking the third bit sequence to obtain a checking result; and

and determining the number of candidate antenna ports and the candidate sub-period frame head index corresponding to the third bit sequence with correct verification result as the number of antenna ports and the sub-period frame head index corresponding to the sub-frame signal, wherein the sub-period frame head index is used for representing the position of the sub-period of the sub-frame signal in the NPBCH period.

Preferably, the number of candidate antenna ports includes 1 and 2, and the candidate sub-period frame header index includes 1, 2, 3, 4, 5, 6, 7, and 8.

Preferably, determining the starting position of the first bit sequence according to the candidate sub-period frame header index includes:

the starting position is 1 in response to the candidate sub-period frame head index being 1 or 4 or 7;

responsive to the candidate sub-period frame header index being 2 or 5 or 8, the starting position is 65; and

the starting position is 129 in response to the candidate sub-period frame header index being 3 or 6.

Preferably, performing the de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence includes:

sequentially adding the data in the second bit sequence to a plurality of data bits in a virtual circular buffer according to the starting position;

shunting the data in the virtual circular buffer; and

and performing sub-block de-interleaving on the shunted data to obtain the second bit sequence.

Preferably, in response to receiving a plurality of subframe signals transmitted by the NPBCH in one subframe, the method further comprises:

and combining the received multiple subframe signals.

In a second aspect, an embodiment of the present invention provides a channel blind detection apparatus, where the apparatus includes:

a receiving unit, configured to receive at least one subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one subframe;

a first bit sequence obtaining unit, configured to obtain a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the candidate subframe header index;

a starting position determining unit, configured to determine a starting position of the first bit sequence according to the candidate sub-period frame header index;

a de-rate matching unit, configured to perform de-rate matching on the first bit sequence according to the starting position to obtain a second bit sequence;

a decoding unit, configured to perform decoding processing on the second bit sequence to obtain a corresponding third bit sequence;

the checking unit is used for checking the third bit sequence to obtain a checking result; and

and the determining unit is used for determining the number of candidate antenna ports and the candidate subframe head index corresponding to the third bit sequence with correct verification results as the number of antenna ports and the subframe head index corresponding to the subframe signal, wherein the subframe head index is used for representing the position of the subframe signal in the NPBCH period.

In a third aspect, an embodiment of the present invention provides a communications apparatus, including a memory and a processor executing program instructions in the memory for implementing the method of the first aspect.

In a fourth aspect, an embodiment of the present invention provides a storage medium, where the storage medium is used to store a computer program, where the computer program is used to implement the method according to the first aspect.

According to the embodiment of the invention, a subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one subframe is received, a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and a candidate subframe frame head index is obtained, the starting position of the first bit sequence is determined according to the candidate subframe frame head index, the first bit sequence is subjected to rate de-matching according to the starting position to obtain a second bit sequence, the second bit sequence is subjected to decoding and checking processing to obtain a checking result, and the number of candidate antenna ports and the candidate subframe frame head index corresponding to a third bit sequence with a correct checking result are determined as the number of antenna ports and the subframe frame head index corresponding to the subframe signal. Therefore, the buffer memory and the calculation amount of the solution rate matching can be reduced, and the blind detection efficiency is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a communication system according to an embodiment of the present invention;

FIG. 2 is a flow chart of data processing of NPBCH of a transmitting device in accordance with an embodiment of the invention;

fig. 3 is a schematic diagram of the number of antenna ports and the corresponding scrambling sequences according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a virtual circular buffer according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an inter-column permutation rule according to an embodiment of the present invention;

FIG. 6 is a block diagram of a channel time-frequency domain of an NPBCH over one period according to an embodiment of the present invention;

FIG. 7 is a flow chart of a prior art NPBCH blind detection method;

FIG. 8 is a schematic diagram of a candidate sequence of the prior art;

fig. 9 is a flow chart of a channel blind detection method according to an embodiment of the invention;

FIG. 10 is a flow chart of acquiring a first bit sequence according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a correspondence between candidate sub-period frame header indexes and start positions according to an embodiment of the present invention;

FIG. 12 is a flow chart of acquiring a second bit sequence according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a channel blind detection device according to an embodiment of the present invention;

Fig. 14 is a schematic hardware configuration of a communication device according to an embodiment of the present invention.

Detailed Description

The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.

Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.

Unless the context clearly requires otherwise, the words "comprise," "comprising," and the like in the description are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present invention. As shown in fig. 1, the communication system of the embodiment of the present invention includes a transmitting apparatus 11 and a receiving apparatus 12.

In this embodiment, the transmitting device 11 is a network device, and the receiving device 12 is a terminal device.

Further, the transmitting apparatus 11 includes an encoder, so that the transmitting apparatus 11 can perform encoding and output the encoded sequence. The coded sequence is scrambled, modulated, layer mapped and precoded, RE mapped and baseband signal generated for transmission to the receiving device 12. The receiving device 12 includes a decoder, and the receiving device 12 can receive the signal transmitted by the transmitting device 101 and decode the received signal.

It should be understood that fig. 1 illustrates an architecture diagram of a communication system by way of example only and is not limiting of the architecture diagram of the communication system.

In the communication process, a transmitting end encodes information to obtain a bit sequence to be transmitted and transmits the bit sequence to be transmitted. The receiving end demodulates the received signal to obtain a set of Log Likelihood Ratios (LLRs), and the number of LLRs included in the set of LLRs is the same as the number of bits included in the bit sequence to be transmitted. The receiving end decodes according to the received set of LLRs. Wherein, whether the sender sends bit 1 or bit 0, the receiver may misjudge. For the signal r, the ratio of the probability p (r|b=0) of correctly judging 0 to the probability p (r|b=1) of correctly judging 1 at the receiving end is the likelihood ratio. For the convenience of calculation processing, the log-likelihood ratio is obtained by taking the natural logarithm, that is, llr=ln [ p (r|b=0)/p (r|b=1) ].

Further, the receiving device 12 includes, but is not limited to, a Mobile station (MobileStation, MS), a Mobile Terminal (MT), a Mobile Telephone (MT), a handset (handset), a portable device (portable equipment), etc., which may communicate with one or more core networks via a radio access network (RadioAccess Network, RAN). For example, the terminal device may be a mobile phone, a computer with a wireless communication function, or the like, and the terminal device may also be a portable, pocket-sized, hand-held, computer-built-in, or vehicle-mounted mobile apparatus or device.

Further, the transmitting device 11 may be an NB-IoT base station, or a base station of a network incorporating a convergence of other various technologies of NB-IoT, etc.

Further, the embodiment of the invention decodes the data of the downlink channel of the NB-IoT network.

Further, the embodiment of the invention decodes the downlink data of the NB-IoT network NPBCH.

Alternatively, the data processing flow of the NPBCH of the transmitting device 11 may refer to fig. 2, including the steps of:

step S110, channel coding.

In this embodiment, the channel coding process of NPBCH includes the steps of:

step S111, CRC (Cyclic Redundancy Check), cyclic redundancy check).

In this embodiment, CRC is a channel coding technique that generates a short fixed-bit check code based on a network packet, and is mainly used to detect or check errors that may occur after data transmission or storage.

Further, the MIB-NB information is 34-bit data, and the length of the CRC sequence is 16 bits when checking, so that the checked output is 50-bit data.

Further, after adding the check bits, the CRC sequence is scrambled with a specific antenna port number scrambling sequence according to the number of antenna ports configured by the base station, and the number of antenna ports and the corresponding scrambling sequence are shown in fig. 3 below. Wherein,<x _ant,0 ，x _ant,1 ，x _ant,2 ，…，x _ant,15 >for the added CRC-Mask sequence. The number of antenna ports of the transmitting end can only be 1 or 2, when the number of antenna ports of the transmitting end is 1, the data in the CRC-Mask sequence are all 0, and when the number of antenna ports of the transmitting end is 2, the data in the CRC-Mask sequence are all 1.

Step S112, TBCC coding.

In this embodiment, the coding principle of TBCC (Tail Biting convolutional code) coding: when the encoder starts to work, special initialization is carried out, the last m bits of the input information bits are sequentially input into a register of the encoder, and when the encoding is finished, the ending state of the encoder is the same as the initial state. This coding method is called tail biting coding since no tail bits are present. The TBCC codes the control information and the broadcast channel, enhances the robustness, reduces the coding cost of tail bits, overcomes the problem of code rate loss, and is suitable for iterative decoding.

Further, after the information bits are input into the TBCC coding module and subjected to TBCC coding, the number of bits of the output information is 3 times of the number of bits of the input information. Representing input bits as A ₁ ，A ₂ ，A ₃ ，……，A _k Where k is the number of bits of the input information and the output information is d ₁₁ ，d ₁₂ ，d ₁₃ ，……d _1k And, d ₂₁ ，d ₂₂ ，d ₂₃ ，……d _2k And, d ₃₁ ，d ₃₂ ，d ₃₃ ，……d _3k 。

Further, k=50.

In this embodiment, the code rate of tail-biting convolutional coding is 1/3. That is, the TBCC encoder has 50 bits of input information and 3×50 bits of output information.

Step S113, rate matching.

In this embodiment, output information of the TBCC encoding module is converted into data of a predetermined length through rate matching.

Further, 3 x 50bit data of the output of the TBCC encoding module is converted into 1600bit data through rate matching. In particular, the rate matching is implemented by one virtual circular buffer, the structure of which can be referred to in fig. 4, including three sub-block interleavers 41, 42, and 43, a bit collection unit 44, and a bit selection unit 45.

In the present embodiment, the data d obtained by encoding in the step S112 is obtained ₁₁ ，d ₁₂ ，d ₁₃ ，……，d _1k Input to the sub-block interleaver 41, d ₂₁ ，d ₂₂ ，d ₂₃ ，……d _2k Input to the sub-block interleaver 42, d ₃₁ ，d ₃₂ ，d ₃₃ ，……d _3k To the sub-block interleaver 43. Where k=50.

In the present embodiment, the workflow of the sub-block interleaver 41 includes the steps of:

step S1131, determining the number of matrix columns.

In this embodiment, the matrix column number C is determined to be 32, and the serial numbers of the columns are numbered 1,2,3, … …,32 from left to right.

Step S1132, determining the number of matrix rows.

In this embodiment, the sub-block interleaver acquires the number of matrix rows according to the determined number of matrix columns. Specifically, it can be obtained according to the following formula:

D≤(R*C)

wherein D is the number of bits of the input information of the sub-block interleaver, R is the number of matrix rows, and C is the number of matrix columns.

Further, R is the smallest integer satisfying the above formula.

Further, it may be determined that d=k=50, c=32, and thus r=2.

Further, each row of the matrix is numbered 1,2 from top left to bottom.

Thus, a matrix of 2 x 32 is obtained.

Step S1133, adding the input information to the matrix.

In this embodiment, the matrix of 2×32 has 64 data bits in total, and the number of input bits is 50, so that 14 dummy bits need to be added to the header, and then the number of bits of input information is added to other positions of the matrix.

Specifically, from row 0 and column 0 of the matrix, 14 dummy bits are added first, and then 50bit data of input information is added to the matrix sequentially.

Step S1134, inter-column permutation.

In this embodiment, the matrix obtained above is subjected to inter-column permutation according to a predetermined rule. Specifically, the substitution rule is shown in fig. 5. Each column of the matrix after the replacement is orderly marked as P from left to right ₁ ，P ₂ ，P ₃ ，……，P ₃₂ It can be seen that P ₁ ，P ₂ ，P ₃ ，……，P ₃₂ Column numbers 2, 18, 10, 26,6, 22, 14, 30,4, 20, 12, 28,8, 24, 16, 32,1, 17,9, 25,5, 21, 13, 29,3,1, respectively, prior to permutation9，11，27，7，23，15，31。

Thus, the sub-block interleaver 41 may obtain a first permutation matrix of 2 x 32.

Further, the sub-block interleavers 42 and 43 may obtain a second permutation matrix and a third permutation matrix of 2×32 according to the same procedure as described above.

In the present embodiment, the bit collection unit 44 performs data collection according to the above-described first permutation matrix, second permutation matrix, and third permutation matrix.

Specifically, a sequence of bits is read from the first permutation matrix column by column in a left to right order, denoted v ₁₁ ，v ₁₂ ，v ₁₃ ，……，v _1m Wherein m=64. Reading out a bit sequence from the second permutation matrix, denoted v ₂₁ ，v ₂₂ ，v ₂₃ ，……，v _2m Wherein m=64. Reading out a bit sequence from the third permutation matrix, denoted v ₃₁ ，v ₃₂ ，v ₃₃ ，……，v _3m Wherein m=64. Let the i (i=1, 2,3, … …,191, 192) th data of the virtual circular buffer be w _i Then:

that is, the m bit sequences read out from the first permutation matrix are sequentially added to the 1 st to m th positions of the virtual circular buffer, the m bit sequences read out from the second permutation matrix are sequentially added to the m+1th to 2*m th positions of the virtual circular buffer, and the m bit sequences read out from the third permutation matrix are sequentially added to the 2 x m+1th to 3*m th positions of the virtual circular buffer, respectively.

Further, since m=64, the virtual circular buffers share 3*m =192 bit data.

In the present embodiment, the bit selection unit 45 is configured to generate a bit sequence e of a predetermined length n.

Further, the bit selection unit 45 is configured to generate a sequence of n=1600 bits.

Further, the length of the transmission period of the NPBCH is 640ms, and the NPBCH is divided into 8 sub-periods of 80ms, and the NPBCH is transmitted in the form of repeated air interface signals in the sub-periods, so that the information bit of the NPBCH carried in each sub-period is the information quantity carried by 100 REs under the condition of QPSK modulation, namely 200 bits, and the total of 8 sub-periods is 1600 bits. Thus requiring a 1600bit rate matching output sequence length.

Specifically, the bit selection unit 45 selects one data from the virtual circular buffer in a predetermined order, determines whether the data is a dummy bit, adds the data to 1600 bits if the data is not a dummy bit, and skips the data to select the next data to continue processing until 1600 bits are filled if the data is a dummy bit.

Further, it can be known from the above principle that the virtual circular buffer shares 3×64 bits of data, and each 64 bits of data includes 50 bits of valid data, so that each 200 bits (4×50 bits) is filled, and the 4×64 bits of data in the virtual circular buffer need to be read. From this, it can be seen that, among the 192bit data in the virtual circular buffer:

the first 200 bits, the start position k0 is 1;

the second 200bit, the start position k0 is 65;

the third 200bit, start position k0 is 129;

a fourth 200bit, the starting position k0 is 1;

fifth 200bit, starting position k0 is 65;

a sixth 200bit, start position k0 is 129;

seventh 200bit, start position k0 is 1;

eighth 200bit, start position k0 is 65.

That is, the start positions of the 1 st, 4 th, and 7 th 200bit data are 1, the start positions of the 2 nd, 5 th, and 8 th 200bit data are 65, and the start positions of the 3 rd and 6 th 200bit data are 129.

Thus, 1600bit data e can be generated by rate matching ₁ ，e ₂ ，e ₃ ，……，e _n ，n＝1600。

Step S120, scrambling.

In this embodiment, scrambling is to multiply the spreading codes by a random code sequence, encrypt the signal, and downlink scrambling can be used to distinguish between cells and channels.

Further, the scrambling formula is as follows:

wherein,for the scrambled h data, e (h) is the h data after rate matching, c (h) is the h data in the random sequence, and h is more than or equal to 1 and less than or equal to 1600.

Specifically, since e (h) and c (h) are 0 or 1, scrambling is actually determined from c (h) in the random sequenceWhen c (h) is 0, < + >>When c (h) is 1, < + >>The 0/1 conversion is performed. Namely:

when e (h) =0, c (h) =0,

when e (h) =0, c (h) =1,

when e (h) =1, c (h) =0,

when e (h) =1, c (h) =1,

step S130, QPSK modulation.

In this embodiment, the NPDSCH adopts a QPSK (Quadrature Phase Shift Keying ) modulation scheme. QPSK is a four-ary phase shift keying that uses four different phase differences of the carrier to characterize the input digital information. QPSK is a phase modulation technique at m=4, which specifies four carrier phases, 45 °,135 °,225 °,315 °, respectively, and the data input by the modulator is a binary digital sequence, which is converted into quaternary data in order to match the quaternary carrier phases.

Specifically, the 1600bit data obtained by scrambling described above is divided into 8 200 bits. For each 200 bits, every two bits in the binary digital sequence are grouped together in four combinations, i.e., 00, 01, 10, 11, where each group is referred to as a two-bit symbol. Each two-bit symbol is composed of two binary information bits, which represent one symbol (symbol) of four symbols, respectively. Each modulation in QPSK can transmit 2 information bits, which are conveyed by four phases of the carrier. The demodulator judges the information bit sent by the sending end according to the phase of the received carrier signal.

Step S140, layer mapping and precoding.

In this embodiment, since the number of codewords is different from the number of transmit antenna ports, it is necessary to map codewords onto different antenna ports. The number of layers is indicated by RI (Rank Indication), rank is the Rank in the antenna matrix in the MIMO (multiple input multiple output ) scheme, i.e. the data streams that can be independently transmitted in parallel. RANK is the number of layers that the terminal tells the network side to support effectively. If the receiving end supports at most two antenna ports, the maximum value of rank can only be 2. The NPBCH performs the function of MIMO together by layer mapping and precoding. Firstly, codeword complex-valued modulation symbols to be transmitted are mapped into one or more layers through layer mapping, serial-parallel conversion is completed, the multiplexing rate of spatial multiplexing is controlled, and then, the data after layer mapping is precoded, namely, MIMO coding is realized. The precoding is used for matching the layer data to the antenna ports, reducing or controlling interference between the spatial multiplexing data streams, reducing complexity of receiver implementation, reducing system overhead, and improving performance of MIMO technology.

Step S150, RE mapping.

In this embodiment, RE (Resource Element) mapping maps the precoded output to allocated RB (Resource Block) resources through a random phase offset process, and the mapping process follows the principle of first frequency domain and then time domain, that is, all REs of one OFDM (Orthogonal Frequency Division Multiplexing ) symbol are filled first, and the next OFDM symbol is filled.

Step S160, baseband signal generation.

In this embodiment, the baseband signal is an original electrical signal sent by a source (transmitting end). Specifically, the method for generating the baseband signal may use various existing technologies, which are not described herein. Thus, a transmission signal can be generated.

Specifically, a structure diagram of a channel time-frequency domain of NPBCH over one period may refer to fig. 6. As shown in fig. 6, one period of NPBCH is 640ms, divided into 8 sub-periods of 80ms each. Each sub-period transmits a 200bit segment of data, so 1600bit data is just transmitted over 8 periods. Meanwhile, each sub-period is divided into 8 10ms, and MIB-NB signals are transmitted in 1ms of each 10ms, so that each 200bit data segment is repeatedly transmitted 8 times in each sub-period.

It should be understood that the signal processing of NPBCH is only one implementation manner of the embodiment of the present invention, which is not limited thereto, and may be implemented in various existing manners.

Further, in order to obtain MIB-NB information, the receiving device 12 needs to perform blind detection on the MIB-NB information, that is, search the calculated search space for the location where the MIB-NB information is located, and decode the MIB-NB information at the location.

Fig. 7 is a flowchart of a NPBCH blind detection method in the prior art. As shown in fig. 7, the NPBCH blind detection method of the prior art includes the steps of:

step S210, obtaining soft bit LLR.

In this embodiment, the receiving device may obtain a frame header of 80ms of the received signal in the time domain, i.e. a certain 80ms start position in one 640ms period, through cell search. Soft bit LLRs for the received subframe signals are obtained.

Specifically, sampling is carried out at a preset rate, cyclic prefix is removed, baseband data on a first subframe is extracted, and complete MIB-NB data and relevant pilot data on a time domain are obtained; performing Fourier transform to generate frequency domain data of the subframe; performing blind detection on the number of antenna ports, wherein if the number of the antenna ports is 1, the corresponding port number p=2000, and if the number of the antenna ports is 2, the corresponding port numbers p=2000 and p=2001; calculating an NRS mapping position corresponding to an antenna port number, extracting NRS (Narrow-band reference signal ), and using an NRS sequence generated locally and an NRS signal in received data to perform channel estimation so as to recover a signal at a transmitting end; performing de-resource mapping, removing resource grids occupied by reference signals LTE-CRS (Cell-Specific Reference Signal, cell specific reference signals) and NRS, and sequentially taking out complex-valued symbols from the positions of the resource grids; performing de-layer mapping and precoding according to the number of antenna ports; demodulation QPSK modulation, demodulating each complex value symbol into two bit data; thus, 200bit soft bit LLRs corresponding to the sub-frame signals when the number of antenna ports is 1 and 2 are obtained.

Further, if a plurality of subframe signals in the same subframe are received, a 200-bit soft bit LLR corresponding to each subframe signal is obtained, and the 200-bit soft bit LLRs corresponding to each subframe signal are combined. The soft bit LLR combining method may employ various existing combining methods, which are not limited in this embodiment of the present invention. For example, the combining method may be equal-proportion combining, saturation adding, or the like.

Step S220, descrambling.

In this embodiment, a random sequence of each sub-period when the transmitting device scrambles is obtained, and descrambling is performed on the obtained 200-bit data according to the random sequence.

Further, as can be seen from the above step S120, when scrambling is performed, the transmitting device may send each bit of data corresponding to one of the random sequences through one random sequence, so that each 200 bits of transmitted data corresponds to one 200 bits of random sequence, and the received data is descrambled according to the random sequence when scrambling to recover the data before scrambling.

Further, according to the step S210, soft bit LLRs of 200 bits corresponding to the number of the antenna ports 1 and 2, respectively, of the subframe signal can be obtained. And (3) obtaining random sequences of all sub-periods when the sending equipment scrambles, and respectively descrambling the obtained 200-bit soft bit LLRs according to the random sequences of all the sub-periods to obtain descrambling sequences respectively corresponding to 8 sub-periods when the number of the antenna ports is 1 and descrambling sequences respectively corresponding to 8 sub-periods when the number of the antenna ports is 2. That is, 16 200-bit data are obtained after descrambling according to the number of antenna ports and the difference of subcycles.

Step S230, rate matching is achieved.

In this embodiment, the rate-de-matching is the inverse process of the above step S113, and specifically includes the following steps:

step S231, determining candidate sequences.

In this embodiment, when the rates are matched, candidate sequences that need to be rate matched are determined.

Specifically, 16 200bit data are obtained through descrambling, and corresponding candidate sequences are determined according to the number of antenna ports and the subcycle corresponding to each 200bit data. And putting the obtained 200-bit data into the sub-period, and filling 0 into the data in other sub-periods, so that 1600-bit data can be obtained, and when the number of antenna ports is 1, 8 cases are left, and 8 1600-bit data are correspondingly obtained. Similarly, when the number of antenna ports is 2, there are 8 cases, and 8 1600bit data are correspondingly obtained.

Fig. 8 shows a candidate sequence of the number of antenna ports, where X is the sub-period frame header index. Specifically, when x=i (i=1, 2,3,4,5,6,7, 8), the data in the i-th sub-period of the 200bit data obtained above is filled with 0 in the other sub-periods.

It should be understood that fig. 8 only shows one candidate sequence of the number of antenna ports, and since there may be two cases of the number of antenna ports, there are 16 candidate sequences in total, and each candidate sequence is 1600 bits.

Step S232, rate matching is achieved.

In this embodiment, the receiving device acquires, through control information, the length D of the original sequence transmitted by the transmitting device, where the original sequence is a sequence obtained after the CRC check, that is, d=50 bits. Further, the virtual circular buffer is constructed according to the original sequence length, and the method specifically refers to fig. 4 and 5, and includes the following steps:

step S2321, determining the number of matrix columns.

Step S2322, determining the number of matrix rows.

D≤(R*C)

Further, R is the smallest integer satisfying the above formula.

Further, d=50, c=32 can be determined, and thus, r=2 can be calculated.

Further, each row of the matrix is numbered 1,2 from top left to bottom.

Thus, a matrix of 2 x 32 is obtained.

Step S2323, adding information to the matrix.

In this embodiment, the matrix of 2×32 has 64 data bits in total, and the number of bits of the original sequence is 50, so that 14 dummy bits need to be added to the header, and then the effective information is added to other positions of the matrix.

Specifically, from row 0 and column 0 of the matrix, 14 dummy bits are added first, and then 50bit data is added to the matrix in sequence.

Step S2324, inter-column permutation.

In this embodiment, the matrix obtained above is subjected to inter-column permutation according to a predetermined rule. Specifically, the substitution rule is shown in fig. 5. Each column of the matrix after the replacement is orderly marked as P from left to right ₁ ，P ₂ ，P ₃ ，……，P ₃₂ It can be seen that P ₁ ，P ₂ ，P ₃ ，……，P ₃₂ Column numbers 2, 18, 10, 26,6, 22, 14, 30,4, 20, 12, 28,8, 24, 16, 32,1, 17,9, 25,5, 21, 13, 29,3, 19, 11, 27,7, 23, 15, 31 before the permutation, respectively.

Thus, the sub-block interleaver 41 may obtain a first permutation matrix of 32×2.

Further, the sub-block interleavers 42 and 43 may obtain a second permutation matrix and a third permutation matrix of 32×2 according to the same procedure as described above.

Specifically, a sequence of bits is read from the first permutation matrix column by column in a left to right order, denoted v ₁₁ ，v ₁₂ ，v ₁₃ ，……，v _1m Wherein m=64. Reading out a bit sequence from the second permutation matrix, denoted v ₂₁ ，v ₂₂ ，v ₂₃ ，……，v _2m Wherein m=64. Reading out a bit sequence from the third permutation matrix, denoted v ₃₁ ，v ₃₂ ，v ₃₃ ，……，v _3m Wherein m=64. The ith data of the virtual circular buffer is denoted as w _i Then:

Further, since m=64, the virtual circular buffers share 3*m =192 bit data.

Thus, a virtual circular buffer can be obtained.

Step S2325, adding the candidate sequence to the virtual circular buffer.

In this embodiment, the candidate sequence obtained above is added to the virtual circular buffer.

Further, for each candidate sequence, 1600bit data is added to 192 data bits in the virtual circular buffer.

Specifically, from the above step of constructing the virtual circular buffer, it can be known that there are 150 valid bits and 42 virtual bit positions in 192 data bits. First, the first bit in the candidate sequence is selected, the first data bit in the virtual circular buffer is selected, whether the data bit is a valid bit is judged, if the data bit is a valid bit, the selected bit is filled into the data bit, if the data bit is not a valid bit, the next data bit in the virtual circular buffer is selected, and the judgment is continued. If the currently processed data bit is the last data bit in the 192 bits, the first data bit is returned at the next processing. The above steps are repeated until 1600 bits of data are all added to 192 data bits.

Further, for each data bit, multiple bits of data are received, and the multiple bits of data are combined. Thereby, 192bit data can be obtained.

Step S2326, bit splitting.

In this embodiment, the obtained 192bit data is subjected to bit splitting to obtain 3×64bit data.

Specifically, 1-64 bits of 192bit data are fetched to generate a 64bit sequence, denoted as v ₁₁ ，v ₁₂ ，v ₁₃ ，……，v _1m Wherein m=64. The 65-128 bit data is fetched to generate a 64bit sequence, denoted as v ₂₁ ，v ₂₂ ，v ₂₃ ，……，v _2m Wherein m=64. Fetching 129-192 bits of data to generate a 64bit sequence denoted v ₃₁ ，v ₃₂ ，v ₃₃ ，……，v _3m Wherein m=64. Thus, 3×64bit data can be obtained.

Step S2327, sub-block de-interleaving.

In this embodiment, for each 64bit data obtained above, it is added to a matrix of 2×32. The data of 3×50 bits can be obtained through the above procedure of step S2324 and the inverse procedure of step S2323.

Further, 3×50bit data of 16 candidate sequences may be obtained by the same method as described above.

Step S240, decoding.

In this embodiment, the above obtained 16 kinds of data with 3×50 bits are respectively decoded by TBCC to obtain 16 pieces of data with 50 bits.

Further, the TBCC decoding may be performed by various methods, which are not limited herein.

Step S250, resolving CRC.

In this embodiment, the 16 check results are obtained by respectively performing CRC decoding on the 16 50-bit data.

Further, the number of antenna ports and the sub-period frame head index corresponding to the situation that the verification result is correct are obtained as decoding results.

However, the buffer and the calculation amount are relatively large in the prior art when the rate is de-matched, and as described above, the buffer required to be occupied before the rate is de-matched is 16 x 1600bit, and the calculation amount is 16 x 160 bit.

Further, according to the rate matching process of the transmitting device, it is known that: the start bit k0 of the 1 st, 4 th and 7 th 200bit data is set to be 1, the start position k0 of the 2 nd, 5 th and 8 th 200bit data is set to be 65, and the start position k0 of the 3 rd and 6 th 200bit data is set to be 129. Therefore, the embodiment of the invention provides a channel blind detection method, which is used for reducing the buffer memory and the calculated amount of solution rate matching and improving the blind detection efficiency. As shown in fig. 9, the method comprises the following steps:

step S310, at least one subframe signal transmitted in one subframe by the narrowband physical broadcast channel NPBCH is received.

In this embodiment, the receiving device may obtain a frame header of 80ms of the received signal in the time domain, i.e. a certain 80ms start position in one 640ms period, through cell search. At least one subframe signal transmitted in one subframe is received by a narrowband physical broadcast channel NPBCH.

Further, if a plurality of subframe signals within the same subframe are received, each subframe signal is combined. The merging method may be any existing merging method, which is not limited in this embodiment of the present invention. For example, the combining method may be equal-proportion combining, saturation adding, or the like.

Step S320, obtaining a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the index of the candidate subframe header.

In this embodiment, the method for obtaining soft bit LLRs of a received subframe signal, as shown in fig. 10, includes the following steps:

and S321, extracting the sampled NPBCH baseband data, and carrying out Fourier transform to obtain frequency domain data.

In this embodiment, sampling is performed at a predetermined frequency, cyclic prefix is removed, baseband data on a first subframe is extracted, and complete MIB-NB data and related pilot data in the time domain are obtained. Fourier transform is performed to generate frequency domain data for the subframe.

Step S322, performing channel estimation by NRS, and recovering the transmitting signal.

In this embodiment, blind detection is performed on the number of antenna ports, if the number of antenna ports is 1, the corresponding port number p=2000 and the number of antenna ports is 2, if the corresponding port numbers p=2000 and p=2001, NRS (Narrow-band reference signal) mapping positions corresponding to the antenna port numbers are calculated, NRS signals are extracted, and channel estimation is performed by using locally generated NRS sequences and NRS signals in received data; and carrying out minimum mean square error estimation, and recovering the signal of the transmitting end by using the obtained estimation matrix.

Step S323, performing de-resource mapping.

In this embodiment, the reference signals LTE-CRS Cell-Specific Reference Signal, cell-specific reference signals) and the resource bins occupied by the NRS are eliminated, and the first three OFDM (Orthogonal Frequency Division Multiplexing ) symbols and the resource bins occupied by the reference signals are eliminated, wherein when the position of the reference signals is calculated, it is assumed that the antenna ports p=0-3 of the CRS are all present, it is assumed that the antenna port numbers p=2000 and p=2001 of the NB-IoT are all present, and complex-valued symbols are sequentially taken out from the 4 th symbol in a predetermined order.

Further, MIB-NB information is transmitted in NPBCH channel, and the data transmission period of the NPBCH channel is 8 subcycles, which is 64 frames. Therefore, it is necessary to perform blind detection on which sub-period of the NPBCH period the frame is located, and make the sub-period frame head index X take values of 1 to 8 in sequence, and then divide the value by the coefficient θf (i) corresponding to 8 10ms frame head indexes in the assumed sub-period to obtain 100 complex-valued symbols.

Where θf (i) is a random phase offset added by the transmitting device before RE mapping. Specifically, before RE mapping, the transmitting apparatus performs random phase offset processing on 100 symbol of all participating RE mappings of the 8 10ms frame header indexes corresponding to the sub-frame 0 in each sub-period, more specifically, multiplies symbol by random phase offset θf (i).

Wherein, the calculation formula of θf (i) is as follows:

where cf (2 i) and cf (2i+1) are random sequences and θf (i) is a random phase offset.

That is, when cf (2 i) =0, cf (2i+1) =0, θf (i) =1;

when cf (2 i) =0, cf (2i+1) =1, θf (i) = -1;

when cf (2 i) =1, cf (2i+1) =0, θf (i) =j;

when cf (2 i) =1, cf (2i+1) =1, θf (i) = -j.

Step S324, de-layer mapping and precoding.

In this embodiment, NPBCH uses a maximum of 2 antenna ports. When 1 antenna port is employed, the use of the antenna port number p=2000 can be regarded as signal direct transmission. When 2 antenna ports are used, the transmission diversity scheme is employed using antenna port numbers p=2000 and p=2001.

Step S325, QPSK modulation is demodulated.

In this embodiment, every two complex-valued symbols are adjusted to a pair of bit data. Thus, 200bit data can be obtained.

Thus, through the steps S321 to S325, 200bit data of the subframe signal under the number of candidate antenna ports and the index of the candidate subframe header can be obtained.

Further, since there are two candidate antenna ports, and 8 candidate sub-period frame head indexes, 16 pieces of 200bit data are obtained in total.

Step S326, descrambling.

In this embodiment, for each 200bit data obtained above, the receiving device generates a random sequence of 1600 bits (8×200 bits), and selects which 200 bits of the random sequence to descramble according to which sub-period the sub-frame signal is in the NPBCH period assumed in step S323.

In this embodiment, when scrambling is performed, the transmitting device may perform descrambling on the received data according to the random sequence during scrambling by using a random sequence, where each bit of data transmitted corresponds to one data in the random sequence, and each sub-period corresponds to one scrambling sequence, so as to recover the data before scrambling by the transmitting device.

Further, for the mapping of the candidate sub-period frame header index x=i (i=1, 2,3,4,5,6,7, 8), descrambling is performed according to the random sequence of the i-th sub-period to obtain the corresponding first bit sequence.

Specifically, the descrambling formula is as follows:

y＝LLR*(1-2c)

wherein LLR is bit sequence obtained by demodulation, c is random sequence, and y is sequence after descrambling.

As can be seen from the above formula, when c=0, y=llr; when c=1, y= -LLR.

That is, if the random sequence is 0, the demodulated bit sequence is not changed; if the scrambling sequence is 1, the demodulated bit sequence is subjected to 0/1 conversion.

Thus, a first bit sequence corresponding to the number of candidate antenna ports and the candidate sub-period frame head index can be obtained.

Step S330, determining a start position (hereinafter referred to as start position k 0) of the first bit sequence in the virtual circular buffer according to the candidate sub-period frame header index.

In this embodiment, according to the rate matching process of the transmitting device, the start position k0 of the 1 st, 4 th and 7 th 200 bits of data in the virtual circular buffer is 1, the start position k0 of the 2 nd, 5 th and 8 th 200 bits of data in the virtual circular buffer is 65, and the start position k0 of the 3 rd and 6 th 200 bits of data in the virtual circular buffer is 129. Thereby, the starting position of the first bit sequence in the virtual circular buffer can be determined from the candidate sub-period frame header index X.

Further, the relationship between the candidate sub-period frame header index X and the start position k0 of the first bit sequence in the virtual circular buffer is shown in fig. 11. Determining the starting position of the first bit sequence in the virtual circular buffer according to the candidate sub-period frame head index comprises:

the starting position is 1 in response to the candidate sub-period frame header index being 1 or 4 or 7.

The starting position is 65 in response to the candidate sub-period frame header index being 2 or 5 or 8.

Step S340, performing de-rate matching on the first bit sequence according to the starting position to obtain a second bit sequence.

In this embodiment, for each 200 bits, the second bit sequence is obtained by performing rate de-matching according to the above determined start position. As shown in fig. 12, the method comprises the following steps:

step S341, adding the data in the second bit sequence to a plurality of data bits in the virtual circular buffer in sequence according to the start position.

In this embodiment, the transmitting device acquires a virtual circular buffer, and sequentially adds the data in the second bit sequence to a plurality of data bits in the virtual circular buffer. Specifically, the step of obtaining the virtual buffer may refer to step S232 described above, and will not be described herein.

Further, the determined starting position is k0, and the second bit sequence (200 bits) obtained above is filled from the k0 th data bit of 192 data bits in the virtual circular buffer.

Specifically, the first bit in the second bit sequence is selected, the kth 0 (k0=1, 65, 129) data bit in the virtual circular buffer is selected, whether the data bit is a valid bit is determined, if the data bit is a valid bit, the selected bit is filled into the data bit, if the data bit is not a valid bit, the next data bit in the virtual circular buffer is selected, and the determination is continued. If the currently processed data bit is the last data bit in 192, the first data bit is returned at the next processing. The above steps are repeated until 200bit data is fully added to 192 data bits.

Further, for each data bit, if multiple bits of data are received, the multiple bits of data are combined. Thereby, 192bit data can be obtained.

Step S342, splitting the data in the virtual circular buffer.

Specifically, 1-64 bits of data in 192 bits of data are fetched to generate a 64bit sequence, denoted v11, v12, v13, … …, v1m, where m=64. The 65-128 bit data is fetched to generate a 64bit sequence denoted v21, v22, v23, … …, v2m, where m=64. The 129-192 bits of data are fetched to produce a 64bit sequence denoted v31, v32, v33, … …, v3m, where m=64. Thus, 3×64bit data can be obtained.

Step S343, performing sub-block de-interleaving on the split data to obtain the second bit sequence.

In this embodiment, the corresponding second bit sequence is obtained according to the obtained 3×64bit data through sub-block deinterleaving.

Further, for each 64bit data obtained above, it is added to the matrix of 2×32 column by column in the order from left to right. And performing inter-column inverse substitution to obtain an original matrix through the inverse process of the step S1134, reading out data in the original matrix row by row from the 0 th row and the 0 th column of the matrix, and removing the first 14 virtual bits to generate 50-bit data. Thus, for 3×64bit data, the second bit sequence obtained by sub-block deinterleaving is 3×50bit.

Further, for the 16 200 bits obtained after descrambling in the step S330, 16 3×50 bits are obtained after rate-de-matching.

In the embodiment of the invention, the descrambled data is directly subjected to rate de-matching, the buffer memory for rate de-matching is 16 x 3 x 50bit, and compared with the 16 x 1600bit data buffered before rate de-matching in the prior art, the occupied buffer memory is 9/32 of the prior art.

And step S350, decoding the second bit sequence to obtain a corresponding third bit sequence.

In this embodiment, decoding processing is performed on the obtained 16 3×50 bits to obtain a corresponding third bit sequence.

Further, 50bit data before tail biting convolution coding with constraint length of 7 and code rate of 1/3, namely a third bit sequence, are obtained for each data with 3 x 50bit through a decoding algorithm. The idea of decoding is to find maximum likelihood decoding based on the received sequence. Initializing a state register, a state transition register and a path register, circulating each state after the initial state, calculating the hamming distance between the state and the two previous possible states, comparing and selecting a path with a smaller hamming distance until a path with the maximum probability value is found, and backtracking the path transition to generate decoding data.

And step S360, checking the third bit sequence to obtain a checking result.

In this embodiment, the above-obtained 16 third bit sequences are checked respectively to obtain a check result.

Further, the 50bit data of the third bit sequence contains 34bit MIB-NB data and 16bit CRC check data, and the 16bit check bit is scrambled by different scrambling sequences. Firstly, according to the number of the antenna ports assumed before, different scrambling codes are selected, and descrambling operation is carried out on CRC check bits. Specifically, for 8 cases where the number of the assumed antenna ports is 1, the scrambling sequence of all 0 in fig. 3 is selected for the descrambling process; for 8 cases where the number of assumed antenna ports is 2, the scrambling sequence of all 1 in fig. 3 is selected for the descrambling process. The descrambled 16-bit CRC data is then used to determine if the data was decoded correctly.

Step S370, determining the number of antenna ports corresponding to the subframe signals and the subframe head index according to the checking result.

In this embodiment, the number of candidate antenna ports and the candidate subframe header index corresponding to the third bit sequence with the correct verification result are determined as the number of antenna ports and the subframe header index corresponding to the subframe signal, where the subframe header index is used to characterize the position of the subframe signal in the NPBCH period.

Thus, the number of frame heads of 80ms for which the received subframe signal is received can be determined.

Further, decoding the CRC by the third bit sequence with correct check result obtains MIB-NB information (34 bits) sent by the sending device.

Further, as can be seen from the above steps, in the embodiment of the present invention, the received 200bit data is directly subjected to rate de-matching, and only 16×3×150bit data output by rate de-matching is required to be buffered, and the calculated amount is 16×200bit. Compared with the buffer memory 16 x 1600bit and the calculated amount 16 x 1600bit required by the prior art, the buffer memory required by the embodiment of the invention is 9/32 of the prior art, and the calculated amount is 1/8 of the prior art.

Fig. 13 is a schematic structural diagram of a channel blind detection device according to an embodiment of the present invention. As shown in fig. 13, the channel blind detection apparatus according to the embodiment of the present invention includes: a receiving unit 131, a first bit sequence acquiring unit 132, a start position determining unit 133, a rate de-matching unit 134, a decoding unit 135, a checking unit 136, and a determining unit 137. Wherein, the receiving unit 131 is configured to receive at least one subframe signal transmitted in one subframe by the narrowband physical broadcast channel NPBCH. The first bit sequence obtaining unit 132 is configured to obtain a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and the candidate subframe header index. The start position determining unit 133 is configured to determine a start position of the first bit sequence according to the candidate sub-period frame header index. The de-rate matching unit 134 is configured to perform de-rate matching on the first bit sequence according to the start position to obtain a second bit sequence. The decoding unit 135 is configured to perform decoding processing on the second bit sequence to obtain a corresponding third bit sequence. The checking unit 136 is configured to check the third bit sequence to obtain a check result. The determining unit 137 is configured to determine the number of candidate antenna ports and the candidate subframe header index corresponding to the third bit sequence with the correct verification result as the number of antenna ports and the subframe header index corresponding to the subframe signal, where the subframe header index is used to characterize a position of a subframe of the subframe signal in the NPBCH period.

Further, the number of candidate antenna ports includes 1 and 2, and the candidate sub-period frame header index includes 1, 2, 3, 4, 5, 6, 7, and 8.

Further, the start position determining unit 133 includes:

a first position determining subunit, configured to respond to the candidate sub-period frame header index being 1 or 4 or 7, where the starting position is 1;

a second position determining subunit, configured to respond to the candidate sub-period frame header index being 2, or 5, or 8, and the starting position being 65; and

a third location determination subunit, configured to respond to the candidate sub-period frame header index being 3 or 6, where the starting location is 129.

Further, the rate de-matching unit 134 includes:

a data adding subunit, configured to sequentially add the data in the second bit sequence to a plurality of data bits in the virtual circular buffer according to the start position;

a splitting subunit, configured to split data in the virtual circular buffer; and

and the de-interleaving subunit is used for performing sub-block de-interleaving on the data after the splitting to obtain the second bit sequence.

Further, in response to receiving a plurality of subframe signals transmitted by the NPBCH in one subframe, the apparatus further comprises:

And the merging unit is used for merging the received plurality of subframe signals.

And receiving a subframe signal transmitted by a narrowband physical broadcast channel NPBCH in one subframe, acquiring a first bit sequence corresponding to the subframe signal under the number of candidate antenna ports and a candidate subframe head index, determining a starting position of the first bit sequence according to the candidate subframe head index, performing de-rate matching on the first bit sequence according to the starting position to acquire a second bit sequence, decoding and checking the second bit sequence to acquire a checking result, and determining the number of candidate antenna ports and the candidate subframe head index corresponding to a third bit sequence with correct checking result as the number of antenna ports and the subframe head index corresponding to the subframe signal. Therefore, the buffer memory and the calculation amount of the solution rate matching can be reduced, and the blind detection efficiency is improved.

Fig. 14 is a schematic hardware structure of a communication device according to an embodiment of the present invention. As shown in fig. 14, the communication apparatus includes: a memory 141 and a processor 142, wherein the memory 141 and the processor 142 are in communication; illustratively, the memory 141 and the processor 142 communicate via a communication bus 143, the memory 141 being adapted to store a computer program, the processor 142 executing the computer program to perform the methods shown in the above embodiments.

Optionally, the communication device may further comprise a transmitter and/or a receiver.

Alternatively, the processor may be a central processing unit (Central Processing Unit, CPU), but may also be implemented as other general purpose processor, PLC (Programmable Logic Controller ), FPGA (Field-Programmable Gate Array, field programmable gate array), DSP (Digital Signal Processor ), or ASIC (Application Specific Integrated Circuit, application specific integrated circuit). A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

The embodiment of the invention provides a storage medium for storing a computer program for implementing the channel blind detection method according to any of the above method embodiments.

The embodiment of the invention provides a chip for supporting receiving equipment (such as terminal equipment, network equipment and the like) to realize the functions shown in the embodiment of the invention, and the chip is particularly used for a chip system, wherein the chip system can be formed by the chip, and can also comprise the chip and other discrete devices. When the above method is implemented as a chip in a receiving device, the chip may further comprise a processing unit, which may be, for example, a processor, and when the chip comprises a communication unit, which may be, for example, an input/output interface, pins or circuits, etc. The processing unit executes all or part of actions executed by each processing module in the embodiment of the present invention, and the communication unit may execute corresponding receiving or transmitting actions. In another specific embodiment, the processing module of the receiving device in the embodiment of the present invention may be a processing unit of a chip, and the receiving module or the transmitting module of the control device is a communication unit of the chip.

All or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a readable memory. The program, when executed, performs steps including the method embodiments described above; and the aforementioned memory (storage medium) includes: read-only memory (ROM), RAM, flash memory, hard disk, solid state disk, magnetic tape, floppy disk, optical disk, and any combination thereof.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims and the equivalents thereof, the present invention is also intended to include such modifications and variations.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for blind detection of a channel, the method comprising:

decoding the second bit sequence to obtain a corresponding third bit sequence;

checking the third bit sequence to obtain a checking result; and

determining the number of candidate antenna ports and the candidate sub-period frame head index corresponding to the third bit sequence with correct verification result as the number of antenna ports and the sub-period frame head index corresponding to the sub-frame signal, wherein the sub-period frame head index is used for representing the position of the sub-period of the sub-frame signal in an NPBCH period;

Wherein determining the starting position of the first bit sequence according to the candidate sub-period frame header index comprises:

2. The method of claim 1, wherein the number of candidate antenna ports comprises 1 and 2, and wherein the candidate sub-period frame header index comprises 1, 2, 3, 4, 5, 6, 7, and 8.

3. The method of claim 1, wherein de-rate matching the first bit sequence according to the starting position to obtain a second bit sequence comprises:

shunting the data in the virtual circular buffer; and

4. The method of claim 1, wherein in response to receiving a plurality of subframe signals transmitted by the NPBCH in one subframe, the method further comprises:

And combining the received multiple subframe signals.

5. A channel blind detection apparatus, the apparatus comprising:

a determining unit, configured to determine, as the number of antenna ports and a sub-period frame header index corresponding to the sub-frame signal, the number of candidate antenna ports and the candidate sub-period frame header index corresponding to the third bit sequence with correct verification result, where the sub-period frame header index is used to characterize a position of a sub-period of the sub-frame signal in an NPBCH period;

Wherein the start position determining unit includes:

6. A communication device comprising a memory and a processor executing program instructions in the memory for implementing the method of any of claims 1-4.

7. A storage medium for storing a computer program for implementing the method of any one of claims 1-4.