CN102447521A - Rate de-matching method and device - Google Patents

Rate de-matching method and device Download PDF

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Publication number
CN102447521A
CN102447521A CN2010105002024A CN201010500202A CN102447521A CN 102447521 A CN102447521 A CN 102447521A CN 2010105002024 A CN2010105002024 A CN 2010105002024A CN 201010500202 A CN201010500202 A CN 201010500202A CN 102447521 A CN102447521 A CN 102447521A
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data
num
address
separate
interleaver
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CN102447521B (en
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徐翼
朱志辉
黄良明
王明耀
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Keen (Chongqing) Microelectronics Technology Co., Ltd.
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Chongqing Cyit Communication Technologies Co Ltd
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Abstract

The invention provides a rate de-matching method and device in the third mobile communication long-term evolution system. The method firstly comprises judging whether to conduct retransmission and combination; if so, writing the last de-interleaved data into a memory 3 to be de-repeated and de-punctured; if not so, directly de-repeating and de-puncturing the received data; then respectively de-interleaving the three channel data collected and sorted by de-bit, if to conduct retransmission and combination, reading data in the memory 3 to combine with the de-interleaved data of this time, writing into the memory 3 again, if not so, writing the de-interleaved data of this time into the memory 3; and providing a corresponding device. The invention omits the memory independently designated for storing de-repeated and de-punctured data, delays the retransmission and combination, shares the memory 3, eliminates a memory, reduces hardware resource, and can compute P_NUM addresses simultaneously at one time to improve the processing efficiency by P_NUM times.

Description

A kind of dissociation rate matching method and device
Technical field
The present invention relates to moving communicating field, particularly relate to a kind of 3G (Third Generation) Moblie long evolving system (being called for short 3G LTE) dissociation rate matching method and device.
Background technology
In the up link of GSM, the code multiplexing of transmission channel is handled and to be comprised that mainly CRC adds (Cyclic Redundancy Code CRC), chnnel coding, rate-matched, interweaves and step such as transmission channel is multiplexing.The data of transmission channel are unit with a transmission block.Because transmission block is changeable; And the turbo encoder has the restriction of certain limit to the length of coding code block; Therefore transmission block will carry out code block to the transmission block greater than turbo coding maximum length and cuts apart; Cut apart length and see 3GPP agreement TS36.212 table 5.1.3-3, and the head of first code block after the cutting apart dummy bit that adds right quantity satisfies code block and cut apart requirement, convolutional encoding then need not be carried out code block and cut apart;
Transmission channel coding multiplexing process process generally comprises following steps:
1, to the additional CRC of transmission block;
2, transmission block is carried out code block and cut apart, the additional CRC of each code block after cutting apart;
3, each code block is carried out chnnel coding, chnnel coding is convolutional encoding or Turbo coding, is divided into the output of 3 circuit-switched data through the data behind the coding;
4, the data after the chnnel coding are carried out rate-matched.
The amount of bits that the DPCH multipotency that the purpose of rate-matched is to make the amount of bits behind the coding to satisfy to distribute carries.The rate-matched of 3GPP agreement TS36.212 regulation comprises: sub-block interleaving, bit collection and bit are selected and are pruned, and as shown in Figure 1, sub-block interleaving is to interweave with 3 block interleavers, and the interleaver input is expressed as d respectively k (0), d k (1)And d k (2), output is expressed as V respectively k (0), V k (1)And V k (2)When the group block length does not satisfy the total length of block interleaver also needs after suitable dummy bit is added in the front of every sub-block, interweave again; Need carry out bit collection and it is merged into a data block w 3 sub-block after interweaving kAfterwards this data block is carried out bit selection and pruning; In selecting and pruning, to judge at first whether this bit is dummy bit; If just remove this dummy bit, carry out repetition (Repeated) or punching (Punctured) operation according to the physical channel bit quantity of distributing to this sub-block then.
According to 3GPP agreement TS36.2125.1.4, the algorithm that interweaves in the rate-matched comprises:
Setting
Figure BSA00000293974800021
is the matrix column number; The rectangular array sequence number is expressed as 0; 1; 2; ...,
Determine the number of rows in the matrix
Figure BSA00000293974800023
by finding the smallest integer
Figure BSA00000293974800024
met:
D ≤ ( R subblock TC × C subblock TC )
The capable sequence number of the matrix of this rectangle is expressed as 0; 1; 2; ...,
Figure BSA00000293974800026
If
Figure BSA00000293974800027
To add so Individual dummy bit is like y k=<nULL>, k=0,1 ..., N D-1.Bit sequence with input is expressed as
Figure BSA00000293974800029
k=0 so; 1; ...; D-1 writes matrix since 0 row, 0 row by row with these data:
To Turbo coding and convolutional encoding different coding mode, take different operation in interweaving:
1) encodes for Turbo
and
Figure BSA000002939748000212
Pattern
Figure BSA000002939748000213
according to table 5.1.4-1 among 3GPP TS 36.212 5.1.4 is accomplished exchange between row.Here P (j) is j original original position that is listed as by exchange.After exchange between row,
Figure BSA000002939748000214
matrix that exchanges between row etc.
The output that the output of block interleaver is listed as from exchange
Figure BSA000002939748000215
matrix one between row.Passed through table of bits is shown
Figure BSA000002939748000216
corresponding yP (0) here, corresponding
Figure BSA000002939748000219
and
Figure BSA000002939748000220
behind the sub-block interleaving
For
After a sub-block interleaved data is represented as
Figure BSA000002939748000222
Here
Figure BSA000002939748000223
and
Figure BSA000002939748000224
2) for convolutional encoding
Pattern
Figure BSA00000293974800031
according to table 5.1.4-2 among 3GPP TS 36.212 5.1.4 is accomplished exchange between row.Here P (j) is j original original position that is listed as by exchange.After exchange between row,
Figure BSA00000293974800032
matrix that exchanges between row etc.
The output that the output of block interleaver is listed as from exchange
Figure BSA00000293974800033
matrix one between row.The table of bits of having passed through behind the sub-block interleaving is shown
Figure BSA00000293974800034
Here Corresponding y P (0),
Figure BSA00000293974800036
Corresponding
Figure BSA00000293974800037
And
Figure BSA00000293974800038
In the down link of GSM, receiving terminal then need be separated rate-matched to the data that receive, and it is corresponding with the rate-matched process to separate the rate-matched process, is its inverse process.
Prior art:
One Chinese patent application numbers 200810232937.6 discloses a kind of dissociation rate matching method; Calculate the position of the dummy bit that when code block is cut apart with sub-block interleaving, adds; And then the dummy bit that adds when cutting apart code block with sub-block interleaving adds in the data of reception, at last the dummy bit data of adding separated rate-matched according to the inverse process of rate-matched.
Because convolution code is different with turbo sign indicating number coded system, the dissociation rate matching method step of existing turbo coding, as shown in Figure 2, concrete performing step is following:
Need be before carrying out step 1 according to the size of transmission block, the mode of cutting apart according to code block calculates the size of each code block and the dummy bit number of when code block is cut apart, adding; The dummy bit number of adding when calculating sub-block interleaving; The summation of when code block is cut apart with sub-block interleaving, adding dummy bit according to the big or small number of the every sub-block that calculates in the top front calculates the position of dummy bit according to the mode of sub-block interleaving and bit collection; The dummy bit that adds when cutting apart with sub-block interleaving at code block according to the position of dummy bit is inserted into to receive in the data and goes;
Separate repetition (The data to repeating abandons or union operation) or separate punching (The data of being struck off is filled up operation) process according to the amount of bits of each code block physical channel and the physical length of code block;
If situation about retransmit merging, the data that separating of present encoding piece repeated to separate data after the punching and needed to repeat to separate with separating of last this encoding block that receives punching merge, otherwise directly carry out the operation of the 4th step;
Mode according to bit collection is separated bit collection.Because this process and bit collection be inverse process each other, carries out so need code block be divided into 3 sub-block;
3 sub-block are carried out sub-piece deinterleaving respectively, remove the dummy bit that adds in the sub-block interleaving then.
The dissociation rate matching method step of existing convolution code and the dissociation rate matching method of above-mentioned turbo sign indicating number are similar basically; But because convolution code need not carried out code block and cut apart; So need not carry out the dummy bit padding of code block when cutting apart to it, also need not calculate code block cut apart in the number and the position of dummy bit.
Above method can be through realizing with lower device, and is as shown in Figure 3, comprising:
Interface module: to the visit of parameter register, data storage, and generation is interrupted seeing off when computing finishes;
Separate and repeat to separate the punching module: accomplish to separate and repeat to separate punch operation;
Retransmit and merge module: judge whether to retransmit merging, retransmit union operation;
Separate the bit collection de-interleaving block: accomplish and separate bit collection reconciliation interlace operation
Four memories are respectively:
Memory 1: be used for the data that store interface module receives, and supply to separate and repeat to separate the punching module and use;
Memory 2: be used for storing to separate repeating to separate the punching data processed, and supply to retransmit the use of merging module;
Memory 3: be used to store the last data that are used to retransmit merging;
Memory 4: be used to store dateout.
By on can know that the problem that existing implementation method of separating rate-matched or device exist is: directly adopt the formula algorithm that interweaves, can only calculate an interleaving address at every turn, thereby can only handle data at every turn, make the implementation method inefficiency; Separating the merging of carrying out data retransmission after repeating to separate punching, the data that need separately to repeat to separate for separating of the last present encoding piece that receives punching are distributed a memory separately, have strengthened memory spending.
Summary of the invention
The technical problem that the present invention solved is to provide a kind of dissociation rate matching method, is used for solving the problem that the prior art memory spending is big, treatment effeciency is low.
For overcoming the above problems, the present invention proposes a kind of dissociation rate matching method, and is as shown in Figure 4, comprising:
201, judge whether to retransmit merging.If then,, then directly carry out step 202 if do not need with the writing data into memory 3 of last deinterleaving;
202, separate and repeat to separate punching receiving data;
203, separate bit collection;
204, the data of separating behind the bit collection are carried out deinterleaving.
205, judge whether to need to retransmit to merge, if, then carry out 206, then carry out 207 if not;
206, the data behind the sub-block interleaving of separating that will separate that data and present encoding piece behind the sub-block interleaving received last time are carried out data and are merged back write memory 3, EO;
207, the writing data into memory 3 after directly will interweaving, EO.Preferably, said step 202 pair reception data are separated and repeated to separate punching is parallel work-flow, specifically comprises:
202-1: distribute P_NUM interleaver unit;
202-2: according to the address before the sub-block interleaving of INADD (address after interweaving) parallel computation of P_NUM interleaver unit;
1,, need judge k in the computing interval for the Turbo coded system nSize;
If k n＜K ∏Address before then interweaving:
Figure BSA00000293974800051
If k n>=K ∏, then judge k nOdd even;
If k nBe odd number, the address before then interweaving
Figure BSA00000293974800052
If k nBe even number, judge Whether less than K ∏If,, the address before then interweaving:
Figure BSA00000293974800054
If not, the address before then interweaving: &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
2, for the convolutional encoding mode, the address
Figure BSA00000293974800056
before then interweaving
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏], preferred value 2 u, 0≤u≤log 2K ∏K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure BSA00000293974800061
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure BSA00000293974800062
The interweave columns of submatrix of expression;
Figure BSA00000293974800063
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure BSA00000293974800064
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure BSA00000293974800065
Expression rounds downwards;
Figure BSA00000293974800066
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
202-3: judge whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position.
Preferably, said step 204 is parallel work-flow, comprising:
204-1: three circuit-switched data branch roads distribute P_NUM interleaver unit respectively;
204-2: the interweave preceding address corresponding according to INADD (address after the interweaving) parallel computation of P_NUM interleaver;
The Turbo coded system:
For system data, the address before then interweaving:
For first via checking data, the address before then interweaving:
Figure BSA00000293974800068
For the second road checking data, judge
Figure BSA00000293974800069
Whether less than K ∏If,, the address before then interweaving:
Figure BSA000002939748000610
If not, the address before then interweaving: &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
Convolutional encoding mode, the then preceding address that interweaves of three circuit-switched data
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏], preferred value 2 u, 0≤u≤log 2K ∏K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure BSA00000293974800072
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure BSA00000293974800073
The interweave columns of submatrix of expression;
Figure BSA00000293974800074
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure BSA00000293974800075
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure BSA00000293974800076
Expression rounds downwards; Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
204-3: three circuit-switched data are carried out the parallel deinterleaving operation in P_NUM road according to the address of calculating respectively;
For overcoming the above problems, the present invention also provides a kind of rate-matched device of separating, and comprising:
Interface module: this module is accomplished outside visit to parameter register, data storage, and generation is interrupted seeing off when computing finishes;
Separate and repeat to separate the punching module: accomplish to separate and repeat to separate punch operation; With the address spaces that receives data is the preceding address of sub-block interleaving, judges whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position;
Separate the bit collection de-interleaving block: accomplish and separate bit collection reconciliation interlace operation, be divided into three data branch roads, and carry out the deinterleaving operation respectively;
Retransmit and merge module: judge whether to retransmit merging; Merge if need to retransmit,, when this deinterleaving is carried out, it is read writing data into memory 3 after the last deinterleaving; Merge with data behind the sub-block interleaving of separating of this reception, will merge back writing data into memory 3;
Three memories, storage is used for storing respectively the input and output data of above-mentioned module respectively, is specially:
Memory 1 is used for the data that store interface module receives, and supplies to separate and repeat to separate the punching module and use;
Memory 2 is used for storing to separate repeating to separate the punching data processed, and supplies to separate the use of bit collection de-interleaving block;
Memory 3 is used to store the data after the last deinterleaving, supplies to retransmit to merge module and use, and stores this and retransmits merging data as dateout.
Preferably, said separating repeated to separate punching module Parallel Implementation and separated and repeat to separate punch operation, the data that repeat adopted abandon or union operation, and the data of punching are taked to fill up operation;
Preferably, separate the bit collection de-interleaving block: realize separating the bit collection operation, be divided into three circuit-switched data with separating the data that repeat to separate after the punching, Parallel Implementation deinterleaving operation reverts to the order before the coding with the data of separating bit collection;
Existing dissociation rate matching method is employed in to separate and repeats to separate the merging of carrying out data retransmission after the punching; It need repeat to separate memory of the independent distribution of data of punching for separating of the last present encoding piece that receives separately, strengthens the memory spending of this implementation method.To divide separately among the present invention to be used in storage and to separate the memory deletion that repeats to separate punctured data, and will retransmit merging and delay and carry out, and promptly use the data after the deinterleaving to retransmit merging; Make that memory 3 is shared; Thereby saved a block storage, reduced hardware resource, reduced hardware area.
Description of drawings
Fig. 1 is a prior art rate-matched structure chart;
Fig. 2 is a prior art rate-matched flow chart;
Fig. 3 separates the rate-matched structure drawing of device for prior art;
Fig. 4 is invention dissociation rate matching method flow chart;
Fig. 5 separates the rate-matched structure drawing of device for invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer; Below in conjunction with accompanying drawing and execution mode; A kind of dissociation rate matching method of the present invention and device are done further explain, and known implementation no longer details, to avoid there be unnecessary obscuring with content of the present invention.
The present invention provides a kind of dissociation rate matching method, and is as shown in Figure 4, comprising:
201, judge whether to retransmit merging.If then,, then directly carry out step 202 if do not need with the writing data into memory 3 of last deinterleaving;
202, separate and repeat to separate punching receiving data;
203, separate bit collection;
204, the data of separating behind the bit collection are carried out deinterleaving.
205, judge whether to need to retransmit to merge, if, then carry out 206, then carry out 207 if not;
206, the data behind the sub-block interleaving of separating that will separate that data and present encoding piece behind the sub-block interleaving received last time are carried out data and are merged back write memory 3, EO;
207, the writing data into memory 3 after directly will interweaving, EO.
At first judge whether to retransmit merging; If then the writing data into memory 3 of last deinterleaving is separated again and repeated to separate punching, otherwise directly separate and repeat to separate punching receiving data, the address spaces that is about to receive data is the preceding address of sub-block interleaving; Judge whether the preceding address of sub-block interleaving is the dummy bit data; If just insert zero, otherwise, fill the reception data in this position; Secondly separate bit collection to separating the data that repeat to separate punching, its extraction is divided into three circuit-switched data, be respectively one road system data, the two-way checking data according to its distinctive data array; Respectively three circuit-switched data are carried out deinterleaving at last, during this period if need retransmit union operation, the data of then data in the memory 3 being read with this deinterleaving merge; It is reduced to the data before the sub-block interleaving; And write memory 3 once more, EO is not if need; Then in the writing data into memory 3 with this deinterleaving, EO.Among the present invention, the data that retransmit merging are dateouts, i.e. data after the deinterleaving; And in the prior art, the data that retransmit merging are intermediate data, promptly separate the data that repeat to separate after the punching; This makes that common storage 3 has been saved a block storage under the prerequisite that realizes function; Reduce hardware resource, reduced hardware area.
Further, before step 201, learn following data:
1) the big or small B of each code block;
2) calculate the number F that adds dummy bit when code block is cut apart;
The number Nd of the dummy bit that 3) adds during sub-block interleaving and the big or small Ncb of virtual circular buffer;
4) separate the input data length E of override interrupt and separate the original position k that repeats to separate punching 0
5) writing data into memory 1 that will handle.
Said step 202 pair reception data are separated and repeated to separate punching is based on the prior art serial operation; The address that is about to receive data is converted into the preceding address of sub-block interleaving one by one, judges whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero; Otherwise, fill the reception data in this position;
Preferably, said step 202 pair reception data are separated and repeated to separate punching is parallel work-flow, specifically comprises:
202-1: distribute P_NUM interleaver unit;
202-2: according to the address before the sub-block interleaving of INADD (address after interweaving) parallel computation of P_NUM interleaver unit;
For the Turbo coded system, need judge k in the computing interval nSize;
If k n＜K ∏Address before then interweaving
Figure BSA00000293974800101
If k n>=K ∏, then judge k nOdd even;
If k nBe odd number, the address before then interweaving
Figure BSA00000293974800102
If k nBe even number, judge
Figure BSA00000293974800103
Whether less than K ∏If,, the address before then interweaving
Figure BSA00000293974800104
If not, the address before then interweaving &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
For the convolutional encoding mode, the address
Figure BSA00000293974800106
before then interweaving
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏], preferred value 2 u, 0≤u≤log 2K ∏K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure BSA00000293974800111
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure BSA00000293974800112
The interweave columns of submatrix of expression;
Figure BSA00000293974800113
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure BSA00000293974800114
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure BSA00000293974800115
Expression rounds downwards;
Figure BSA00000293974800116
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
202-3: judge whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position.
Present embodiment can be calculated P_NUM address at every turn simultaneously, and with respect to can only calculate an address in the prior art at every turn, treatment effeciency has improved P_NUM doubly, has solved the slow shortcoming of processing speed in the prior art.
Further, said step 203 is divided into 3 data branch roads with separating the result data that repeats to separate punching, comprises the steps:
203-1: K before will separating in the result data that repeats to separate punching ∏Individual data are extracted out as system data;
203-2: different according to coded system, take different disposal; Promptly for the situation of Turbo coding, the data cross arrangement successively of verification one and verification two is pressed rule respectively with its extraction; For the situation of convolutional encoding, the data of verification one and verification two are pressed rule respectively with its extraction by the data block sequence arrangement;
The data that said step 204 pair is separated behind the bit collection are carried out deinterleaving for according to prior art three data branch roads are carried out serial operation respectively;
Preferably, said step 204 is parallel work-flow, comprising:
204-1: three circuit-switched data branch roads distribute P_NUM interleaver unit respectively;
204-2: the interweave preceding address corresponding according to INADD (address after the interweaving) parallel computation of P_NUM interleaver;
The Turbo coded system,
For system data, the address before then interweaving
For first via checking data, the address
Figure BSA00000293974800122
before then interweaving
For the second road checking data, judge
Figure BSA00000293974800123
Whether less than K ∏If,, the address before then interweaving:
Figure BSA00000293974800124
If not, the address before then interweaving: &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
Convolutional encoding mode, the then preceding address
Figure BSA00000293974800126
that interweaves of three circuit-switched data
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏], preferred value 2 u, 0≤u≤log 2K ∏K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure BSA00000293974800127
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure BSA00000293974800128
The interweave columns of submatrix of expression;
Figure BSA00000293974800129
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure BSA000002939748001210
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure BSA000002939748001211
Expression rounds downwards;
Figure BSA000002939748001212
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
204-3: three circuit-switched data are carried out the parallel deinterleaving operation in P_NUM road according to the address of calculating respectively;
Present embodiment can be calculated P_NUM address at every turn simultaneously, and with respect to can only calculate an address in the prior art at every turn, treatment effeciency has improved P_NUM doubly, has solved the slow shortcoming of processing speed in the prior art.
The present invention provides a kind of rate-matched device of separating, and is as shown in Figure 5, comprising:
Interface module: this module is accomplished outside visit to parameter register, data storage, and generation is interrupted seeing off when computing finishes;
Separate and repeat to separate the punching module: accomplish to separate and repeat to separate punch operation; With the address spaces that receives data is the preceding address of sub-block interleaving, judges whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position;
Separate the bit collection de-interleaving block: accomplish and separate bit collection reconciliation interlace operation, be divided into three data branch roads, and carry out the deinterleaving operation respectively;
Retransmit and merge module: judge whether to retransmit merging; Merge if need to retransmit,, when this deinterleaving is carried out, it is read writing data into memory 3 after the last deinterleaving; Merge with data behind the sub-block interleaving of separating of this reception, will merge back writing data into memory 3;
Three memories, storage is used for storing respectively the input and output data of above-mentioned module respectively, is specially:
Memory 1 is used for the data that store interface module receives, and supplies to separate and repeat to separate the punching module and use;
Memory 2 is used for storing to separate repeating to separate the punching data processed, and supplies to separate the use of bit collection de-interleaving block;
Memory 3 is used to store the data after the last deinterleaving, supplies to retransmit to merge module and use, and stores this and retransmits merging data as dateout.
This device is used in storage and separates the memory of data deletion that repeats to separate punching will dividing separately, and will retransmit to merge to delay and carry out, and makes under the prerequisite of realization function; Common storage 3; Save a block storage, reduced hardware resource, reduced hardware area.
Preferably, said separating repeated to separate punching module Parallel Implementation and separated and repeat to separate punch operation, the data that repeat adopted abandon or union operation, and the data of punching are taked to fill up operation;
Said parallel separating repeats to separate punch operation, comprising:
202-1: distribute P_NUM interleaver unit;
202-2: according to the address before the sub-block interleaving of INADD (address after interweaving) parallel computation of P_NUM interleaver unit;
For the Turbo coded system, need judge k in the computing interval nSize;
If k n＜K ∏Address before then interweaving:
If k n>=K ∏, then judge k nOdd even;
If k nBe odd number, the address before then interweaving
Figure BSA00000293974800142
If k nBe even number, judge
Figure BSA00000293974800143
Whether less than K ∏If,, the address before then interweaving:
Figure BSA00000293974800144
If not, the address before then interweaving: &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
For the convolutional encoding mode, the address before then interweaving:
Figure BSA00000293974800146
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏], preferred value 2 u, 0≤u≤log 2K ∏K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure BSA00000293974800147
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving; The interweave columns of submatrix of expression;
Figure BSA00000293974800149
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure BSA000002939748001410
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure BSA000002939748001411
Expression rounds downwards;
Figure BSA000002939748001412
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
202-3: judge whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position.
Preferably; Separate the bit collection de-interleaving block: realize separating the bit collection operation; Be divided into three circuit-switched data (being respectively one road system data, the two-way checking data) Parallel Implementation deinterleaving operation with separating the data that repeat to separate after the punching, the data of separating bit collection are reverted to the order before the coding;
Said parallel deinterleaving operation comprises:
204-1: three circuit-switched data branch roads distribute P_NUM interleaver unit respectively;
204-2: the interweave preceding address corresponding according to INADD (address after the interweaving) parallel computation of P_NUM interleaver;
The Turbo coded system:
For system data, the address
Figure BSA00000293974800151
before then interweaving
For first via checking data, the address
Figure BSA00000293974800152
before then interweaving
For the second road checking data, judge Whether less than K ∏If,, the address before then interweaving: If not, the address before then interweaving: &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
Convolutional encoding mode, the then preceding address
Figure BSA00000293974800156
that interweaves of three circuit-switched data
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏], preferred value 2 u, 0≤u≤log 2K ∏K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure BSA00000293974800161
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure BSA00000293974800162
The interweave columns of submatrix of expression;
Figure BSA00000293974800163
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure BSA00000293974800164
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure BSA00000293974800165
Expression rounds downwards;
Figure BSA00000293974800166
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
204-3: three circuit-switched data are carried out the parallel deinterleaving operation in P_NUM road according to the address of calculating respectively.
This device can calculate P_NUM address at every turn simultaneously, and with respect to can only calculate an address in the prior art at every turn, treatment effeciency has improved P_NUM doubly, has solved the slow shortcoming of processing speed in the prior art.
Execution mode that the present invention lifts or embodiment have carried out further detailed description to the object of the invention, technical scheme and advantage; Institute is understood that; Abovely lift execution mode or embodiment is merely preferred implementation of the present invention; Not in order to restriction the present invention, all within spirit of the present invention and principle to any modification that the present invention did, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. a dissociation rate matching method is characterized in that, comprising:
201, judge whether to retransmit merging, if then,, then directly carry out step 202 if do not need with the writing data into memory 3 of last deinterleaving;
202, separate and repeat to separate punching receiving data;
203, separate bit collection;
204, the data of separating behind the bit collection are carried out deinterleaving;
205, judge whether to need to retransmit to merge, if, then carry out 206, then carry out 207 if not;
206, the data behind the sub-block interleaving of separating that will separate that data and present encoding piece behind the sub-block interleaving received last time are carried out data and are merged back write memory 3, EO;
207, the writing data into memory 3 after directly will interweaving, EO.
2. dissociation rate matching method according to claim 1 is characterized in that, said step 202 pair receives data and separates and repeat to separate punching and be parallel work-flow, comprising:
202-1: distribute P_NUM interleaver unit;
202-2: according to the address before the sub-block interleaving of INADD (address after interweaving) parallel computation of P_NUM interleaver unit;
For the Turbo coded system, need judge k in the computing interval nSize;
If k n＜K ∏Address before then interweaving
If k n>=K ∏, then judge k nOdd even;
If k nBe odd number, the address before then interweaving
Figure FSA00000293974700012
If k nBe even number, judge
Figure FSA00000293974700013
Whether less than K ∏If,, the address before then interweaving
Figure FSA00000293974700014
Otherwise, the address before interweaving &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
For the convolutional encoding mode, the address
Figure FSA00000293974700016
before then interweaving
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏]; K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ...,
Figure FSA00000293974700021
k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure FSA00000293974700022
The interweave columns of submatrix of expression; The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively:
Figure FSA00000293974700024
Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure FSA00000293974700025
Expression rounds downwards;
Figure FSA00000293974700026
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
202-3: judge whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position.
3. dissociation rate matching method according to claim 1 is characterized in that said step 204 is parallel work-flow, comprising:
204-1: three circuit-switched data branch roads distribute P_NUM interleaver unit respectively;
204-2: the interweave preceding address corresponding according to INADD (address after the interweaving) parallel computation of P_NUM interleaver;
If Turbo coded system:
For system data, the address before then interweaving:
Figure FSA00000293974700027
For first via checking data, the address before then interweaving:
Figure FSA00000293974700028
For the second road checking data, judge
Figure FSA00000293974700029
Whether less than K ∏If,, the address before then interweaving:
Figure FSA00000293974700031
If not, the address before then interweaving: &pi; ( k n ) = P ( p 1 ( k n ) ) + C Subblock TC &times; p 2 ( k n ) + 1 - K &Pi; ;
If convolutional encoding mode, the then preceding address
Figure FSA00000293974700033
that interweaves of three circuit-switched data
For the 1st interleaver: k n=k 0+ n * P_NUM
For the 2nd interleaver: k n=k 0+ 1+n * P_NUM
For the 3rd interleaver: k n=k 0+ 2+n * P_NUM
......
For P_NUM interleaver: k n=k 0+ P_NUM-1+n * P_NUM
Wherein, P_NUM representes the number of parallel interleaver, its value for [1, K ∏]; K ∏The interweave size of submatrix of expression; N representes the address after the n time parallel computation P_NUM interleaver interweaves, and span is 0,1 ..., k nAddress after expression interweaves is an increment with P_NUM; π (k n) the address k of expression after interweaving nThe address of the input data before corresponding interweaving;
Figure FSA00000293974700035
The interweave columns of submatrix of expression;
Figure FSA00000293974700036
The interweave line number of submatrix of expression; p 1(k n) and p 2(k n) be k nFunction, its value is respectively: Be illustrated in the sub-interleaver matrix integer line numbers all before the k position,
Figure FSA00000293974700038
Expression rounds downwards;
Figure FSA00000293974700039
Be illustrated in the columns at place, k position in the sub-interleaver matrix, mod representes the complementation computing; P (p 1(k)) represent with interweave after row sequence number p 1(k) the original row sequence number of correspondence;
204-3: three circuit-switched data are carried out the parallel deinterleaving operation in P_NUM road according to the address of calculating respectively.
4. separate the rate-matched device for one kind, comprising:
Interface module: this module is accomplished outside visit to parameter register, data storage, and generation is interrupted seeing off when computing finishes;
Separate and repeat to separate the punching module: accomplish to separate and repeat to separate punch operation; With the address spaces that receives data is the preceding address of sub-block interleaving, judges whether the preceding address of sub-block interleaving is the dummy bit data, if just insert zero, otherwise, fill the reception data in this position;
Separate the bit collection de-interleaving block: accomplish and separate bit collection reconciliation interlace operation, be divided into three data branch roads, and carry out the deinterleaving operation respectively;
Retransmit and merge module: judge whether to retransmit merging; Merge if need to retransmit,, when this deinterleaving is carried out, it is read writing data into memory 3 after the last deinterleaving; Merge with data behind the sub-block interleaving of separating of this reception, will merge back writing data into memory 3;
Three memories, storage is used for storing respectively the input and output data of above-mentioned module respectively, is specially:
Memory 1 is used for the data that store interface module receives, and supplies to separate and repeat to separate the punching module and use;
Memory 2 is used for storing to separate repeating to separate the punching data processed, and supplies to separate the use of bit collection de-interleaving block;
Memory 3 is used to store the data after the last deinterleaving, supplies to retransmit to merge module and use, and stores this and retransmits merging data as dateout.
5. like the said rate-matched device of separating of claim 4, it is characterized in that said separating repeats to separate the punching module: Parallel Implementation is separated and is repeated to separate punch operation, the data that repeat is adopted abandon or union operation, and the data of punching are taked to fill up operation.
6. like the said rate-matched device of separating of claim 4; It is characterized in that; The said bit collection de-interleaving block of separating: realize separating the bit collection operation; Be divided into three circuit-switched data with separating the data that repeat to separate after the punching, Parallel Implementation deinterleaving operation reverts to the order before the coding with the data of separating bit collection.
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