CN113300808A - Rate de-matching method and device, electronic equipment and storage medium - Google Patents
Rate de-matching method and device, electronic equipment and storage medium Download PDFInfo
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- CN113300808A CN113300808A CN202010112683.5A CN202010112683A CN113300808A CN 113300808 A CN113300808 A CN 113300808A CN 202010112683 A CN202010112683 A CN 202010112683A CN 113300808 A CN113300808 A CN 113300808A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0009—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the channel coding
- H04L1/0013—Rate matching, e.g. puncturing or repetition of code symbols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
Abstract
The embodiment of the invention discloses a method and a device for de-rate matching, electronic equipment and a storage medium, wherein the de-rate matching comprises the following steps: determining the number of sample points of data to be decoded and acquiring preset parameters, and determining a decoding bit selection address based on the number of sample points of the data to be decoded and the preset parameters; determining a bit decoding interleaving address of the data to be decoded based on the bit decoding selection address and the dimension of the data to be decoded; and determining a de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded so as to perform de-rate matching based on the de-rate address. The invention can effectively save the storage space of the cache de-rate address and reduce the storage overhead, thereby effectively improving the matching efficiency of the de-rate matching.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a rate de-matching method, a rate de-matching device, electronic equipment and a storage medium.
Background
In a mobile communication system, data which is not decoded (e.g. Polar codes are decoded) is usually subjected to rate matching and de-rate matching, so as to improve reliability of data transmission and ensure quality of communication.
At this stage, after rate matching is performed on the uncoded data (the uncoded data after rate matching may be referred to as data to be decoded), rate matching is typically performed on the data to be decoded again. Specifically, first, a pre-generated rate de-matching table may be obtained, where the rate de-matching table includes a correspondence relationship between all rate de-addresses and address differences between the start data of two same rows in the data to be decoded. Then, according to the address difference between the start data of the same two rows in the data to be decoded, the real address corresponding to the data to be decoded, that is, the de-rate address, may be queried in the de-rate matching graph. Then, rate de-matching can be performed based on the rate de-matching address, so that the bit rate of transmission of the transmission channel is consistent with the carrying capacity of the physical channel, and the reliability of data transmission and the communication quality are ensured.
In the prior art, a de-rate matching chart needs to be generated and stored in advance, so that the storage of the de-rate matching chart needs to occupy more storage space, thereby increasing the storage resource consumption of a system and influencing the matching efficiency of the de-rate matching.
Disclosure of Invention
Because the existing method can increase the storage resource consumption of the system and influence the matching efficiency of rate de-matching, the embodiment of the invention provides a rate de-matching method, a rate de-matching device, electronic equipment and a storage medium.
In a first aspect, an embodiment of the present invention provides a method for rate de-matching, including:
determining the number of sample points of data to be decoded and acquiring preset parameters, and determining a decoding bit selection address based on the number of sample points of the data to be decoded and the preset parameters;
determining a bit decoding interleaving address of the data to be decoded based on the bit decoding selection address and the dimension of the data to be decoded;
and determining a de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded so as to perform de-rate matching based on the de-rate address.
Optionally, the preset parameters include a starting line number, a current sample number, a data difference between adjacent lines, and a data step.
Optionally, the determining a decoding bit selection address based on the number of samples of the data to be decoded and the preset parameter includes:
determining the current data stepping based on the number of the current sample points and the data difference value between the adjacent lines, acquiring a preset row and column value, and determining the actual difference value between the preset row and column value and the initial row number;
judging whether the number of current samples is larger than that of the data to be decoded or whether the stepping of the current data is larger than the actual difference value plus one;
and if so, determining the current sampling point number as a solution bit selection address.
Optionally, the determining a bit decoding interleaving address of the data to be decoded based on the bit decoding selection address and the dimension of the data to be decoded includes:
and determining the modulus of the bit decoding selection address based on the dimension of the data to be decoded, and determining the modulus of the bit decoding selection address as a bit decoding interleaving address of the data to be decoded.
Optionally, the determining a de-rate address of the data to be decoded based on the de-bit interleaving address and the dimension of the data to be decoded includes:
determining a weighted value corresponding to the dimensionality based on the dimensionality of the data to be decoded, and determining an intermediate parameter corresponding to the data to be decoded based on the numerical value of the bit decoding interleaving address and the weighted value;
and determining a decoding parameter corresponding to the intermediate parameter based on a preset parameter comparison table, and determining a de-rate address of the data to be decoded based on the decoding parameter, the weighted value and a modulus of the de-bit interleaving address.
Optionally, the formula for determining the intermediate parameter corresponding to the data to be decoded based on the dimension of the data to be decoded and the value of the bit interleaving address is as follows:
i＝floor(addr1/m)
wherein i represents the intermediate parameter, floor represents rounding-down, addr1 represents the value of the bit interleaving address, and m represents the weighted value corresponding to the intermediate parameter;
the formula for determining the de-rate address of the data to be decoded based on the decoding parameters, the weighted values and the modulus of the de-bit interleaving address is as follows:
addr2＝p(i)*m+addr1％m
where addr2 represents the decode rate address, p (i) represents the decode parameters, and addr 1% m represents the modulus of addr 1.
In a second aspect, an embodiment of the present invention further provides a de-rate matching apparatus, including a selective address determining module, an interleaving address determining module, and a de-rate matching module, where:
the selection address determining module is used for determining the number of sample points of the data to be decoded and acquiring a preset parameter, and determining a decoding bit selection address based on the number of sample points of the data to be decoded and the preset parameter;
the interleaving address determining module is used for determining a bit-decoding interleaving address of the data to be decoded based on the bit-decoding selection address and the dimension of the data to be decoded;
and the de-rate matching module is used for determining a de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded so as to perform de-rate matching based on the de-rate address.
Optionally, the preset parameters include a starting line number, a current sample number, a data difference between adjacent lines, and a data step.
Optionally, the select address determining module is configured to:
determining the current data stepping based on the number of the current sample points and the data difference value between the adjacent lines, acquiring a preset row and column value, and determining the actual difference value between the preset row and column value and the initial row number;
judging whether the number of current samples is larger than that of the data to be decoded or whether the stepping of the current data is larger than the actual difference value plus one;
and if so, determining the current sampling point number as a solution bit selection address.
Optionally, the interleaving address determining module is configured to:
and determining the modulus of the bit decoding selection address based on the dimension of the data to be decoded, and determining the modulus of the bit decoding selection address as a bit decoding interleaving address of the data to be decoded.
Optionally, the rate de-matching module is configured to:
determining a weighted value corresponding to the dimensionality based on the dimensionality of the data to be decoded, and determining an intermediate parameter corresponding to the data to be decoded based on the numerical value of the bit decoding interleaving address and the weighted value;
and determining a decoding parameter corresponding to the intermediate parameter based on a preset parameter comparison table, and determining a de-rate address of the data to be decoded based on the decoding parameter, the weighted value and a modulus of the de-bit interleaving address.
Optionally, the formula for determining the intermediate parameter corresponding to the data to be decoded based on the dimension of the data to be decoded and the value of the bit interleaving address is as follows:
i＝floor(addr1/m)
wherein i represents the intermediate parameter, floor represents rounding-down, addr1 represents the value of the bit interleaving address, and m represents the weighted value corresponding to the intermediate parameter;
the formula for determining the de-rate address of the data to be decoded based on the decoding parameters, the weighted values and the modulus of the de-bit interleaving address is as follows:
addr2＝p(i)*m+addr1％m
where addr2 represents the decode rate address, p (i) represents the decode parameters, and addr 1% m represents the modulus of addr 1.
In a third aspect, an embodiment of the present invention further provides an electronic device, including:
at least one processor; and
at least one memory communicatively coupled to the processor, wherein:
the memory stores program instructions executable by the processor, which when called by the processor are capable of performing the above-described methods.
In a fourth aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium storing a computer program, which causes the computer to execute the above method.
According to the technical scheme, the bit decoding selection address is determined based on the number of the sample points of the data to be decoded and the preset parameters, the bit decoding interleaving address of the data to be decoded is determined based on the bit decoding selection address and the dimension, and the rate decoding matching is performed based on the dimension rate decoding matching address of the bit decoding interleaving address so as to perform rate decoding matching based on the rate decoding address. Therefore, the bit decoding selection address, the bit decoding interleaving address and the rate decoding address corresponding to the data to be decoded are calculated in real time according to a pipeline mode, the rate decoding address does not need to be stored, the storage space for caching the rate decoding address can be effectively saved, the storage cost is reduced, and the matching efficiency of rate decoding matching can be effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for de-rate matching according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a de-rate matching apparatus according to an embodiment of the present invention;
fig. 3 is a logic block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Fig. 1 shows a flowchart of a rate de-matching method provided in this embodiment, which includes:
s101, determining the number of sample points of the data to be decoded and acquiring preset parameters, and determining a decoding bit selection address based on the number of sample points of the data to be decoded and the preset parameters.
The preset parameters at least include a starting line number of the data to be decoded, a number of samples of the data to be decoded (i.e., a current number of samples), a data difference between adjacent lines between any two lines of data in the data to be decoded (hereinafter, referred to as a line space difference), and a data step.
The decoding bit selection address refers to an address for decoding bit selection of data to be decoded.
In implementation, rate de-matching may be performed on the data to be decoded based on the number of samples and the dimension of the data to be decoded and the preset parameter. Specifically, first, the number of sample points of the data to be decoded (i.e., the number of data to be decoded) may be determined, and preset parameters may be obtained, where the preset parameters may include at least a starting line number of the data to be decoded, the number of sample points of the data to be decoded (i.e., a current number of sample points), a line interval difference between any two lines of data in the data to be decoded, and a data step (i.e., a difference between 2 adjacent rate matching addresses). Then, an address for performing bit decoding selection on the data to be decoded, that is, a bit decoding selection address, may be determined based on the number of samples of the data to be decoded and the preset parameter.
S102, based on the dimension of the bit decoding selection address and the data to be decoded, the bit decoding interleaving address of the data to be decoded is determined.
In an implementation, after determining the decoding bit selection address, the dimensions of the data to be decoded may be determined. Then, the bit decoding interleaving address of the data to be decoded can be determined according to the dimension of the data to be decoded and the bit decoding selection address of the data to be decoded. The dimension of the data to be decoded can be determined according to the bit number of the data to be decoded. Taking the bit number of the data to be decoded as 1024 as an example, 1024 is a power of ten of 2, so the dimension of the data to be decoded is 10. Referring to table 1, different dimensions corresponding to data to be decoded with different bit numbers are shown.
TABLE 1
| Number of bits | 1024 | 512 | 256 | 128 | 64 | 32 | 16 |
| Dimension (d) of | 10 | 9 | 8 | 7 | 6 | 5 | 4 |
S103, determining a de-rate address of the data to be decoded based on the de-bit interleaving address and the dimensionality of the data to be decoded, and performing de-rate matching based on the de-rate address.
In implementation, after determining the bit interleaving address of the data to be decoded, the de-rate address of the data to be decoded (i.e., the written rate matching address corresponding to the data to be decoded) may be determined based on the bit interleaving address of the data to be decoded and the dimension of the data to be decoded, so as to perform rate de-matching on the data to be decoded based on the de-rate address, so that the bit rate of transmission of a transmission channel is consistent with the carrying capacity of a physical channel, and the reliability of data transmission and the communication quality are ensured.
According to the technical scheme, the bit decoding selection address is determined based on the number of the sample points of the data to be decoded and the preset parameters, the bit decoding interleaving address of the data to be decoded is determined based on the bit decoding selection address and the dimension, and the rate decoding matching is performed based on the dimension rate decoding matching address of the bit decoding interleaving address so as to perform rate decoding matching based on the rate decoding address. Therefore, the bit decoding selection address, the bit decoding interleaving address and the rate decoding address corresponding to the data to be decoded are calculated in real time according to a pipeline mode, the rate decoding address does not need to be stored, the storage space for caching the rate decoding address can be effectively saved, the storage cost is reduced, and the matching efficiency of rate decoding matching can be effectively improved.
Further, on the basis of the above method embodiment, when the number of current sampling points is greater than the number of sampling points of the data to be decoded, or when the current data step is greater than the actual difference plus one, the starting line number may be determined as the solution bit selection address, and the corresponding processing of step S101 may be as follows: determining the current data stepping based on the number of current samples and the data difference value between adjacent lines, acquiring a preset row and column value, and determining the actual difference value between the preset row and column value and the initial row number; judging whether the number of current sample points is larger than that of the data to be decoded or whether the current data stepping is larger than the actual difference value plus one; and if so, determining the current sampling point number as the solution bit selection address.
The current sample point number refers to any one of all sample points of the data to be decoded.
The current data step refers to a data step corresponding to the current number of sampling points.
The preset rank value refers to a rank value T set in the 3GPP TS 36.212 protocol, for example, T may be 16.
The actual difference value refers to the difference value between the preset row column value and the starting row number.
In implementation, when determining a decoding bit selection address of data to be decoded, first, a first _ column _ element, an increment _ value, and a step of start data of the data to be decoded may be defined. Then, the current data step may be determined based on the current sample number (current _ value) and the adjacent data difference, and the preset row and column value may be obtained, and the difference between the preset row and column value and the starting row, that is, the actual difference, may be determined. Then, it can be determined whether the number of current sampling points is greater than the number of sampling points of the data to be decoded, or whether the current data step is greater than the actual difference plus one. If so, the starting line number may be determined as the solution bit selection address. Otherwise, the data difference between adjacent lines may be updated to be the data difference between adjacent lines minus one. Therefore, the bit decoding selection address is determined based on the current sample point number of the data to be decoded, the current data step and the preset row and column value, the bit decoding selection address of the data to be decoded can be determined in real time, all the bit decoding selection addresses do not need to be stored in advance, and therefore consumption of storage space can be further reduced.
Specifically, taking as an example that first _ column _ element is defined as 1, current _ value is defined as 1, increment _ value is defined as T, step is defined as 1, and the number of samples of data to be decoded is E, first, it may be determined whether current _ value is between 1 and E, that is, whether the current _ value is greater than or equal to E, at this time, since current _ value is defined as 1 to E, current _ value may be updated to 1+ increment _ value, and current step may be updated to step + 1. Thereafter, it may be determined whether the current _ value is less than or equal to E and the current step is less than or equal to T-first _ column _ element + 1. If the current _ value is less than or equal to E and the current step is less than or equal to T-first _ column _ element +1, increment _ value may be updated to current increment _ value-1. If not, that is, if the current _ value is greater than E or the current step is greater than T-first _ column _ element +1, increment _ value ═ T, first _ column _ element ═ first _ column _ element +1, current _ value ═ first _ column _ element, and step ═ 1 may be set, and the current _ value may be determined as the solution bit selection address.
Further, on the basis of the above method embodiment, the modulus of the solution bit selection address may be determined as a solution bit interleaving address, and the corresponding processing of step S102 may be as follows: and determining the modulus of the decoding bit selection address based on the dimension of the data to be decoded, and determining the modulus of the decoding bit selection address as the decoding bit interleaving address of the data to be decoded.
In an implementation, after determining the decoding bit selection address of the data to be decoded, the modulus of the decoding bit selection address may be calculated based on the dimension of the data to be decoded, as may be calculated by the formula addr 0% m-2nAnd calculating, wherein addr0 represents a decoding bit selection address, addr 0% m represents a module of addr0, and n represents the dimension of the data to be decoded. Then, the modulus of the bit decoding selection address of the data to be decoded can be determined as the bit decoding interleaving address of the data to be decoded. In this way, the bit-decoding interleaved address is calculated in real time based on the bit-decoding selection address, and all the bit-decoding interleaved addresses do not need to be stored in advance, so that the consumption of storage space can be further reduced.
Further, on the basis of the above method embodiment, a de-rate address of the data to be decoded may be determined based on the de-bit interleaving address and the decoding parameter corresponding to the dimension of the data to be decoded, and the corresponding processing of step S103 may be as follows: determining a weighted value corresponding to the dimension based on the dimension of the data to be decoded, and determining an intermediate parameter corresponding to the data to be decoded based on the numerical value and the weighted value of the bit interleaving address; and determining a decoding parameter corresponding to the intermediate parameter based on the preset parameter comparison table, and determining a de-rate address of the data to be decoded based on the decoding parameter, the weighted value and the modulus of the de-bit interleaving address.
The weighting value refers to a preset value corresponding to a dimension of the data to be decoded, for example, referring to table 2, table 2 shows different weighting values corresponding to different dimensions.
TABLE 2
| Dimension (d) of | 4 or 5 | 6 | 7 | 8 | 9 | 10 |
| Weighted values | 1 | 2 | 4 | 8 | 16 | 32 |
The intermediate parameter refers to a parameter determined based on a numerical value of a bit-decoding interleaving address and a weighted value corresponding to the dimensionality of the data to be decoded.
The decoding parameters refer to parameters corresponding to the intermediate parameters, which are inquired from a preset parameter comparison table based on the intermediate parameters.
In implementation, after determining the bit-decoding interleaved address of the data to be decoded, first, a weighting value corresponding to a dimension of the data to be decoded may be determined based on the dimension. Then, an intermediate parameter corresponding to the data to be decoded may be determined based on the numerical value of the bit-decoding interleaving address and the weighted value, and specifically, the intermediate parameter may be calculated according to the following formula:
i＝floor(addr1/m)
wherein i represents the intermediate parameter, floor represents rounding-down, addr1 represents the value of the bit interleaving address, and m represents the weighted value corresponding to the intermediate parameter.
After the intermediate parameter is determined, the preset parameter comparison table may be queried according to the intermediate parameter to determine the decoding parameter corresponding to the intermediate parameter based on the preset parameter comparison table, see table 3, where i represents the intermediate parameter and p (i) represents the decoding parameter corresponding to i in table 2.
TABLE 3
| i | p(i) | i | p(i) | i | p(i) | i | p(i) | i | p(i) | i | p(i) | i | p(i) | i | p(i) |
| 0 | 0 | 4 | 3 | 8 | 8 | 12 | 10 | 16 | 12 | 20 | 14 | 24 | 24 | 28 | 27 |
| 1 | 1 | 5 | 5 | 9 | 16 | 13 | 18 | 17 | 20 | 21 | 22 | 25 | 25 | 29 | 29 |
| 2 | 2 | 6 | 6 | 10 | 9 | 14 | 11 | 18 | 13 | 22 | 15 | 26 | 26 | 30 | 30 |
| 3 | 4 | 7 | 7 | 11 | 17 | 15 | 19 | 19 | 21 | 23 | 23 | 27 | 28 | 31 | 31 |
After the decoding parameters are determined, the de-rate address of the data to be decoded can be determined based on the decoding parameters, the weighted values and the modulus of the de-bit interleaving address, and the corresponding calculation formula can be as follows:
addr2＝p(i)*m+addr1％m
wherein addr2 represents the decoding rate address, p (i) represents the decoding parameters, addr 1% m represents the modulus of addr1, and the modulus of addr1 can be determined according to the storage bit width: .
Therefore, the bit interleaving address is calculated in real time based on the bit interleaving address and the decoding parameter, and the real-time calculation of the de-rate address can be realized, so that all rate addresses do not need to be stored in advance, the consumption of storage resources can be further reduced, and the matching efficiency of the de-rate matching is further improved.
Fig. 2 shows a de-rate matching apparatus provided in this embodiment, which includes a selection address determining module 201, an interleaving address determining module 202, and a de-rate matching module 203, where:
the selection address determining module 201 is configured to determine a number of samples of data to be decoded and obtain a preset parameter, and determine a decoding bit selection address based on the number of samples of the data to be decoded and the preset parameter;
the interleaving address determining module 202 is configured to determine a bit decoding interleaving address of the data to be decoded based on the bit decoding selection address and the dimension of the data to be decoded;
the de-rate matching module 203 is configured to determine a de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded, so as to perform de-rate matching based on the de-rate address.
Optionally, the preset parameters include a starting line number, a current sample number, a data difference between adjacent lines, and a data step.
Optionally, the selective address determining module 201 is configured to:
determining the current data stepping based on the number of the current sample points and the data difference value between the adjacent lines, acquiring a preset row and column value, and determining the actual difference value between the preset row and column value and the initial row number;
judging whether the number of current samples is larger than that of the data to be decoded or whether the stepping of the current data is larger than the actual difference value plus one;
and if so, determining the current sampling point number as a solution bit selection address.
Optionally, the interleaving address determining module 202 is configured to:
and determining the modulus of the bit decoding selection address based on the dimension of the data to be decoded, and determining the modulus of the bit decoding selection address as a bit decoding interleaving address of the data to be decoded.
Optionally, the rate de-matching module 203 is configured to:
determining a weighted value corresponding to the dimensionality based on the dimensionality of the data to be decoded, and determining an intermediate parameter corresponding to the data to be decoded based on the numerical value of the bit decoding interleaving address and the weighted value;
and determining a decoding parameter corresponding to the intermediate parameter based on a preset parameter comparison table, and determining a de-rate address of the data to be decoded based on the decoding parameter, the weighted value and a modulus of the de-bit interleaving address.
Optionally, the formula for determining the intermediate parameter corresponding to the data to be decoded based on the dimension of the data to be decoded and the value of the bit interleaving address is as follows:
i＝floor(addr1/m)
wherein i represents the intermediate parameter, floor represents rounding-down, addr1 represents the value of the bit interleaving address, and m represents the weighted value corresponding to the intermediate parameter;
the formula for determining the de-rate address of the data to be decoded based on the decoding parameters, the weighted values and the modulus of the de-bit interleaving address is as follows:
addr2＝p(i)*m+addr1％m
where addr2 represents the decode rate address, p (i) represents the decode parameters, and addr 1% m represents the modulus of addr 1.
The rate de-matching apparatus described in this embodiment may be used to implement the above method embodiments, and the principle and technical effect are similar, which are not described herein again.
Referring to fig. 3, the electronic device includes: a processor (processor)301, a memory (memory)302, and a bus 303;
wherein the content of the first and second substances,
the processor 301 and the memory 302 complete communication with each other through the bus 303;
the processor 301 is configured to call program instructions in the memory 302 to perform the methods provided by the above-described method embodiments.
The present embodiments disclose a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the methods provided by the above-described method embodiments.
The present embodiments provide a non-transitory computer-readable storage medium storing computer instructions that cause the computer to perform the methods provided by the method embodiments described above.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
It should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (14)
1. A method of de-rate matching, comprising:
determining the number of sample points of data to be decoded and acquiring preset parameters, and determining a decoding bit selection address based on the number of sample points of the data to be decoded and the preset parameters;
determining a bit decoding interleaving address of the data to be decoded based on the bit decoding selection address and the dimension of the data to be decoded;
and determining a de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded so as to perform de-rate matching based on the de-rate address.
2. The method of claim 1, wherein the predetermined parameters include a starting number of lines, a current number of samples, a data difference between adjacent lines, and a data step.
3. The method of claim 2, wherein determining a decoding bit selection address based on the number of samples of the data to be decoded and the predetermined parameter comprises:
determining the current data stepping based on the number of the current sample points and the data difference value between the adjacent lines, acquiring a preset row and column value, and determining the actual difference value between the preset row and column value and the initial row number;
judging whether the number of current samples is larger than that of the data to be decoded or whether the stepping of the current data is larger than the actual difference value plus one;
and if so, determining the current sampling point number as a solution bit selection address.
4. The method of claim 1, wherein determining the de-bit interleaved address of the data to be decoded based on the de-bit selection address and the dimension of the data to be decoded comprises:
and determining the modulus of the bit decoding selection address based on the dimension of the data to be decoded, and determining the modulus of the bit decoding selection address as a bit decoding interleaving address of the data to be decoded.
5. The method of claim 1, wherein the determining the de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded comprises:
determining a weighted value corresponding to the dimensionality based on the dimensionality of the data to be decoded, and determining an intermediate parameter corresponding to the data to be decoded based on the numerical value of the bit decoding interleaving address and the weighted value;
and determining a decoding parameter corresponding to the intermediate parameter based on a preset parameter comparison table, and determining a de-rate address of the data to be decoded based on the decoding parameter, the weighted value and a modulus of the de-bit interleaving address.
6. The method according to claim 5, wherein the formula for determining the intermediate parameter corresponding to the data to be decoded based on the dimension of the data to be decoded and the value of the bit interleaving address is as follows:
i＝floor(addr1/m)
wherein i represents the intermediate parameter, floor represents rounding-down, addr1 represents the value of the bit interleaving address, and m represents the weighted value corresponding to the intermediate parameter;
the formula for determining the de-rate address of the data to be decoded based on the decoding parameters, the weighted values and the modulus of the de-bit interleaving address is as follows:
addr2＝p(i)*m+addr1％m
where addr2 represents the decode rate address, p (i) represents the decode parameters, and addr 1% m represents the modulus of addr 1.
7. A de-rate matching apparatus comprising a select address determining module, an interleave address determining module, and a de-rate matching module, wherein:
the selection address determining module is used for determining the number of sample points of the data to be decoded and acquiring a preset parameter, and determining a decoding bit selection address based on the number of sample points of the data to be decoded and the preset parameter;
the interleaving address determining module is used for determining a bit-decoding interleaving address of the data to be decoded based on the bit-decoding selection address and the dimension of the data to be decoded;
and the de-rate matching module is used for determining a de-rate address of the data to be decoded based on the de-bit interleaved address and the dimension of the data to be decoded so as to perform de-rate matching based on the de-rate address.
8. The apparatus of claim 7, wherein the predetermined parameters include a starting number of lines, a current number of samples, a data difference between adjacent lines, and a data step.
9. The de-rate matching device of claim 8, wherein the select address determination module is configured to:
determining the current data stepping based on the number of the current sample points and the data difference value between the adjacent lines, acquiring a preset row and column value, and determining the actual difference value between the preset row and column value and the initial row number;
judging whether the number of current samples is larger than that of the data to be decoded or whether the stepping of the current data is larger than the actual difference value plus one;
and if so, determining the current sampling point number as a solution bit selection address.
10. The de-rate matching device of claim 7, wherein the interleaving address determination module is configured to:
and determining the modulus of the bit decoding selection address based on the dimension of the data to be decoded, and determining the modulus of the bit decoding selection address as a bit decoding interleaving address of the data to be decoded.
11. The de-rate matching device of claim 7, wherein the de-rate matching module is configured to:
determining a weighted value corresponding to the dimensionality based on the dimensionality of the data to be decoded, and determining an intermediate parameter corresponding to the data to be decoded based on the numerical value of the bit decoding interleaving address and the weighted value;
and determining a decoding parameter corresponding to the intermediate parameter based on a preset parameter comparison table, and determining a de-rate address of the data to be decoded based on the decoding parameter, the weighted value and a modulus of the de-bit interleaving address.
12. The apparatus according to claim 11, wherein the formula for determining the intermediate parameter corresponding to the data to be decoded based on the dimension of the data to be decoded and the value of the bit interleaving address is:
i＝floor(addr1/m)
wherein i represents the intermediate parameter, floor represents rounding-down, addr1 represents the value of the bit interleaving address, and m represents the weighted value corresponding to the intermediate parameter;
the formula for determining the de-rate address of the data to be decoded based on the decoding parameters, the weighted values and the modulus of the de-bit interleaving address is as follows:
addr2＝p(i)*m+addr1％m
where addr2 represents the decode rate address, p (i) represents the decode parameters, and addr 1% m represents the modulus of addr 1.
13. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of de-rate matching according to any of claims 1 to 6 when executing the program.
14. A non-transitory computer readable storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the method of de-rate matching according to any of claims 1 to 6.
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