CN105897277B - Decoder decoding performance analysis method and device - Google Patents
Decoder decoding performance analysis method and device Download PDFInfo
- Publication number
- CN105897277B CN105897277B CN201610183746.XA CN201610183746A CN105897277B CN 105897277 B CN105897277 B CN 105897277B CN 201610183746 A CN201610183746 A CN 201610183746A CN 105897277 B CN105897277 B CN 105897277B
- Authority
- CN
- China
- Prior art keywords
- decoder
- time
- subtask
- decoding performance
- shift
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004458 analytical method Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000012360 testing method Methods 0.000 claims abstract description 29
- 238000005457 optimization Methods 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 description 7
- 230000006870 function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000009795 derivation Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- XCWPUUGSGHNIDZ-UHFFFAOYSA-N Oxypertine Chemical compound C1=2C=C(OC)C(OC)=CC=2NC(C)=C1CCN(CC1)CCN1C1=CC=CC=C1 XCWPUUGSGHNIDZ-UHFFFAOYSA-N 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/01—Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/015—Simulation or testing of codes, e.g. bit error rate [BER] measurements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/091—Parallel or block-wise CRC computation
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mobile Radio Communication Systems (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The embodiment of the present invention provides a kind of decoder decoding performance analysis method and device.This method comprises: test decoder interferes the lower first time for executing decoding task at the scene, and execute the second time of the task except decoding task, decoding task includes multiple subtasks, and scene interference is that can lead to the decoder when decoder executes any subtask back to the interference for executing first subtask in the multiple subtask；Test decoder executes the time of each subtask respectively, and each subtask respectively corresponds mobile digit；According to first time, the second time, decoder executes the time of each subtask respectively and each subtask respectively corresponds mobile digit and judges whether decoder meets decoding performance demand；If decoder is unsatisfactory for decoding performance demand, decoder is optimized.The embodiment of the present invention realizes the method in the case where source code is interfered, analyzed the decoding performance of decoder.
Description
Technical Field
The embodiment of the invention relates to the technical field of decoding, in particular to a method and a device for analyzing decoding performance of a decoder.
Background
The transponder system is widely applied to railway systems nowadays, and comprises a ground device and a vehicle-mounted device, wherein the BTM is a core device in the vehicle-mounted device, the core function of the BTM is decoding, and particularly, a decoder of the BTM decodes a TA signal received by the BTM. It has been found that the decoding performance of the decoder is directly related to the noise immunity of the BTM and the maximum speed of the train to which the BTM is applied.
The decoding performance of the decoder may specifically be considered from two aspects: 1) decoding time refers to the time from the time when the decoder receives the correct source code of a frame of message to the time when the decoder finally decodes the legal user message, and the shorter the decoding time is, the better the decoding performance is; 2) the shortest decodable source code length is 1100 bits when the source codes are all good codes, that is, the source codes are not interfered, the shortest decodable source code length of the long packet is 462 bits, but, when the source codes are interfered, the shortest decodable source code length of the long packet is greater than 1100 bits, and the shortest decodable source code length of the short packet is greater than 462 bits, which will cause the decoder not to decode and to have a dead halt state if the shortest decodable source code length is too large.
In the prior art, a large-scale simulation device is used for carrying out a function test on a BTM complete machine, or the decoding performance of a decoder is tested only under the condition that a source code is not interfered, however, under a field test environment, the source code can be interfered in various ways, so that the decoding performance of the decoder is reduced, and a method for analyzing the decoding performance of the decoder under the condition that the source code is interfered is lacked in the prior art.
Disclosure of Invention
The embodiment of the invention provides a method and a device for analyzing decoding performance of a decoder, which are used for analyzing the decoding performance of the decoder under the condition that a source code is interfered.
One aspect of the embodiments of the present invention is to provide a decoding performance analysis method for a decoder, including:
testing a first time when a decoder executes a decoding task under field interference and a second time when a task other than the decoding task is executed, wherein the decoding task comprises a plurality of subtasks, and the field interference is interference which can cause the decoder to return to execute a first subtask in the plurality of subtasks when the decoder executes any subtask;
testing the time of the decoder for executing each subtask, wherein each subtask corresponds to a shift digit, and the shift digit is an update digit of a source code input to the decoder when the decoder fails to execute the subtask under field interference;
judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the time for the decoder to respectively execute each subtask and the number of shift bits corresponding to each subtask respectively;
and if the decoder does not meet the decoding performance requirement, optimizing the decoder.
Another aspect of the embodiments of the present invention is to provide a decoding performance analysis apparatus for a decoder, including:
the device comprises a testing module, a processing module and a processing module, wherein the testing module is used for testing a first time when a decoder executes a decoding task under field interference and a second time when the decoder executes a task except the decoding task, the decoding task comprises a plurality of subtasks, and the field interference is interference which can cause the decoder to return to execute a first subtask in the plurality of subtasks when the decoder executes any subtask; testing the time of the decoder for executing each subtask, wherein each subtask corresponds to a shift digit, and the shift digit is an update digit of a source code input to the decoder when the decoder fails to execute the subtask under field interference;
the judging module is used for judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the time for the decoder to respectively execute each subtask and the number of shift bits corresponding to each subtask;
and the optimization module is used for optimizing the decoder if the decoder does not meet the decoding performance requirement.
According to the method and the device for analyzing the decoding performance of the decoder, whether the decoder meets the decoding performance requirement is judged by testing the first time when the decoder executes the decoding task under the field interference, the second time when the decoder executes the tasks except the decoding task, the time when the decoder executes the subtasks in the decoding task and the moving digit of the source code, and the method for analyzing the decoding performance of the decoder under the condition that the source code is interfered is realized.
Drawings
FIG. 1 is a flowchart of a decoding performance analysis method of a decoder according to an embodiment of the present invention;
FIG. 2 is a flow chart of a decoding task provided by an embodiment of the present invention;
fig. 3 is a block diagram of a decoding performance analysis apparatus of a decoder according to an embodiment of the present invention;
fig. 4 is a block diagram of a decoding performance analysis apparatus of a decoder according to another embodiment of the present invention.
Detailed Description
FIG. 1 is a flowchart of a decoding performance analysis method of a decoder according to an embodiment of the present invention; fig. 2 is a flowchart of a decoding task according to an embodiment of the present invention. The embodiment of the invention provides a decoding performance analysis method of a decoder aiming at the problem that the prior art lacks a method for analyzing the decoding performance of the decoder under the condition that a source code is interfered, and the method comprises the following specific steps:
step S101, testing a first time when a decoder executes a decoding task under field interference and a second time when a task except the decoding task is executed, wherein the decoding task comprises a plurality of subtasks, and the field interference is interference which can cause the decoder to return to execute a first subtask in the plurality of subtasks when the decoder executes any subtask;
fig. 2 is a flowchart illustrating a decoder performing a decoding task and other tasks according to an embodiment of the present invention, which includes the following specific steps:
step 21, the decoder reads the source code through the sliding window;
in the embodiment of the invention, the source code, namely the code to be processed by the decoder is stored in the buffer at the continuous baud rate 564K, the decoder reads the source code from the buffer through the sliding window, and the size of the sliding window is the length of the source code processed by the decoder by executing one decoding task.
Step 22, the decoder judges whether the length of the source code is greater than n + r bits; if yes, go to step 24, otherwise go to step 23;
if the message before decoding is a long message, n is 1023, and r is 77; if the message before decoding is a short message, n is 341 and r is 121.
Step 23, sliding the window to add source codes;
steps 21, 22, 23 are executed in a loop until the length of the source code is greater than n + r bits.
Step 24, the decoder performs CRC on the source code;
step 25, the decoder judges whether the CRC check passes; if yes, go to step 27, otherwise go to step 26;
step 26, moving the sliding window by n1 bits, and returning to step 21;
for example, if the sliding window has 1100 bit source codes before the step, n1 bit unprocessed source codes are newly added after the 1100 bit source codes, and at the same time, the 1 st bit to n1 bit source codes are shifted out of the sliding window, if the processed source codes are arranged in the cache before and the unprocessed source codes are arranged behind, the step of processing is performed by n1 bits under the condition that the size of the sliding window is kept unchanged.
Step 27, the decoder performs n + r check on the source code;
step 28, judging whether the n + r check passes, if so, executing step 30, otherwise, executing step 29;
step 29, moving the sliding window by n2 bits, and returning to step 21;
the same process is performed in step 26, which is not described herein again.
Step 30, the decoder detects a synchronous value for the source code;
step 31, the decoder judges whether the synchronous value is legal; if yes, go to step 33, otherwise go to step 32;
step 32, moving the sliding window by n3 bits, and returning to step 21;
step 33, the decoder checks the source code for validity;
step 34, the decoder judges whether all bits are legal; if yes, executing step 36, otherwise, executing step 35;
step 35, moving the sliding window by n4 bits, and returning to the step 21;
step 36, the decoder checks whether the source code needs to be reversed, and if the source code needs to be reversed, the source code is reversed;
step 37, the decoder checks the control bit in the source code;
step 38, the decoder judges whether the control bit is legal; if yes, go to step 40, otherwise go to step 39;
step 39, moving the sliding window by n5 bits, and returning to step 21;
step 40, the decoder inverts and descrambles the source code to obtain a legal message and inverted bits;
step 41, the sliding window moves by n6 bits, and the step 21 is returned.
As shown in fig. 2, the decoding task executed by the decoder includes a plurality of subtasks, and preferably, the embodiment of the present invention provides 6 steps, specifically, the first subtask taking steps 21 to 26 as the decoding task is the first step, the second subtask taking steps 27 to 29 as the decoding task is the second step, the third subtask taking steps 30 to 32 as the decoding task is the third step, the fourth subtask taking steps 33 to 35 as the decoding task is the fourth step, the fifth subtask taking steps 36 to 39 as the decoding task is the fifth step, and the sixth subtask taking step 40 as the decoding task is the sixth step.
The site interference is the interference experienced by the source code, which site interference may cause the decoder to return to performing the first step, preferably, the presence of the disturbance may cause the decoder to return to performing the first step when performing any of the first, second, third and fourth steps, the first time the decoder performs a decoding task under the presence of the disturbance being the time from the start of step 21 to step 40, the first time is denoted as T, which may be the sum of T1, T2, T3, T4, T5, T6, the addition of t1, t2, t3, t4, t5 or t6 which may be integer multiples is also carried out from the beginning of step 21 to the process of step 40, the first step, the second step, the third step, the fourth step, the fifth step or the sixth step is performed a plurality of times. The decoder in the embodiment of the present invention may perform not only the decoding task but also other tasks, and the decoder may perform a plurality of tasks in parallel or in series, and the decoding performance analysis method of the decoder provided in the embodiment of the present invention is suitable for both the parallel execution manner and the series execution manner, and preferably, taking the series execution of the plurality of tasks as an example, the decoder has already performed a plurality of other tasks before performing the decoding task, and the execution time is denoted as a second time and denoted by t0, as shown in fig. 2.
Step S102, testing the time of the decoder for respectively executing each subtask, wherein each subtask corresponds to a shift digit, and the shift digit is an update digit of a source code input to the decoder when the decoder fails to execute the subtask under field interference;
as can be seen from fig. 2, the time for the decoder to execute the first step is t1, the time for continuously executing the first step and the second step is t2, the time for continuously executing the first step, the second step and the third step is t3, the time for continuously executing the first step, the second step, the third step and the fourth step is t4, the time for continuously executing the first step, the second step, the third step, the fourth step and the fifth step is t5, the time for continuously executing the first step, the second step, the third step, the fourth step, the fifth step and the sixth step is t6, and if the decoder fails to execute each subtask, the number of bits of the source code input to the decoder needs to be updated, specifically, when the decoder fails to execute the first step, the number of bits of the source code input to the decoder is updated to n1, that is, the sliding window moves n1 bits; when the decoder fails to execute the second step, updating the number of the source codes input into the decoder to be n2, namely, sliding window moving n2 bits; when the decoder fails to execute the third step, updating the number of the source codes input into the decoder to be n3, namely, sliding window moving n3 bits; when the decoder fails to execute the fourth step, updating the bit number of the source code input into the decoder to be n4, namely, moving the sliding window by n4 bits; when the decoder fails to execute the fifth step, updating the number of the source codes input into the decoder to be n5, namely, sliding window moving n5 bits; after the decoder performs the sixth step, the number of bits of the source code input to the decoder is updated to n6, i.e. the sliding window is moved by n6 bits.
Step S103, judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the time for the decoder to respectively execute each subtask and the number of shift bits corresponding to each subtask respectively;
specifically, whether the decoder meets the decoding performance requirement is judged according to the first time T, the second time T0, the time T1, T2, T3, T4, T5 and T6 when the decoder respectively executes each subtask, and the number of shift bits n1, n2, n3, n4, n5 and n6 corresponding to each subtask.
Judging whether the decoder meets the decoding performance requirement or not if the decoder meets the decoding performance requirement If yes, the decoder meets the decoding performance requirement; if it is If at least one of the first and second decoders fails, the decoder is determined not to meet the decoding performance requirement.
Wherein, the derivation of (c) is illustrated in the following examples.
And step S104, if the decoder does not meet the decoding performance requirement, optimizing the decoder.
If it is If at least one of the above methods fails, the decoder needs to be optimized to improve the anti-interference performance of the decoder, and the specific optimization method will be described in the following embodiments.
The embodiment of the invention judges whether the decoder meets the decoding performance requirement or not by testing the first time when the decoder executes the decoding task under the field interference, the second time when the decoder executes the task except the decoding task, the time when the decoder executes the subtask in the decoding task and the moving digit of the source code, thereby realizing the method for analyzing the decoding performance of the decoder under the condition that the source code is interfered.
On the basis of the foregoing embodiment, the determining whether the decoder meets the decoding performance requirement according to the first time, the second time, the time when the decoder executes each sub-task, and the number of shift bits corresponding to each sub-task, respectively, includes: and judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the third time for the decoder to execute the first subtask, the fourth time for the decoder to continuously execute the first subtask and the second subtask, the first shift digit corresponding to the first subtask and the second shift digit corresponding to the second subtask.
In the actual testing process, because the existence of the field interference causes the decoder to have a higher probability of failing to execute the first step and the second step in fig. 2, and if the decoder has succeeded in executing both the first step and the second step, the probability of failing to execute the third step and the subsequent steps is very low, therefore, the embodiment of the present invention mainly considers the case that the decoder fails to execute the first step and the second step in fig. 2, and preferably, the embodiment of the present invention judges whether the decoder meets the decoding performance requirement according to the first time T, the second time T0, the time T1 for the decoder to execute the first subtask, the time T2 for the decoder to execute the second subtask, the number of shift bits n1 corresponding to the first subtask, and the number of shift bits n2 corresponding to the second subtask.
The method for judging whether the decoder meets the decoding performance requirement comprises the following steps: determining whether the first time, the second time, the third time, and the first number of shift bits satisfy formula (1):
wherein T represents the first time, T0 represents the second time, T1 represents the third time, n1 represents the first number of shift bits;
determining whether the first time, the second time, the fourth time, and the second number of shift bits satisfy formula (2):
wherein t2 represents the fourth time, n2 represents the second number of shift bits;
if the formula (1) and the formula (2) are simultaneously established, determining that the decoder meets the decoding performance requirement;
determining that the decoder does not meet the decoding performance requirement if at least one of equation (1) and equation (2) fails.
The derivation processes of the formula (1) and the formula (2) will be described in the following examples.
Detailed description of embodiments of the invention The derivation process comprises the following steps:
since the source codes are stored in the buffer at the sustained baud rate 564K, the newly added source codes to be processed in the buffer have (T + T0)/(1000/564) bits of (T + T0)/1.77 bits in the time T + T0. Assuming that x1 bit source codes do not pass through the (T + T0)/1.77 bit source codes to be processed in the first step, x2 bit source codes do not pass through the second step, x3 bit source codes do not pass through the third step, x4 bit source codes do not pass through the fourth step, x5 bit source codes do not pass through the fifth step, x6 bit source codes pass through the first step to the fifth step, and according to the fact that the processing time of the decoder on newly added source codes is less than or equal to the first time T of the decoder for executing decoding task under field interference, the formula (3) is established:
according to the fact that the total number of bits of the source codes processed by the decoder at one time is larger than the number of the newly increased source codes in one period time, the formula (4) is established:
suppose thatIt is true that the first and second sensors,will be provided withSubstituting formula (3) results in formula (5):
from equations (4) and (5), equation (6) can be derived:
as can be seen from equation (6), when t0 is equal to 0,namely, it isWhen t0 ≠ 0,that is, the formula (1)
In addition, due toIs established, then Both are true.
According to It can be seen that how many bits the decoder moves per step depends on the processing time of each step and the processing time of other tasks than the decoding task. When in use When the two steps are simultaneously satisfied, the decoder meets the decoding performance requirement under the field interference, and the probability that the decoder fails to execute the first step and the second step in the figure 2 is higher due to the field interference, so that only the decoder needs to execute the first step and the second step And meanwhile, when the situation is met, the decoder can meet the decoding performance requirement under the field interference.
The embodiment of the invention details the condition that the decoder meets the decoding performance requirement under the field interference and the specific expression of the condition, thereby providing a foundation for the analysis of the subsequent decoding performance and the optimization of the decoder.
On the basis of any of the above embodiments, the embodiment of the present invention describes a method for optimizing the decoder, specifically: if the decoder does not meet the decoding performance requirement, optimizing the decoder, including: if the decoder does not meet the decoding performance requirement, reducing second time for the decoder to execute tasks except the decoding task; or if the decoder does not meet the decoding performance requirement, reducing the third time for the decoder to execute the first subtask or reducing the fourth time for the decoder to execute the second subtask.
Detailed description of embodiments of the inventionA method. In the case where the decoder has a high probability of failure in performing the first step and the second step of fig. 2, if at least one of the formula (1) and the formula (2) is not satisfied, it is determined that the decoder does not satisfy the decoding performance requirement, assuming that the decoder does not satisfy the decoding performance requirementIf the condition is not satisfied,is established, then in order toIt is preferable that the second time t0 when the decoder performs a task other than the decoding task may be reduced, and the embodiment of the present invention does not limit the method of reducing t 0. In addition, t1 can be reduced, and the embodiment of the present invention does not limit the method for reducing t 1. In the same way, forIt is true that the first and second sensors,if this is not the case, a reduction of t0 or t2 may be considered. For theIf the condition is not satisfied,this is not the case, and it is contemplated to reduce t0, or reduce t1 and t2 simultaneously, or reduce t0, t1 and t2 simultaneously.
Or, if the decoder does not meet the decoding performance requirement, optimizing the decoder, including: calculating a first moving digit with the minimum value meeting the formula (1) according to the first time, the second time and the third time, and modifying the first moving digit corresponding to the first subtask into the first moving digit with the minimum value; or calculating a second shift digit with the minimum value meeting the formula (2) according to the first time, the second time and the fourth time, and modifying the second shift digit corresponding to the second subtask to the second shift digit with the minimum value.
In the embodiment of the invention, the minimum n1 value meeting the formula (1) can be calculated according to the first time T, the second time T0 and the third time T1 obtained by testing and is recorded as min (n1), min (n1) and n1 in fig. 2 are compared, and if min (n1) is larger than n1 and min (n1) is within an acceptable range, n1 in fig. 2 is modified into min (n 1). Similarly, the smallest n2 value satisfying the formula (2) can be calculated according to the first time T, the second time T0 and the fourth time T2 obtained by the test and is recorded as min (n2), min (n2) and n2 in fig. 2 are compared, and if min (n2) is larger than n2 and min (n2) is within the acceptable range, n2 in fig. 2 is modified into min (n 2).
The embodiment of the invention provides a method for optimizing a decoder according to the condition that the decoder meets the decoding performance requirement under the field interference.
Fig. 3 is a block diagram of a decoding performance analysis apparatus of a decoder according to an embodiment of the present invention. As shown in fig. 3, the decoder decoding performance analysis apparatus 30 includes a test module 31, a determination module 32, and an optimization module 33, where the test module 31 is configured to test a first time when a decoder executes a decoding task under field interference and a second time when a task other than the decoding task is executed, where the decoding task includes a plurality of sub tasks, and the field interference is interference that when the decoder executes any sub task, the decoder may return to execute a first sub task of the plurality of sub tasks; testing the time of the decoder for executing each subtask, wherein each subtask corresponds to a shift digit, and the shift digit is an update digit of a source code input to the decoder when the decoder fails to execute the subtask under field interference; the judging module 32 is configured to judge whether the decoder meets the decoding performance requirement according to the first time, the second time, the time for the decoder to respectively execute each subtask, and the shift digit corresponding to each subtask; the optimization module 33 is configured to optimize the decoder if the decoder does not meet the decoding performance requirement.
The embodiment of the invention judges whether the decoder meets the decoding performance requirement or not by testing the first time when the decoder executes the decoding task under the field interference, the second time when the decoder executes the task except the decoding task, the time when the decoder executes the subtask in the decoding task and the moving digit of the source code, thereby realizing the method for analyzing the decoding performance of the decoder under the condition that the source code is interfered.
Fig. 4 is a block diagram of a decoding performance analysis apparatus of a decoder according to another embodiment of the present invention. On the basis of the foregoing embodiment, the determining module 32 is specifically configured to determine whether the decoder meets the decoding performance requirement according to the first time, the second time, the third time for the decoder to execute the first sub-task, the fourth time for the decoder to continuously execute the first sub-task and the second sub-task, the first shift bit number corresponding to the first sub-task, and the second shift bit number corresponding to the second sub-task.
The judging module 32 includes a first judging unit 321, a second judging unit 322, and a determining unit 323, wherein the first judging unit 321 is configured to judge whether the first time, the second time, the third time, and the first number of shift bits satisfy formula (1):
wherein T represents the first time, T0 represents the second time, T1 represents the third time, n1 represents the first number of shift bits;
the second determining unit 322 is configured to determine whether the first time, the second time, the fourth time, and the second number of shift bits satisfy formula (2):
wherein t2 represents the fourth time, n2 represents the second number of shift bits;
the determining unit 323 is configured to determine that the decoder meets the decoding performance requirement if the formula (1) and the formula (2) are satisfied simultaneously; determining that the decoder does not meet the decoding performance requirement if at least one of equation (1) and equation (2) fails.
The optimization module 33 is specifically configured to reduce a second time for the decoder to execute a task other than the decoding task if the decoder does not meet the decoding performance requirement; or if the decoder does not meet the decoding performance requirement, reducing the third time for the decoder to execute the first subtask or reducing the fourth time for the decoder to execute the second subtask.
Or the optimization module 33 is specifically configured to calculate a minimum first shift digit satisfying the formula (1) according to the first time, the second time, and the third time, and modify the first shift digit corresponding to the first subtask to the minimum first shift digit; or calculating a second shift digit with the minimum value meeting the formula (2) according to the first time, the second time and the fourth time, and modifying the second shift digit corresponding to the second subtask to the second shift digit with the minimum value.
The decoder decoding performance analysis apparatus provided in the embodiment of the present invention may be specifically configured to execute the method embodiment provided in fig. 1, and specific functions are not described herein again.
The embodiment of the invention details the condition that the decoder meets the decoding performance requirement under the field interference and the specific expression of the condition, thereby providing a basis for the analysis of the subsequent decoding performance and the optimization of the decoder; a method for optimizing a decoder is provided according to the condition that the decoder meets the decoding performance requirement under field interference.
In summary, the embodiment of the present invention determines whether the decoder meets the decoding performance requirement by testing the first time when the decoder executes the decoding task under the field interference, the second time when the decoder executes the task other than the decoding task, the time when the decoder executes the subtask in the decoding task, and the number of the shift bits of the source code, so as to implement a method for analyzing the decoding performance of the decoder under the condition that the source code is interfered; detailing the condition that the decoder meets the decoding performance requirement under the field interference and a specific expression of the condition, and providing a foundation for the analysis of the subsequent decoding performance and the optimization of the decoder; a method for optimizing a decoder is provided according to the condition that the decoder meets the decoding performance requirement under field interference.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
It is obvious to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be performed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to perform all or part of the above described functions. For the specific working process of the device described above, reference may be made to the corresponding process in the foregoing method embodiment, which is not described herein again.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. A method for analyzing decoding performance of a decoder, comprising:
testing a first time when a decoder executes a decoding task under field interference and a second time when a task other than the decoding task is executed, wherein the decoding task comprises a plurality of subtasks, and the field interference is interference which can cause the decoder to return to execute a first subtask in the plurality of subtasks when the decoder executes any subtask;
testing the time of the decoder for executing each subtask, wherein each subtask corresponds to a shift digit, and the shift digit is an update digit of a source code input to the decoder when the decoder fails to execute the subtask under field interference;
judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the time for the decoder to respectively execute each subtask and the number of shift bits corresponding to each subtask respectively;
if the decoder does not meet the decoding performance requirement, optimizing the decoder;
the determining whether the decoder meets the decoding performance requirement according to the first time, the second time, the time for the decoder to respectively execute each subtask, and the number of shift bits corresponding to each subtask respectively includes:
judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the third time for the decoder to execute the first subtask, the fourth time for the decoder to continuously execute the first subtask and the second subtask, the first shift digit corresponding to the first subtask and the second shift digit corresponding to the second subtask;
the determining whether the decoder meets the decoding performance requirement according to the first time, the second time, the third time for the decoder to execute the first subtask, the fourth time for the decoder to continuously execute the first subtask and the second subtask, the first shift bit number corresponding to the first subtask, and the second shift bit number corresponding to the second subtask includes:
determining whether the first time, the second time, the third time, and the first number of shift bits satisfy formula (1):
wherein T represents the first time, T0 represents the second time, T1 represents the third time, n1 represents the first number of shift bits;
determining whether the first time, the second time, the fourth time, and the second number of shift bits satisfy formula (2):
wherein t2 represents the fourth time, n2 represents the second number of shift bits;
if the formula (1) and the formula (2) are simultaneously established, determining that the decoder meets the decoding performance requirement;
determining that the decoder does not meet the decoding performance requirement if at least one of equation (1) and equation (2) fails.
2. The method of claim 1, wherein optimizing the decoder if the decoder does not meet decoding performance requirements comprises:
if the decoder does not meet the decoding performance requirement, reducing second time for the decoder to execute tasks except the decoding task; or
If the decoder does not meet the decoding performance requirement, reducing a third time for the decoder to execute the first subtask or reducing a fourth time for the decoder to execute the second subtask.
3. The method of claim 1, wherein optimizing the decoder if the decoder does not meet decoding performance requirements comprises:
calculating a first moving digit with the minimum value meeting the formula (1) according to the first time, the second time and the third time, and modifying the first moving digit corresponding to the first subtask into the first moving digit with the minimum value; or
And calculating a second moving digit with the minimum value meeting the formula (2) according to the first time, the second time and the fourth time, and modifying the second moving digit corresponding to the second subtask to the second moving digit with the minimum value.
4. An apparatus for analyzing decoding performance of a decoder, comprising:
the device comprises a testing module, a processing module and a processing module, wherein the testing module is used for testing a first time when a decoder executes a decoding task under field interference and a second time when the decoder executes a task except the decoding task, the decoding task comprises a plurality of subtasks, and the field interference is interference which can cause the decoder to return to execute a first subtask in the plurality of subtasks when the decoder executes any subtask; testing the time of the decoder for executing each subtask, wherein each subtask corresponds to a shift digit, and the shift digit is an update digit of a source code input to the decoder when the decoder fails to execute the subtask under field interference;
the judging module is used for judging whether the decoder meets the decoding performance requirement or not according to the first time, the second time, the time for the decoder to respectively execute each subtask and the number of shift bits corresponding to each subtask;
an optimization module, configured to optimize the decoder if the decoder does not meet the decoding performance requirement;
the judging module is specifically configured to judge whether the decoder meets the decoding performance requirement according to the first time, the second time, a third time for the decoder to execute the first subtask, a fourth time for the decoder to continuously execute the first subtask and the second subtask, a first shift bit number corresponding to the first subtask, and a second shift bit number corresponding to the second subtask;
the judging module comprises:
a first judging unit configured to judge whether the first time, the second time, the third time, and the first number of shift bits satisfy formula (1):
wherein T represents the first time, T0 represents the second time, T1 represents the third time, n1 represents the first number of shift bits;
a second determination unit, configured to determine whether the first time, the second time, the fourth time, and the second number of shift bits satisfy formula (2):
wherein t2 represents the fourth time, n2 represents the second number of shift bits;
a determining unit, configured to determine that the decoder meets the decoding performance requirement if equation (1) and equation (2) are satisfied simultaneously; determining that the decoder does not meet the decoding performance requirement if at least one of equation (1) and equation (2) fails.
5. The apparatus according to claim 4, wherein the optimization module is specifically configured to reduce a second time for the decoder to perform the task other than the decoding task if the decoder does not satisfy the decoding performance requirement; or if the decoder does not meet the decoding performance requirement, reducing the third time for the decoder to execute the first subtask or reducing the fourth time for the decoder to execute the second subtask.
6. The decoding performance analysis device of claim 4, wherein the optimization module is specifically configured to calculate a minimum first shift digit satisfying formula (1) according to the first time, the second time, and the third time, and modify the first shift digit corresponding to the first subtask to the minimum first shift digit; or calculating a second shift digit with the minimum value meeting the formula (2) according to the first time, the second time and the fourth time, and modifying the second shift digit corresponding to the second subtask to the second shift digit with the minimum value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610183746.XA CN105897277B (en) | 2016-03-28 | 2016-03-28 | Decoder decoding performance analysis method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610183746.XA CN105897277B (en) | 2016-03-28 | 2016-03-28 | Decoder decoding performance analysis method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105897277A CN105897277A (en) | 2016-08-24 |
| CN105897277B true CN105897277B (en) | 2019-06-14 |
Family
ID=57014565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610183746.XA Active CN105897277B (en) | 2016-03-28 | 2016-03-28 | Decoder decoding performance analysis method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105897277B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1620760A (en) * | 2001-12-21 | 2005-05-25 | 数字方敦股份有限公司 | Multi-stage code generator and decoder for communication systems |
| CN104796156A (en) * | 2014-01-20 | 2015-07-22 | 联想(北京)有限公司 | LDPC (low density parity check) decoder and LDPC decoding method |
| CN105247808A (en) * | 2013-03-07 | 2016-01-13 | 马维尔国际贸易有限公司 | Systems and methods for decoding with late reliability information |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101526317B1 (en) * | 2008-05-09 | 2015-06-11 | 삼성전자주식회사 | Hierarchical decoding apparatus |
-
2016
- 2016-03-28 CN CN201610183746.XA patent/CN105897277B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1620760A (en) * | 2001-12-21 | 2005-05-25 | 数字方敦股份有限公司 | Multi-stage code generator and decoder for communication systems |
| CN105247808A (en) * | 2013-03-07 | 2016-01-13 | 马维尔国际贸易有限公司 | Systems and methods for decoding with late reliability information |
| CN104796156A (en) * | 2014-01-20 | 2015-07-22 | 联想(北京)有限公司 | LDPC (low density parity check) decoder and LDPC decoding method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105897277A (en) | 2016-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11379555B2 (en) | Dilated convolution using systolic array | |
| US20200322238A1 (en) | Distributed assignment of video analytics tasks in cloud computing environments to reduce bandwidth utilization | |
| US11734007B2 (en) | Address generation method, related apparatus, and storage medium | |
| CN107240396B (en) | Speaker self-adaptation method, device, equipment and storage medium | |
| CN105700956A (en) | Distributed job processing method and system | |
| CN112035066B (en) | Log reservation time length calculation method and device | |
| US8899343B2 (en) | Replacing contiguous breakpoints with control words | |
| CN117435855B (en) | Method for performing convolution operation, electronic device, and storage medium | |
| CN111401518A (en) | Neural network quantization method and device and computer readable storage medium | |
| CN104021226A (en) | Method and device for updating prefetch rule | |
| CN116451174A (en) | Task execution device, method, electronic device, and storage medium | |
| CN105897277B (en) | Decoder decoding performance analysis method and device | |
| KR102151364B1 (en) | Animation creation method and device | |
| US10477245B2 (en) | Methods and devices for coding and decoding depth information, and video processing and playing device | |
| JP5922848B2 (en) | Determining a unified user identifier for visiting users | |
| CN111158907A (en) | Data processing method and device, electronic equipment and storage medium | |
| CN115495153A (en) | Calculation acceleration method, system, equipment and storage medium | |
| CN110990852B (en) | Big data security protection method and device, server and readable storage medium | |
| CN113744744A (en) | Audio coding method and device, electronic equipment and storage medium | |
| CN107450968B (en) | Load reduction method, device and equipment | |
| US20150195551A1 (en) | Programmable variable block size motion estimation processor | |
| CN110647998B (en) | Method, system, device and storage medium for implementing automatic machine learning | |
| CN114816032B (en) | Data processing method and device, electronic equipment and storage medium | |
| US12067266B1 (en) | CXL HDM decoding sequencing for reduced area and power consumption | |
| CN111176583B (en) | Data writing method and device and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |